diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 8e798269b..72163fdf7 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,13 +9,13 @@ on: jobs: # Linux - job_linux_18_04_64_gcc: - name: ubuntu-18.04 gcc - runs-on: ubuntu-18.04 + job_linux_20_04_64_gcc: + name: ubuntu-20.04 gcc + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Install dependencies + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -29,13 +29,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_18_04_32_gcc: - name: ubuntu-18.04 gcc 32-bit - runs-on: ubuntu-18.04 + job_linux_20_04_32_gcc: + name: ubuntu-20.04 gcc 32-bit + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Install dependencies + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -54,13 +54,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_18_04_64_clang: - name: ubuntu-18.04 clang - runs-on: ubuntu-18.04 + job_linux_20_04_64_clang: + name: ubuntu-20.04 clang + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Install dependencies + run: sudo apt update && sudo apt-get install clang-12 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -74,13 +74,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_18_04_32_clang: - name: ubuntu-18.04 clang 32-bit - runs-on: ubuntu-18.04 + job_linux_20_04_32_clang: + name: ubuntu-20.04 clang 32-bit + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-12 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -99,13 +99,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_20_04_64_gcc: - name: ubuntu-20.04 gcc - runs-on: ubuntu-20.04 + job_linux_22_04_64_gcc: + name: ubuntu-22.04 gcc + runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -119,13 +119,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_20_04_32_gcc: - name: ubuntu-20.04 gcc 32-bit - runs-on: ubuntu-20.04 + job_linux_22_04_32_gcc: + name: ubuntu-22.04 gcc 32-bit + runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -144,13 +144,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_20_04_64_clang: - name: ubuntu-20.04 clang - runs-on: ubuntu-20.04 + job_linux_22_04_64_clang: + name: ubuntu-22.04 clang + runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-14 libusb-1.0.0-dev libgtk-4-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -164,13 +164,13 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean - job_linux_20_04_32_clang: - name: ubuntu-20.04 clang 32-bit - runs-on: ubuntu-20.04 + job_linux_22_04_32_clang: + name: ubuntu-22.04 clang 32-bit + runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-14 libusb-1.0.0-dev libgtk-4-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -190,13 +190,13 @@ jobs: run: sudo make uninstall && sudo make clean # Linux MinGW cross compliation -# job_linux_20_04_cross: -# name: ubuntu-20.04 mingw64 -# runs-on: ubuntu-20.04 +# job_linux_22_04_cross: +# name: ubuntu-22.04 mingw64 +# runs-on: ubuntu-22.04 # steps: # - uses: actions/checkout@v2 # - name: Install dependencies -# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 +# run: sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm mingw-w64 # - name: Building Release for Windows (x86-64) ... # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ # -DCMAKE_SYSTEM_NAME=Windows \ diff --git a/CHANGELOG.md b/CHANGELOG.md index 82656d50b..551a4ba09 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,7 +17,7 @@ Features: - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) -- [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) +- STM32H72X/3X: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173), [#1273](https://github.com/stlink-org/stlink/pull/1273)) - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) @@ -31,7 +31,7 @@ Features: Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) -- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216)) +- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216), [#1228](https://github.com/stlink-org/stlink/pull/1228)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) @@ -44,14 +44,17 @@ Updates & changes: - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) -- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) +- End of support for macOS ([#1269](https://github.com/stlink-org/stlink/pull/1269), [#1296](https://github.com/stlink-org/stlink/pull/1296), commit [#61ff09e](https://github.com/stlink-org/stlink/commit/61ff09e5274d46a46ae58bc4ffe44fe90a887ea6)) +- [doc] Added device ID for GD32F303VET6 ([#1288](https://github.com/stlink-org/stlink/pull/1288)) Fixes: + - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) -- Set of fixes and improvements ([#1154](https://github.com/stlink-org/stlink/pull/1154)) +- Set of fixes and improvements ([#1153](https://github.com/stlink-org/stlink/pull/1153), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) - Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) - Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) @@ -64,13 +67,15 @@ Fixes: - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) -- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) -- st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) +- General fixes and improvements ([#1240](https://github.com/stlink-org/stlink/pull/1240), [#1242](https://github.com/stlink-org/stlink/pull/1242), [#1290](https://github.com/stlink-org/stlink/pull/1290), [#1291](https://github.com/stlink-org/stlink/pull/1291), [#1295](https://github.com/stlink-org/stlink/pull/1295)) +- Fixes for project compilation ([#1241](https://github.com/stlink-org/stlink/pull/1241), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) +- st-trace: Fixed clock issues ([#1248](https://github.com/stlink-org/stlink/pull/1248), [#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) -- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) -- Fixes for project compilation ([#1270](https://github.com/stlink-org/stlink/pull/1270), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) +- Fixed incorrect SRAM size for L496x and L4A6x ([#1268](https://github.com/stlink-org/stlink/pull/1268), commit [#ff81148](https://github.com/stlink-org/stlink/commit/ff8114895a9fc32cae6a9374e58eac6256d68183)) +- Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) @@ -84,7 +89,7 @@ Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) - Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7d8bce8cf..4ce0ee126 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,8 +78,8 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") -set(CMAKE_INSTALL_SHAREDIR /usr/share/) +message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") +set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) ## Set C build flags diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 55a859189..57d4803d7 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -48,7 +48,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.13.0), libusb-1.0-0-dev (>= 1.0.22)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 2ed3b6b11..7c2ab8fe7 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) +Build-Depends: cmake (>= 3.13.0), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.22), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.6.2 Rules-Requires-Root: no Section: electronics diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index f817175f4..e90f4a78e 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB -option_base 0x40023C14 -option_size 0x4 +option_base 0x40023C14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo diff --git a/config/chips/F446.chip b/config/chips/F446.chip index e4d0bdec2..25f22d9b6 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -10,5 +10,5 @@ sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x10 // 16 B flags swo diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index a414b52ab..2010940c7 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -10,5 +10,5 @@ sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 bootrom_size 0x2000 // 8 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index ae074e584..ba556b53a 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32G05x / STM32G06x device # dev_type STM32G05x_G06x -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x456 // STM32_CHIPID_G0_CAT4 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x4800 // 18 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 82b3992c2..60a6bec7a 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,7 +1,7 @@ # Chip-ID file for STM32G07x / STM32G08x device # dev_type STM32G07x_G08x -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x460 // STM32_CHIPID_G0_CAT2 flash_type G0 flash_size_reg 0x1fff75e0 @@ -10,5 +10,5 @@ sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index f21fd65a0..a9bae1f08 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32G0Bx / STM32G0Cx device # dev_type STM32G0Bx_G0Cx -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x467 // STM32_CHIPID_G0_CAT3 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x24000 // 144 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags dualbank diff --git a/config/chips/H5xx.chip b/config/chips/H5xx.chip new file mode 100644 index 000000000..a1c438999 --- /dev/null +++ b/config/chips/H5xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32H5xx device +# +dev_type STM32H5xx +ref_manual_id 0481 +chip_id 0x484 // STM32_CHIPID_H5xx +flash_type L5_U5 // ? +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0xa0000 // 640 KB +bootrom_base 0x0bf80000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags dualbank diff --git a/config/chips/L5x5xx.chip b/config/chips/L5x5xx.chip new file mode 100644 index 000000000..0f205a62b --- /dev/null +++ b/config/chips/L5x5xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L5x2xx device +# +dev_type STM32L5x2xx +ref_manual_id 0438 +chip_id 0x472 // STM32_CHIPID_L5x2xx +flash_type L5_U5 +flash_size_reg 0x0bfa05e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags dualbank diff --git a/config/chips/U5x5.chip.txt b/config/chips/U5x5.chip similarity index 61% rename from config/chips/U5x5.chip.txt rename to config/chips/U5x5.chip index 177359cc3..5f71436ef 100644 --- a/config/chips/U5x5.chip.txt +++ b/config/chips/U5x5.chip @@ -2,14 +2,13 @@ # dev_type STM32U5x5 ref_manual_id 0456 -chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +chip_id 0x482 // STM32_CHIPID_U5x5 +flash_type L5_U5 flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB bootrom_base 0x0bf90000 -bootrom_size 0x8000 // 32 KB +bootrom_size 0x10000 // 64 KB option_base 0x0 option_size 0x0 flags none - diff --git a/doc/devices_boards.md b/doc/devices_boards.md deleted file mode 100644 index 13aa0361a..000000000 --- a/doc/devices_boards.md +++ /dev/null @@ -1,207 +0,0 @@ -# MCUs supported by the STlink toolset - -The following devices are supported by the stlink toolset. - -## STM32F0 / ARM Cortex M0 - -| Chip-ID | Product-Code | -| ------- | ------------------- | -| 0x440 | STM32F0**30**x**8** | -| 0x442 | STM32F0**30**x**C** | -| 0x444 | STM32F0**3**xx**4** | -| 0x444 | STM32F0**3**xx**6** | -| 0x445 | STM32F0**4**xxx | -| 0x440 | STM32F0**5**xxx | -| 0x445 | STM32F0**70**x**6** | -| 0x448 | STM32F0**70**x**B** | -| 0x448 | STM32F0**71**xx | -| 0x448 | STM32F0**72**xx | -| 0x442 | STM32F0**9**xxx | - - -## STM32F1 / ARM Cortex M3 - -| Product-Code | Product Line | -| ----------------- | ----------------------- | -| STM32F10**0**yyxx | Value line (V) | -| STM32F10**1**yyxx | Access line (A) | -| STM32F10**2**yyxx | USB Access line (USB-A) | -| STM32F10**3**yyxx | Performance line (P) | -| STM32F10**5**yyxx | Connectivity line (C) | -| STM32F10**7**yyxx | Connectivity line (C) | - -| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | -| ------- | -------------------- | --------- | ---- | ---- | ----- | ---- | -------------- | -| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | -| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | -| 0x414 | High density | xC xD xE | | F101 | F103 | | | -| 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
F107 | -| 0x420 | Medium density value | x8 xB | F100 | | | | | -| 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF xG | | F101 | | F103 | | - -Tested non-official ST boards [incl. STLINK programmers]: - -- HY-STM32 (STM32F103VETx) [v1, v2] -- DecaWave EVB1000 (STM32F105RCTx) [v1, v2] - -## STM32F2 / ARM Cortex M3 - -| Chip-ID | Product-Code | Product Line | -| ------- | ------------ | ------------- | -| 0x411 | STM32F2yyxx | (all devices) | - -## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] - -| Product-Code | Chip-ID | STLink
Programmer | Boards | -| ------------- | ------- | ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------ | -| CKS32F103C8Tx | 0x410 | v2 | STM32F103C8T6 clone from China Key Systems (CKS) either as
CKS32-Bluepill or even as "STM32"-Bluepill with _**Fake-Marking !**_ | - -## STM32F3 / ARM Cortex M4F - -| Product-Code | Product Line | -| ----------------- | ------------------------------------------------------------- | -| STM32F3**01**yyxx | Access line (A) | -| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | -| STM32F3**03**yyxx | Performance line (P) | -| STM32F3**34**yy | Digital Power line (DP) | -| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | -| STM32F3**18**yy | General Purpose line (GP) 64k/16k | -| STM32F3**28**yy | General Purpose line (GP) 64k/16k | -| STM32F3**58**yy | General Purpose line (GP) 265k/48k | -| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | -| STM32F3**98**yy | General Purpose line (GP) 512k/80k | - -| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | -| ------- | ------------ | --------- | ---- | ------- | ---- | -------------- | -| 0x422 | _N/A_ | xB xC | | F302 | F303 | | -| 0x422 | _N/A_ | - | | | | F358 | -| 0x432 | _N/A_ | - | | | | F373
F378 | -| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | -| 0x438 | _N/A_ | - | | | | F334
F328 | -| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | -| 0x439 | _N/A_ | - | | | | F318 | -| 0x446 | _N/A_ | xD xE | | F302 | F303 | | -| 0x446 | _N/A_ | - | | | | F398 | - -## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!] - -| Product-Code | Chip-ID | STLINK
Programmer | Boards | -| ------------ | ------- | ---------------------- | ---------------------------------- | -| GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -| GD32F303VET6 | 0x414 | [v2] | STM32F303 clone from GigaDevice GD | -| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | - -## STM32F4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | ------------------- | -| 0x413 | STM32F4**0**xxx | -| 0x413 | STM32F4**1**xxx | -| 0x419 | STM32F4**2**xxx | -| 0x419 | STM32F4**3**xxx | -| 0x423 | STM32F4**01**x**B** | -| 0x423 | STM32F4**01**x**C** | -| 0x433 | STM32F4**01**x**D** | -| 0x433 | STM32F4**01**x**E** | -| 0x458 | STM32F4**10**xx | -| 0x431 | STM32F4**11**xx | -| 0x441 | STM32F4**12**xx | -| 0x421 | STM32F4**46**xx | -| 0x434 | STM32F4**69**xx | -| 0x434 | STM32F4**79**xx | -| 0x463 | STM32F4**13**xx | -| 0x463 | STM32F4**23**xx | - -## STM32F7 / ARM Cortex M7F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x452 | STM32F7**2**xxx | -| 0x452 | STM32F7**3**xxx | -| 0x449 | STM32F7**4**xxx | -| 0x449 | STM32F7**5**xxx | -| 0x451 | STM32F7**6**xxx | -| 0x451 | STM32F7**7**xxx | - -## STM32H7 / ARM Cortex M7F - -| Chip-ID | Product-Code | -| ------- | ------------- | -| 0x450 | STM32H7**4**x | -| 0x450 | STM32H7**5**x | -| 0x480 | STM32H7**A**x | -| 0x480 | STM32H7**B**x | - -## STM32G0 / ARM Cortex M0+ - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x466 | STM32G0**3**xxx | -| 0x466 | STM32G0**4**xxx | -| 0x460 | STM32G0**7**xxx | -| 0x460 | STM32G0**8**xxx | - -## STM32G4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x468 | STM32G4**31**xx | -| 0x468 | STM32G4**41**xx | -| 0x469 | STM32G4**7**xxx | -| 0x469 | STM32G4**8**xxx | -| 0x479 | STM32G4**91**xx | - -## STM32L0 / ARM Cortex M0+ - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x457 | STM32L0**1**xxx | -| 0x457 | STM32L0**2**xxx | -| 0x425 | STM32L0**31**xx | -| 0x425 | STM32L0**41**xx | -| 0x417 | STM32L0**5**xxx | -| 0x417 | STM32L0**6**xxx | -| 0x447 | STM32L0**7**xxx | -| 0x447 | STM32L0**8**xxx | - -## STM32L1 / ARM Cortex M3 - -| Chip-ID | Product-Code | -| ------- | ---------------- | -| 0x416 | STM32L1xxx**6** | -| 0x416 | STM32L1xxx**8** | -| 0x416 | STM32L1xxx**B** | -| 0x429 | STM32L1xxx**6A** | -| 0x429 | STM32L1xxx**8A** | -| 0x429 | STM32L1xxx**BA** | -| 0x427 | STM32L1xxx**C** | -| 0x436 | STM32L1xxx**D** | -| 0x437 | STM32L1xxx**E** | - -## STM32L4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x464 | STM32L4**12**xx | -| 0x464 | STM32L4**22**xx | -| 0x435 | STM32L4**3**xxx | -| 0x435 | STM32L4**4**xxx | -| 0x462 | STM32L4**5**xxx | -| 0x462 | STM32L4**6**xxx | -| 0x415 | STM32L4**7**xxx | -| 0x415 | STM32L4**8**xxx | -| 0x461 | STM32L4**96**xx | -| 0x461 | STM32L4**A6**xx | -| 0x470 | STM32L4**R**xx | -| 0x470 | STM32L4**S**xx | -| 0x471 | STM32L4**P5**xx | -| 0x471 | STM32L4**Q5**xx | - -## STM32W / ARM Cortex M3 - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x495 | STM32WB**50**xx | -| 0x495 | STM32WB**55**xx | -| 0x497 | STM32WLE**5**xx | diff --git a/doc/supported devices.md b/doc/supported devices.md new file mode 100644 index 000000000..2e96dcd39 --- /dev/null +++ b/doc/supported devices.md @@ -0,0 +1,59 @@ +# MCUs supported by the STlink toolset + +A list of devices supported by the stlink toolset can be found in */inc/stm32.h*. +More commonly these are: + +| Product-Family | ARM Cortex Core | Product Line | +| -------------- | --------------- | ---------------------------------------------------------- | +| STM32F0 | M0 | | +| STM32G0 | M0+ | | +| STM32L0 | M0+ | | +| STM32F10**0** | M3 | Value line | +| STM32F10**1** | M3 | Access line | +| STM32F10**2** | M3 | USB Access line | +| STM32F10**3** | M3 | Performance line | +| STM32F10**5** | M3 | Connectivity line | +| STM32F10**7** | M3 | Connectivity line | +| STM32L1 | M3 | | +| STM32F2 | M3 | | +| STM32F3**01** | M4F | Access line | +| STM32F3**02** | M4F | USB & CAN line | +| STM32F3**03** | M4F | Performance line | +| STM32F3**34** | M4F | Digital Power line | +| STM32F3**73** | M4F | Precision Measurement line (64k/16k / 128k/24k / 265k/32k) | +| STM32F3**18** | M4F | General Purpose line (64k/16k) | +| STM32F3**28** | M4F | General Purpose line (64k/16k) | +| STM32F3**58** | M4F | General Purpose line (265k/48k) | +| STM32F3**78** | M4F | Precision Measurement line (265k/32k) | +| STM32F3**98** | M4F | General Purpose line (512k/80k) | +| STM32F4 | M4F | | +| STM32G4 | M4F | | +| STM32L4 | M4F | | +| STM32F7 | M4F | | +| STM32H7 | M4F | | +| STM32WB | M4F | | +| STM32WL | M4 | | + + +# Chinese Clone-Chips [may work, but without support!] + +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) (mostly on Bluepill-Boards) + +**(!) Attention:** Some MCUs may come with with _**Fake-STM32-Marking !**_ + +**(!) Attention:** The Core-ID of these MCUs is in conflict with the one of the original STM32F1-devices. + +| Product-Code | Chip-ID | Comment | +| ------------- | ------- | ------------------------------------------------------------------------- | +| CKS32F103C8T6 | 0x410 | STM32F103C8T6 clone from China Key Systems (CKS) | +| CH32F103C8T6 | 0x410 | STM32F103C8T6 clone from Nanjing Qinheng Microelectronics Co., Ltd. (WCH) | + +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) + +**(!) Attention:** The Chip-IDs of these MCUs are in conflict with such of original STM32F1-devices. + +| Product-Code | Chip-ID | Comment | +| ------------ | ------- | ------------------------------------ | +| GD32F303VET6 | 0x414 | STM32F303 clone from GigaDevice (GD) | +| GD32F303CGT6 | 0x430 | STM32F303 clone from GigaDevice (GD) | +| GD32F303VGT6 | 0x430 | STM32F303 clone from GigaDevice (GD) | diff --git a/doc/version_support.md b/doc/version_support.md index 593c86549..358e65fb9 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,10 +1,10 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk (as of Apr 2023) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake **3.10.2** or any later version is installed.
+On Windows users should ensure that cmake **3.13.0** or any later version is installed.
Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 @@ -21,6 +21,7 @@ Maintained versions of: - Arch Linux - FreeBSD - NetBSD +- OpenBSD Other Linux-/Unix-based Operating Systems: @@ -59,43 +60,41 @@ Other Linux-/Unix-based Operating Systems: | Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | | Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | | Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | | Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | -## Unsupported Operating Systems (as of Release v1.7.1) +## Unsupported Operating Systems (as of Release v1.8.0) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
OS-Support | -| ------------------------- | ------------------------------ | ---------- | ---------------------- | -| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | -| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | -| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Operating System | libusb | cmake | End of
OS-Support | +| ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| CentOS / Rocky Linux / AlmaLinux 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | +| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.21 | 3.**17.0** | Dec 2022 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.21 | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.21 | 3.10.2 | Apr 2023 | +| openSUSE Leap 15.1 [x64] | 1.0.21 | 3.10.2 | Jan 2021 | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS / Rocky Linux / AlmaLinux 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stm32.h b/inc/stm32.h index 856d6e4bd..d3c4e5512 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -10,8 +10,8 @@ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0444 Section 40.5.3) G0 SW-DP + // (RM0377 Section 27.5.3) L0 SW-DP STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP @@ -29,9 +29,15 @@ enum stm32_core_id { STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG // (RM0090 Section 47.6.3) G4 JTAG STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + // (RM0473 Section 33.4.4) WB SW-DP + // (RM0453 Section 38.4.1) WL SW-DP STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG - STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG + STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG + // (RM0433 Section 60.4.1) H7 JTAG + // (RM0473 Section 33.4.1) WB JTAG + // (RM0453 Section 38.3.8) WL JTAG STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP // (RM0456 Section 65.3.3) U5 SW-DP STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP @@ -106,20 +112,23 @@ enum stm32_chipids { STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L011 = 0x457, STM32_CHIPID_F410 = 0x458, - STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, STM32_CHIPID_L45x_L46x = 0x462, STM32_CHIPID_F413 = 0x463, STM32_CHIPID_L41x_L42x = 0x464, - STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G0_CAT1 = 0x466, /* G03x/G04x */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0Bx/G0Cx */ STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */ STM32_CHIPID_G4_CAT4 = 0x479, STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */ STM32_CHIPID_WB55 = 0x495, STM32_CHIPID_WLE = 0x497, }; @@ -196,10 +205,16 @@ enum stm32_chipids { #define STM32L1_RCC_AHBENR 0x4002381C #define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN +#define STM32L5_RCC_AHB1ENR 0x40021048 // RM0438, p. 91,377 +#define STM32L5_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN // RM0438, p. 378 + #define STM32H7_RCC_AHB1ENR 0x58024538 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define STM32WB_RCC_AHB1ENR 0x58000048 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 +#define STM32L5_PWR_CR1_VOS 9 + #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 5e7ad2e4a..07f824837 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -72,7 +72,7 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 -// Flash registers common to STM32G0 and STM32G4 series. +// Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) #define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) #define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) @@ -207,6 +207,43 @@ #define STM32L4_FLASH_OPTR_DUALBANK 21 +// Flash registers common to STM32L5 series (RM0438, p. 241) +#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00) +#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08) +#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10) +#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20) +#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28) +#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30) +#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40) + +// FLASH_NSCR (RM0438, p. 242) +#define STM32L5_FLASH_NSCR_NSPG 0 /* Program */ +#define STM32L5_FLASH_NSCR_NSPER 1 /* Page erase */ +#define STM32L5_FLASH_NSCR_NSMER1 2 /* Bank 1 erase */ +#define STM32L5_FLASH_NSCR_NSPNB 3 /* Page number (7 bits) */ +#define STM32L5_FLASH_NSCR_NSBKER 11 /* Bank select for page erase */ +#define STM32L5_FLASH_NSCR_NSMER2 15 /* Bank 2 erase */ +#define STM32L5_FLASH_NSCR_NSSTRT 16 /* Start command */ +#define STM32L5_FLASH_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ +#define STM32L5_FLASH_NSCR_NSEOPIE 24 +#define STM32L5_FLASH_NSCR_NSERRIE 25 +#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ +#define STM32L5_FLASH_NSCR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L5_FLASH_NSCR_NSLOCK 31 /* Lock control register */ + +// FLASH_NSSR (RM0438, p. 241) +#define STM32L5_FLASH_NSSR_NSEOP 0 /* End of Operation */ +#define STM32L5_FLASH_NSSR_NSOPERR 1 +#define STM32L5_FLASH_NSSR_NSPROGERR 3 +#define STM32L5_FLASH_NSSR_NSWRPERR 4 +#define STM32L5_FLASH_NSSR_NSPGAERR 5 +#define STM32L5_FLASH_NSSR_NSSIZERR 6 +#define STM32L5_FLASH_NSSR_NSPGSERR 7 +#define STM32L5_FLASH_NSSR_OPTWERR 12 +#define STM32L5_FLASH_NSSR_BSY 16 /* Busy */ +#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa) + // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 4b8e37fef..3b25dc214 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -169,7 +169,10 @@ int main(int ac, char** av) { printf("Unknown memory region\n"); goto on_error; } + } else if (o.cmd == FLASH_CMD_ERASE) { + + // erase if (o.size > 0 && o.addr > 0) { err = stlink_erase_flash_section(sl, o.addr, o.size, false); } else { @@ -179,11 +182,16 @@ int main(int ac, char** av) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } + printf("Mass erase completed successfully.\n"); + } else if (o.cmd == CMD_RESET) { + + // reset if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); goto on_error; } + } else { // read @@ -254,6 +262,7 @@ int main(int ac, char** av) { if (o.reset) { stlink_reset(sl, RESET_AUTO); + stlink_run(sl, RUN_NORMAL); } err = 0; // success diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index d2edf0d9f..fb4478bdc 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -24,19 +24,12 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) set(GUI_SOURCES gui.c gui.h) - ## stlink-gui-local - add_executable(stlink-gui-local ${GUI_SOURCES}) - file(COPY stlink-gui.ui DESTINATION ${CMAKE_BINARY_DIR}/bin) - set_target_properties(stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_BINARY_DIR}/bin") - target_link_libraries(stlink-gui-local ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) + install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) endif () endif () diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 34a8ac573..e7c2392c1 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -62,6 +62,7 @@ void stlink_close(stlink_t *sl) { sl->backend->close(sl); free(sl); } + // 250 int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); @@ -74,11 +75,13 @@ int stlink_exit_debug_mode(stlink_t *sl) { return (sl->backend->exit_debug_mode(sl)); } + //248 int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); return (sl->backend->enter_swd_mode(sl)); } + // 271 // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { @@ -91,11 +94,13 @@ int stlink_force_debug(stlink_t *sl) { stop_wdg_in_debug(sl); return (0); } + // 251 int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); return (sl->backend->exit_dfu_mode(sl)); } + // 253 int stlink_core_id(stlink_t *sl) { int ret; @@ -115,6 +120,7 @@ int stlink_core_id(stlink_t *sl) { DLOG("core_id = 0x%08x\n", sl->core_id); return (ret); } + // 287 // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. @@ -132,10 +138,9 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { /* * the chip_id register in the reference manual have * DBGMCU_IDCODE / DBG_IDCODE name - * */ - if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_M33_SWD || sl->core_id == STM32_CORE_ID_M7F_M33_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); @@ -178,6 +183,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { return (ret); } + // 288 /** * Cortex M tech ref manual, CPUID register description @@ -201,6 +207,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { cpuid->revision = raw & 0xf; return (0); } + // 303 /** * Reads and decodes the flash parameters, as dynamically as possible @@ -272,8 +279,7 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } @@ -286,6 +292,15 @@ int stlink_load_device_params(stlink_t *sl) { } } + if (sl->chip_id == STM32_CHIPID_L5x2xx) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32L5_FLASH_OPTR, &flash_optr); + + if (sl->flash_size == 512*1024 && (flash_optr & (1 << 22)) != 0) { + sl->flash_pgsz = 0x800; + } + } + // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -300,6 +315,7 @@ int stlink_load_device_params(stlink_t *sl) { return (0); } + // 254 int stlink_reset(stlink_t *sl, enum reset_type type) { uint32_t dhcsr; @@ -334,11 +350,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { dhcsr = 0; int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); + // reset not done yet --> try reset through AIRCR so that NRST does not need to be connected + ILOG("NRST is not connected --> using software reset via AIRCR\n"); + DLOG("NRST not connected --> Reset through SYSRESETREQ\n"); return stlink_soft_reset(sl, 0); } @@ -361,6 +375,81 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return (0); } + +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } + + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } + + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } + + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + + return (0); +} + // 255 int stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; @@ -377,11 +466,13 @@ int stlink_run(stlink_t *sl, enum run_type type) { return (sl->backend->run(sl, type)); } + // 273 int stlink_set_swdclk(stlink_t *sl, int freq_khz) { DLOG("*** set_swdclk ***\n"); return (sl->backend->set_swdclk(sl, freq_khz)); } + // 293 // this function is called by stlink_status() // do not call stlink_core_stat() directly, always use stlink_status() @@ -403,6 +494,7 @@ void stlink_core_stat(stlink_t *sl) { DLOG(" core status: unknown\n"); } } + // 256 int stlink_status(stlink_t *sl) { int ret; @@ -412,6 +504,7 @@ int stlink_status(stlink_t *sl) { stlink_core_stat(sl); return (ret); } + // 257 int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version ***\n"); @@ -435,6 +528,7 @@ int stlink_version(stlink_t *sl) { return (0); } + // 272 int stlink_target_voltage(stlink_t *sl) { int voltage = -1; @@ -454,16 +548,19 @@ int stlink_target_voltage(stlink_t *sl) { return (voltage); } + // 299 bool stlink_is_core_halted(stlink_t *sl) { stlink_status(sl); return (sl->core_stat == TARGET_HALTED); } + // 269 int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); return (sl->backend->step(sl)); } + // 270 int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); @@ -483,20 +580,24 @@ int stlink_current_mode(stlink_t *sl) { DLOG("stlink mode: unknown!\n"); return (STLINK_DEV_UNKNOWN_MODE); } + // 274 int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); return (sl->backend->trace_enable(sl, frequency)); } + // 275 int stlink_trace_disable(stlink_t *sl) { DLOG("*** stlink_trace_disable ***\n"); return (sl->backend->trace_disable(sl)); } + // 276 int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { return (sl->backend->trace_read(sl, buf, size)); } + // 294 void stlink_print_data(stlink_t *sl) { if (sl->q_len <= 0 || sl->verbose < UDEBUG) { @@ -523,9 +624,9 @@ void stlink_print_data(stlink_t *sl) { // DLOG("\n\n"); fprintf(stderr, "\n"); } + // 283 -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { // write the file in sram at addr int error = -1; @@ -581,6 +682,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, on_error: return (error); } + //284 int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr @@ -655,9 +757,9 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { unmap_file(&mf); return (error); } + // 302 -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file ILOG("read from address %#010x size %u\n", addr, (unsigned)size); @@ -689,9 +791,9 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, close(fd); return (error); } + // 300 -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader int ret = 0; size_t chunk = size & ~0x3; @@ -709,6 +811,7 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, return (ret); } + // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || @@ -749,6 +852,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { return ((uint32_t)sl->flash_pgsz); } + // 279 int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, size_t *size, uint32_t *begin) { @@ -910,6 +1014,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, return (res); } + // 280 uint8_t stlink_get_erased_pattern(stlink_t *sl) { if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { @@ -1024,79 +1129,6 @@ int stlink_jtag_reset(stlink_t *sl, int value) { return (sl->backend->jtag_reset(sl, value)); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} /** * Decode the version bits, originally from -sg, verified with usb * @param sl stlink context, assumed to contain valid data in the buffer @@ -1283,8 +1315,7 @@ static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, } static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; + struct stlink_fread_worker_arg *the_arg = (struct stlink_fread_worker_arg *)arg; if (write(the_arg->fd, block, len) != len) { fprintf(stderr, "write() != aligned_size\n"); @@ -1315,8 +1346,7 @@ static uint8_t stlink_parse_hex(const char *hex) { return ((d[0] << 4) | (d[1])); } -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { uint32_t addr = the_arg->addr; uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); @@ -1330,8 +1360,7 @@ stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { return (true); } -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { uint8_t count = the_arg->buf_pos; if (count == 0) { @@ -1399,8 +1428,7 @@ static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { return (true); } -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { if (!stlink_fread_ihex_writeline(the_arg)) { return (false); } diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 0ed4734ad..000f9279d 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -38,15 +38,17 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + reg = STM32L5_FLASH_NSCR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + reg = STM32WB_FLASH_CR; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -60,7 +62,7 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { } void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { @@ -76,21 +78,24 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } @@ -118,21 +123,23 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_reg = STM32L5_FLASH_NSSR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; } else { ELOG("method 'write_flash_sr' is unsupported\n"); return (-1); @@ -156,6 +163,12 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; + case STM32_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; case STM32_FLASH_TYPE_L0_L1: if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); @@ -166,11 +179,8 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STM32_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } + case STM32_FLASH_TYPE_L5_U5: + write_flash_sr(sl, BANK_1, STM32L5_FLASH_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); @@ -186,21 +196,23 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_reg = STM32L5_FLASH_NSSR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; } else { ELOG("method 'read_flash_sr' is unsupported\n"); return (-1); @@ -222,15 +234,17 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_busy_shift = STM32L5_FLASH_NSSR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; } else { ELOG("method 'is_flash_busy' is unsupported\n"); return (-1); @@ -286,6 +300,13 @@ int check_flash_error(stlink_t *sl) { PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; + case STM32_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1); if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { @@ -303,12 +324,11 @@ int check_flash_error(stlink_t *sl) { PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STM32_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); + case STM32_FLASH_TYPE_L5_U5: + res = read_flash_sr(sl, BANK_1) & STM32L5_FLASH_NSSR_ERROR_MASK; + WRPERR = (1 << STM32L5_FLASH_NSSR_NSWRPERR); + PROGERR = (1 << STM32L5_FLASH_NSSR_NSPROGERR); + PGAERR = (1 << STM32L5_FLASH_NSSR_NSPGAERR); break; case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; @@ -357,22 +377,25 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return (-1); @@ -400,22 +423,31 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) + uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); + uint32_t val; + if (!stlink_read_debug32(sl, STM32L5_PWR_CR1, &val) && (val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { + val &= ~mask; + stlink_write_debug32(sl, STM32L5_PWR_CR1, val); + } + key_reg = STM32L5_FLASH_NSKEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + key_reg = STM32WB_FLASH_KEYR; } else { ELOG("unsupported flash method, abort\n"); return; @@ -464,6 +496,17 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -472,21 +515,14 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + case STM32_FLASH_TYPE_L5_U5: + optcr_reg = STM32L5_FLASH_NSCR; + optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -537,6 +573,15 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -545,19 +590,14 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + case STM32_FLASH_TYPE_L5_U5: + optcr_reg = STM32L5_FLASH_NSCR; + optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -590,6 +630,15 @@ static int unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; @@ -598,18 +647,12 @@ static int unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_L4: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; + case STM32_FLASH_TYPE_L5_U5: + optkey_reg = STM32L5_FLASH_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STM32_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; default: ELOG("unsupported flash method, abort\n"); return (-1); @@ -672,16 +715,18 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; } else { cr_reg = FLASH_CR; } @@ -693,7 +738,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; - fprintf(stdout, "Mass erasing"); + fprintf(stdout, "Mass erasing..."); fflush(stdout); while (is_flash_busy(sl)) { @@ -744,6 +789,8 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { @@ -761,6 +808,8 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { @@ -796,19 +845,22 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_strt = (1 << STM32L5_FLASH_NSCR_NSSTRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); @@ -830,28 +882,30 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_mer = (1 << STM32L5_FLASH_NSCR_NSMER1) | (1 << STM32L5_FLASH_NSCR_NSMER2); + cr_pg = (1 << STM32L5_FLASH_NSCR_NSPG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_mer = (1 << FLASH_CR_MER); @@ -993,25 +1047,16 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { + if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1027,6 +1072,34 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + uint32_t flash_page; + stlink_read_debug32(sl, STM32L5_FLASH_NSCR, &val); + if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { + flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / + (uint32_t)(sl->flash_pgsz); + // set bank 2 for erasure + val |= (1 << STM32L5_FLASH_NSCR_NSBKER); + } else { + flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + // set bank 1 for erasure + val &= ~(1 << STM32L5_FLASH_NSCR_NSBKER); + } + // sec 6.9.9 + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32L5_FLASH_NSCR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index d9542ebbc..4adf93a86 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -46,14 +46,12 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); break; } if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading + // show progress; writing procedure is slow and previous errors are misleading fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } @@ -84,6 +82,9 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -136,6 +137,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32L0_RCC_DMAEN; } break; + case STM32_FLASH_TYPE_L5_U5: + rcc = STM32L5_RCC_AHB1ENR; + rcc_dma_mask = STM32L5_RCC_DMAEN; + break; case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; @@ -216,8 +221,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { set_flash_cr_pg(sl, BANK_1); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -320,14 +326,15 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(off / sl->flash_pgsz + 1), (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } @@ -368,7 +375,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(off / sl->flash_pgsz + 1), (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } @@ -451,11 +458,12 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || (sl->flash_type == STM32_FLASH_TYPE_G0) || (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7)) { + (sl->flash_type == STM32_FLASH_TYPE_H7) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); if ((sl->flash_type == STM32_FLASH_TYPE_H7 && diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index ee690e0b1..3777f720b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -33,9 +33,9 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__OpenBSD__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (__linux__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (_WIN32) #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 3d332f49d..32becc5cf 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -242,8 +242,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { int err = -1; for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); if (err == -1) { return err; } else { @@ -272,8 +271,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t // Clear errors clear_flash_error(sl); - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), addr); write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); @@ -306,8 +304,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t ret = check_flash_error(sl); if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, addr); /* option bytes are reloaded at reset only, no obl. */ @@ -510,8 +507,7 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); @@ -534,8 +530,7 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t /* Check for errors */ if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); return -1; } break; @@ -753,8 +748,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui int ret = -1; if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); + ELOG("Option bytes writing is currently not supported for connected chip\n"); return (-1); } @@ -771,8 +765,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return (-1); } @@ -809,8 +802,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui ret = stlink_write_option_bytes_wb(sl, addr, base, len); break; default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + ELOG("Option bytes writing is currently not implemented for connected chip\n"); break; } @@ -892,8 +884,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -915,8 +906,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { stlink_write_option_control_register_wb(sl, option_cr); break; default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); + ELOG("Option control register writing is currently not implemented for connected chip\n"); break; } @@ -965,8 +955,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -1050,8 +1039,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { */ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); + ELOG("Option bytes boot address read is currently not supported for connected chip\n"); return -1; } @@ -1076,8 +1064,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -1091,8 +1078,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); + ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); break; }