diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
index b663dd84da426b..4d1a215ab184fc 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
@@ -8,7 +8,7 @@
 	ahb {
 		apb {
 			i2c: i2c@1e78a040 {
-				i2c0: i2c-bus@0x40 {
+				i2c0: i2c-bus@40 {
 					eeprom@50 {
 						compatible = "atmel,24c256";
 						reg = <0x50>;
@@ -25,7 +25,7 @@
 					};
 				};
 
-				i2c6: i2c-bus@0x1C0 {
+				i2c6: i2c-bus@1c0 {
 					nct7904@2d {
 						compatible = "nuvoton,nct7904";
 						reg = <0x2d>;
diff --git a/arch/arm/mach-aspeed/aspeed.c b/arch/arm/mach-aspeed/aspeed.c
index 9d106b857fbd03..46bc7f53d3847e 100644
--- a/arch/arm/mach-aspeed/aspeed.c
+++ b/arch/arm/mach-aspeed/aspeed.c
@@ -124,12 +124,35 @@ static void udbg_uart_putc(char c)
 	udbg_uart_out(UART_THR, c);
 }
 
+void aspeed_dump_scu(void)
+{
+	int i;
+
+	for (i = 0; i <= 0xE4; i+=4) {
+		if (i == 0x78 || i == 0xE0 || i == 0xE4)
+			continue;
+		printk("SCU %03x  %08x\n", i,
+			readl(AST_IO(AST_BASE_SCU | i)));
+	}
+
+	printk("SCU %02x  %08x\n", 0x160, readl(AST_IO(AST_BASE_SCU | 0x160)));
+
+	for (i = 0x180; i <= 0x19C; i+=4)
+		printk("SCU %02x  %08x\n", i,
+			readl(AST_IO(AST_BASE_SCU | i)));
+
+	printk("SCU %02x  %08x\n", 0x1a4, readl(AST_IO(AST_BASE_SCU | 0x1a4)));
+}
+EXPORT_SYMBOL_GPL(aspeed_dump_scu);
+
 #define SCU_PASSWORD	0x1688A8A8
 
 static void __init aspeed_init_early(void)
 {
 	u32 reg;
 
+	aspeed_dump_scu();
+
 	// XXX UART stuff to fix to pinmux & co
 	printk("UART IO MUX...\n");
 	writel(0x02010023, AST_IO(AST_BASE_LPC | 0x9c));
@@ -159,6 +182,16 @@ static void __init aspeed_init_early(void)
 	udbg_uart_putc('O');
 	udbg_uart_putc('O');
 	udbg_uart_putc('\n');
+
+	/*
+	 * temporary: enable i2c usage of the shared GPIO/I2C pins for
+	 * i2c busses 4 - 8
+	 */
+	reg = readl(AST_IO(AST_BASE_SCU | 0x90));
+	reg |= 0x3E0000;
+	writel(reg, AST_IO(AST_BASE_SCU | 0x90));
+
+	aspeed_dump_scu();
 }
 
 static void __init aspeed_map_io(void)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index 9b82420f902542..806a63b4141c9c 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -43,11 +43,25 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
 
 #define	WDT_RESTART_MAGIC	0x4755
 
+static void aspeed_wdt_dump_regs(struct aspeed_wdt *wdt)
+{
+	printk("WDT_STATUS: %p %08x\n", wdt->base + WDT_STATUS,
+			readl(wdt->base + WDT_STATUS));
+	printk("WDT_RELOAD_VALUE: %p %08x\n", wdt->base + WDT_RELOAD_VALUE,
+			readl(wdt->base + WDT_RELOAD_VALUE));
+	printk("WDT_RESTART: %p %08x\n", wdt->base + WDT_RESTART,
+			readl(wdt->base + WDT_RESTART));
+	printk("WDT_CTRL: %p %08x\n", wdt->base + WDT_CTRL,
+			readl(wdt->base + WDT_CTRL));
+}
+
 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
 {
 	u32 ctrl = WDT_CTRL_RESET_MODE_FULL_CHIP | WDT_CTRL_RESET_SYSTEM |
 		WDT_CTRL_ENABLE;
 
+	printk("%s\n", __func__);
+
 	writel(0, wdt->base + WDT_CTRL);
 	writel(count, wdt->base + WDT_RELOAD_VALUE);
 	writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
@@ -94,12 +108,17 @@ static int aspeed_wdt_restart(struct notifier_block *nb, unsigned long action,
 	struct aspeed_wdt *wdt = container_of(nb,
 			struct aspeed_wdt, restart_nb);
 
+	printk("%s\n", __func__);
+	aspeed_wdt_dump_regs(wdt);
+
 	/*
 	 * Trigger watchdog bite:
 	 *    Setup reload count to be 128ms, and enable WDT.
 	 */
 	aspeed_wdt_enable(wdt, 128 * wdt->rate / 1000);
 
+	aspeed_wdt_dump_regs(wdt);
+
 	return NOTIFY_DONE;
 }
 
diff --git a/init/main.c b/init/main.c
index 9e64d7097f1ad4..a0bba5974a5d6d 100644
--- a/init/main.c
+++ b/init/main.c
@@ -88,6 +88,8 @@
 #include <asm/sections.h>
 #include <asm/cacheflush.h>
 
+extern void aspeed_dump_scu(void);
+
 static int kernel_init(void *);
 
 extern void init_IRQ(void);
@@ -679,6 +681,8 @@ asmlinkage __visible void __init start_kernel(void)
 
 	ftrace_init();
 
+	aspeed_dump_scu();
+
 	/* Do the rest non-__init'ed, we're now alive */
 	rest_init();
 }