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vga.c
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vga.c
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// Halfix generic VGA emulator
// http://www.osdever.net/FreeVGA/vga/portidx.htm
// ftp://ftp.apple.asimov.net/pub/apple_II/documentation/hardware/video/Second%20Sight%20VGA%20Registers.pdf
// The ET4000 manual (on archive.org)
// https://01.org/sites/default/files/documentation/ilk_ihd_os_vol3_part1r2_0.pdf
// https://ia801809.us.archive.org/11/items/bitsavers_ibmpccardseferenceManualMay92_1756350/IBM_VGA_XGA_Technical_Reference_Manual_May92.pdf
// https://www-user.tu-chemnitz.de/~kzs/tools/whatvga/vga.txt
// https://wiki.osdev.org/Bochs_VBE_Extensions
#include "cpuapi.h"
#include "devices.h"
#include "display.h"
#include "io.h"
#include "state.h"
#include <string.h>
#define VGA_LOG(x, ...) LOG("VGA", x, ##__VA_ARGS__)
#define VGA_FATAL(x, ...) \
do { \
VGA_LOG(x, ##__VA_ARGS__); \
abort(); \
} while (0)
#define VBE_LFB_BASE 0xE0000000
static struct vga_info {
// <<< BEGIN STRUCT "struct" >>>
/// ignore: framebuffer, vram, scanlines_modified, scanlines_to_update, mem, rom, rom_size
// CRT Controller
uint8_t crt[256], crt_index;
// Attribute Controller
uint8_t attr[32], attr_index, attr_palette[16];
// Sequencer
uint8_t seq[8], seq_index;
// Graphics Registers
uint8_t gfx[256], gfx_index;
// Digital To Analog
uint8_t dac[1024];
uint32_t dac_palette[256];
uint8_t dac_mask,
dac_state, // 0 if reading, 3 if writing
dac_address, // Index into dac_palette
dac_color, // Current color being read (0: red, 1: blue, 2: green)
dac_read_address // same as dac_address, but for reads
;
// Status stuff
uint8_t status[2];
// Miscellaneous Graphics Register
uint8_t misc;
// Text Mode Rendering variables
uint8_t char_width;
uint32_t character_map[2];
// General rendering variables
uint8_t pixel_panning, current_pixel_panning;
uint32_t total_height, total_width;
int renderer;
uint32_t current_scanline, character_scanline;
uint32_t* framebuffer; // where pixel data is written to, created by SDL
uint32_t framebuffer_offset; // the offset being written to right now
uint32_t vram_addr; // Current VRAM offset being accessed by renderer
uint32_t scanlines_to_update; // Number of scanlines to update per vga_update
// Memory access settings
uint8_t write_access, read_access, write_mode;
uint32_t vram_window_base, vram_window_size;
union {
uint8_t latch8[4];
uint32_t latch32;
};
// VBE stuff
uint16_t vbe_index, vbe_version, vbe_enable;
uint32_t vbe_regs[10];
uint32_t vbe_bank;
// PCI VGA stuff
uint32_t vgabios_addr;
uint8_t* mem;
int vram_size;
uint8_t *vram, *rom;
uint32_t rom_size;
// <<< END STRUCT "struct" >>>
// These fields should not be saved in the VRAM savestate since they have to do with rendering.
uint8_t* vbe_scanlines_modified;
// Screen data cannot change if memory_modified is zero.
int memory_modified;
} vga /* = { 0 }*/;
#define VBE_DISPI_DISABLED 0x00
#define VBE_DISPI_ENABLED 0x01
#define VBE_DISPI_GETCAPS 0x02
#define VBE_DISPI_8BIT_DAC 0x20
#define VBE_DISPI_LFB_ENABLED 0x40
#define VBE_DISPI_NOCLEARMEM 0x80
static void vga_update_size(void);
static void vga_alloc_mem(void)
{
if (vga.vram)
afree(vga.vram);
vga.vram = aalloc(vga.vram_size, 8);
memset(vga.vram, 0, vga.vram_size);
}
static void vga_state(void)
{
// <<< BEGIN AUTOGENERATE "state" >>>
struct bjson_object* obj = state_obj("vga", 42);
state_field(obj, 256, "vga.crt", &vga.crt);
state_field(obj, 1, "vga.crt_index", &vga.crt_index);
state_field(obj, 32, "vga.attr", &vga.attr);
state_field(obj, 1, "vga.attr_index", &vga.attr_index);
state_field(obj, 16, "vga.attr_palette", &vga.attr_palette);
state_field(obj, 8, "vga.seq", &vga.seq);
state_field(obj, 1, "vga.seq_index", &vga.seq_index);
state_field(obj, 256, "vga.gfx", &vga.gfx);
state_field(obj, 1, "vga.gfx_index", &vga.gfx_index);
state_field(obj, 1024, "vga.dac", &vga.dac);
state_field(obj, 1024, "vga.dac_palette", &vga.dac_palette);
state_field(obj, 1, "vga.dac_mask", &vga.dac_mask);
state_field(obj, 1, "vga.dac_state", &vga.dac_state);
state_field(obj, 1, "vga.dac_address", &vga.dac_address);
state_field(obj, 1, "vga.dac_color", &vga.dac_color);
state_field(obj, 1, "vga.dac_read_address", &vga.dac_read_address);
state_field(obj, 2, "vga.status", &vga.status);
state_field(obj, 1, "vga.misc", &vga.misc);
state_field(obj, 1, "vga.char_width", &vga.char_width);
state_field(obj, 8, "vga.character_map", &vga.character_map);
state_field(obj, 1, "vga.pixel_panning", &vga.pixel_panning);
state_field(obj, 1, "vga.current_pixel_panning", &vga.current_pixel_panning);
state_field(obj, 4, "vga.total_height", &vga.total_height);
state_field(obj, 4, "vga.total_width", &vga.total_width);
state_field(obj, 4, "vga.renderer", &vga.renderer);
state_field(obj, 4, "vga.current_scanline", &vga.current_scanline);
state_field(obj, 4, "vga.character_scanline", &vga.character_scanline);
state_field(obj, 4, "vga.framebuffer_offset", &vga.framebuffer_offset);
state_field(obj, 4, "vga.vram_addr", &vga.vram_addr);
state_field(obj, 1, "vga.write_access", &vga.write_access);
state_field(obj, 1, "vga.read_access", &vga.read_access);
state_field(obj, 1, "vga.write_mode", &vga.write_mode);
state_field(obj, 4, "vga.vram_window_base", &vga.vram_window_base);
state_field(obj, 4, "vga.vram_window_size", &vga.vram_window_size);
state_field(obj, 4, "vga.latch8", &vga.latch8);
state_field(obj, 2, "vga.vbe_index", &vga.vbe_index);
state_field(obj, 2, "vga.vbe_version", &vga.vbe_version);
state_field(obj, 2, "vga.vbe_enable", &vga.vbe_enable);
state_field(obj, 40, "vga.vbe_regs", &vga.vbe_regs);
state_field(obj, 4, "vga.vbe_bank", &vga.vbe_bank);
state_field(obj, 4, "vga.vgabios_addr", &vga.vgabios_addr);
state_field(obj, 4, "vga.vram_size", &vga.vram_size);
// <<< END AUTOGENERATE "state" >>>
if (state_is_reading()) {
vga_update_size();
vga_alloc_mem();
}
state_file(vga.vram_size, "vram", vga.vram);
// Force a redraw.
vga.memory_modified = 3;
}
enum {
CHAIN4,
ODDEVEN,
NORMAL,
READMODE_1
};
enum {
BLANK_RENDERER = 0, // Shows nothing on the screen
ALPHANUMERIC_RENDERER = 2, // AlphaNumeric Mode (aka text mode)
MODE_13H_RENDERER = 4, // Mode 13h
RENDER_4BPP = 6,
// VBE render modes
RENDER_32BPP = 8, // Windows XP uses this
RENDER_8BPP = 10, // Debian uses this one
RENDER_16BPP = 12,
RENDER_24BPP = 14
};
static void vga_update_mem_access(void)
{
// Different VGA memory access modes.
// Note that some have higher precedence than others; if Chain4 and Odd/Even write are both set, then Chain4 will be selected
if (vga.seq[4] & 8)
vga.write_access = CHAIN4;
else if (!(vga.seq[4] & 4)) // Note: bit has to be 0
vga.write_access = ODDEVEN;
else
vga.write_access = NORMAL;
if (vga.gfx[5] & 8)
vga.read_access = READMODE_1;
else if (vga.seq[4] & 8) // Note: Same bit as write
vga.read_access = CHAIN4;
else if (vga.gfx[5] & 0x10) // Note: Different bit than write
vga.read_access = ODDEVEN;
else
vga.read_access = NORMAL;
vga.write_mode = vga.gfx[5] & 3;
VGA_LOG("Updating Memory Access Constants: write=%d [mode=%d], read=%d\n", vga.write_access, vga.write_mode, vga.read_access);
}
// despite its name, it only resets drawing state
static void vga_complete_redraw(void)
{
vga.current_scanline = 0;
vga.character_scanline = vga.crt[8] & 0x1F;
vga.current_pixel_panning = vga.pixel_panning;
vga.vram_addr = ((vga.crt[0x0C] << 8) | vga.crt[0x0D]) << 2; // Video Address Start is done by planar offset
vga.framebuffer_offset = 0;
// Force a complete redraw of the screen, and to do that, pretend that memory has been written.
vga.memory_modified = 3;
}
static void vga_change_renderer(void)
{
// Check if VBE is enabled.
if (vga.vbe_enable & VBE_DISPI_ENABLED) {
switch (vga.vbe_regs[3]) {
// Depends on BPP
case 8:
vga.renderer = RENDER_8BPP;
break;
case 16:
vga.renderer = RENDER_16BPP;
break;
case 24:
vga.renderer = RENDER_24BPP;
break;
case 32:
vga.renderer = RENDER_32BPP;
break;
default:
VGA_FATAL("TODO: support %dbpp displays!\n", vga.vbe_regs[3]);
}
goto done;
}
// First things first: check if screen is enabled
if (((vga.seq[1] & 0x20) == 0) && (vga.attr_index & 0x20)) {
if (vga.gfx[6] & 1) {
// graphics mode
if (vga.gfx[5] & 0x40) {
// 256 mode (AKA mode 13h)
vga.renderer = MODE_13H_RENDERER;
vga.renderer |= vga.attr[0x10] >> 6 & 1;
goto done;
} else {
if (!(vga.gfx[5] & 0x20)) {
vga.renderer = RENDER_4BPP;
} else
VGA_FATAL("TODO: other gfx mode\n");
}
} else {
// alphanumeric
vga.renderer = ALPHANUMERIC_RENDERER;
}
} else {
vga.renderer = BLANK_RENDERER;
}
VGA_LOG("Change renderer to: %d\n", vga.renderer);
vga.renderer |= (vga.seq[1] >> 3 & 1);
done:
vga_complete_redraw();
}
static uint32_t vga_char_map_address(int b)
{
return b << 13;
}
static void vga_update_size(void)
{
int width, height;
// Check if VBE is enabled, and if so, use that
if (vga.vbe_enable & VBE_DISPI_ENABLED) {
width = vga.vbe_regs[1]; // xres
height = vga.vbe_regs[2]; // yres
} else {
// CR01 and CR02 control width.
// Technically, CR01 should be less than CR02, but that may not always be the case.
// Both should be less than CR00
int horizontal_display_enable_end = vga.crt[1] + 1;
int horizontal_blanking_start = vga.crt[2];
int total_horizontal_characters = (horizontal_display_enable_end < horizontal_blanking_start) ? horizontal_display_enable_end : horizontal_blanking_start;
// Screen width is measured in terms of characters
width = total_horizontal_characters * vga.char_width;
// CR12 and CR15 control height
int vertical_display_enable_end = (vga.crt[0x12] + (((vga.crt[0x07] >> 1 & 1) | (vga.crt[0x07] >> 5 & 2)) << 8)) + 1;
int vertical_blanking_start = vga.crt[0x15] + (((vga.crt[0x07] >> 3 & 1) | (vga.crt[0x09] >> 4 & 2)) << 8);
height = vertical_display_enable_end < vertical_blanking_start ? vertical_display_enable_end : vertical_blanking_start;
}
display_set_resolution(width, height);
vga.framebuffer = display_get_pixels();
vga.total_height = height;
vga.total_width = width;
if (vga.vbe_scanlines_modified)
vga.vbe_scanlines_modified = realloc(vga.vbe_scanlines_modified, vga.total_height);
else
vga.vbe_scanlines_modified = malloc(vga.total_height);
memset(vga.vbe_scanlines_modified, 1, vga.total_height);
vga.scanlines_to_update = height >> 1;
}
static uint8_t c6to8(uint8_t a)
{
if (vga.vbe_enable & VBE_DISPI_8BIT_DAC)
return a;
uint8_t b = a & 1;
return a << 2 | b << 1 | b;
}
static void update_one_dac_entry(int i)
{
int index = i << 2;
#ifndef EMSCRIPTEN
vga.dac_palette[i] = 255 << 24 | c6to8(vga.dac[index | 0]) << 16 | c6to8(vga.dac[index | 1]) << 8 | c6to8(vga.dac[index | 2]);
#else
// Reverse order of palette
vga.dac_palette[i] = 255 << 24 | c6to8(vga.dac[index | 2]) << 16 | c6to8(vga.dac[index | 1]) << 8 | c6to8(vga.dac[index | 0]);
#endif
}
static void update_all_dac_entries(void)
{
for (int i = 0; i < 256; i++) {
update_one_dac_entry(i);
}
}
static void vga_change_attr_cache(int i)
{
if (vga.attr[0x10] & 0x80)
vga.attr_palette[i] = (vga.attr[i] & 0x0F) | ((vga.attr[0x14] << 4) & 0xF0);
else
vga.attr_palette[i] = (vga.attr[i] & 0x3F) | ((vga.attr[0x14] << 4) & 0xC0);
}
#define MASK(n) (uint8_t)(~n)
static const uint32_t vbe_maximums[3] = { 1024, 768, 32 };
#ifndef VGA_LIBRARY
static
#endif
void
vga_write(uint32_t port, uint32_t data)
{
if ((port >= 0x3B0 && port <= 0x3BF && (vga.misc & 1)) || (port >= 0x3D0 && port <= 0x3DF && !(vga.misc & 1))) {
VGA_LOG("Ignoring unsupported write to addr=%04x data=%02x misc=%02x\n", port, data, vga.misc);
return;
}
uint8_t diffxor;
switch (port) {
case 0x1CE: // Bochs VBE index
vga.vbe_index = data;
break;
case 0x1CF: // Bochs VBE data
switch (vga.vbe_index) {
case 0:
vga.vbe_version = data;
break;
case 1 ... 3:
if (vga.vbe_enable & VBE_DISPI_GETCAPS)
VGA_LOG("Ignoring write (%d): GETCAPS bit\n", port);
else {
if (vga.vbe_index == 3 && data == 0)
data = 8;
if (!(vga.vbe_enable & VBE_DISPI_ENABLED)) {
if (data <= vbe_maximums[vga.vbe_index - 1])
vga.vbe_regs[vga.vbe_index] = data; // Note: no "vga.vbe_index - 1" required here
else
VGA_LOG("VBE reg out of range: reg=%d val=%x\n", port, data);
} else
VGA_LOG("Setting reg %d when VBE is enabled\n", vga.vbe_index);
}
break;
case 4:
diffxor = vga.vbe_enable ^ data;
if (diffxor) {
if (!(diffxor & VBE_DISPI_ENABLED)) {
data &= ~VBE_DISPI_LFB_ENABLED;
data |= vga.vbe_enable & VBE_DISPI_LFB_ENABLED;
}
VGA_LOG(" Set VBE enable=%04x bpp=%d diffxor=%04x current=%04x\n", data, vga.vbe_regs[3], diffxor, vga.vbe_enable);
vga.vbe_enable = data;
if (vga.vbe_regs[3] == 4)
VGA_FATAL("TODO: support VBE 4-bit modes\n");
int width = vga.vbe_regs[1], // AKA xres
height = vga.vbe_regs[2]; // AKA yres
//int bytes_per_pixel = (vga.vbe_regs[3] + 7) >> 3, total_bytes_used = bytes_per_pixel * width * height;
vga.total_height = height;
vga.total_width = width;
vga_update_size();
if (diffxor & VBE_DISPI_ENABLED) {
vga_change_renderer();
if (vga.vbe_enable & VBE_DISPI_ENABLED)
if (!(data & VBE_DISPI_NOCLEARMEM)) // should i use diffxor or data?
memset(vga.vram, 0, vga.vram_size);
}
if (diffxor & VBE_DISPI_8BIT_DAC) {
// 8-bit DAC: TODO
update_all_dac_entries();
}
vga.vbe_regs[8] = 0;
vga.vbe_regs[9] = 0;
vga.vbe_regs[6] = vga.total_width;
vga.vbe_regs[7] = vga.total_height;
// TODO...
}
break;
case 5:
data <<= 16;
if (data >= (unsigned int)vga.vram_size)
VGA_FATAL("Unsupported VBE bank offset: %08x\n", data);
vga.vbe_regs[5] = data;
break;
case 6: { // vbe virtual width
int bpp = (vga.vbe_regs[3] + 7) >> 3;
vga.vbe_regs[6] = data;
if (bpp)
vga.vbe_regs[7] = vga.vram_size / bpp;
else
vga.vbe_regs[7] = 1;
break;
}
case 7: // vbe virtual height
vga.vbe_regs[7] = data;
break;
case 8 ... 9:
vga.vbe_regs[vga.vbe_index] = data;
break;
default:
VGA_FATAL("Unknown VBE register: %d\n", vga.vbe_index);
}
break;
case 0x3C0: // Attribute controller register
if (!(vga.attr_index & 0x80)) {
// Select attribute index
diffxor = (vga.attr_index ^ data);
vga.attr_index = data & 0x7F /* | (vga.attr_index & 0x80) */; // We already know that attr_index is zero
if (diffxor & 0x20)
vga_change_renderer();
vga.attr_index = data & 0x7F /* | (vga.attr_index & 0x80) */; // We already know that attr_index is zero
} else {
// Select attribute data
uint8_t index = vga.attr_index & 0x1F;
diffxor = vga.attr[index] ^ data;
if (diffxor) {
vga.attr[index] = data;
switch (index) {
case 0 ... 15:
if (diffxor & 0x3F)
vga_change_attr_cache(index);
break;
case 16: // Mode Control Register, mostly for text modes
/*
bit 0 Graphics mode if set, Alphanumeric mode else.
1 Monochrome mode if set, color mode else.
2 9-bit wide characters if set.
The 9th bit of characters C0h-DFh will be the same as
the 8th bit. Otherwise it will be the background color.
3 If set Attribute bit 7 is blinking, else high intensity.
5 (VGA Only) If set the PEL panning register (3C0h index 13h) is
temporarily set to 0 from when the line compare causes a wrap around
until the next vertical retrace when the register is automatically
reloaded with the old value, else the PEL panning register ignores
line compares.
6 (VGA Only) If set pixels are 8 bits wide. Used in 256 color modes.
7 (VGA Only) If set bit 4-5 of the index into the DAC table are taken
from port 3C0h index 14h bit 0-1, else the bits in the palette
register are used.
*/
if (diffxor & ((1 << 0) | // Alphanumeric/Graphical Mode
//(1 << 5) | // Line Compare Register
(1 << 6)) // Pixel Width
)
vga_change_renderer(); // Changes between graphics/alphanumeric mode
if (diffxor & 0x80)
for (int i = 0; i < 16; i++)
vga_change_attr_cache(i);
if (diffxor & ((1 << 2) | // Character Width
(1 << 3) | // Blinking
(1 << 5)) // Line compare reset PEL Panning
)
vga_complete_redraw();
VGA_LOG("Mode Control Register: %02x\n", data);
break;
case 17: // Overscan color register break;
VGA_LOG("Overscan color (currently unused): %02x\n", data);
break;
case 18: // Color Plane Enable
VGA_LOG("Color plane enable: %02x\n", data);
vga.attr[18] &= 0x0F;
break;
case 19: // Horizontal PEL Panning Register
// This register enables you to shift display data "x" pixels to the left.
// However, in an effort to confuse people, this value is interpreted differently based on graphics mode
//
// pixels to shift left
// Value 8-dot 9-dot 256 color
// 0 0 1 0
// 1 1 2 -
// 2 2 3 1
// 3 3 4 -
// 4 4 5 2
// 5 5 6 -
// 6 6 7 3
// 7 7 8 -
// 8 - 0 -
// 9 and above: all undefined
// Note that due to these restrictions, it's impossible to obscure a full col of characters (and why would you want to do such a thing?)
if (data > 8)
VGA_FATAL("Unknown PEL pixel panning value");
if (vga.gfx[5] & 0x40)
vga.pixel_panning = data >> 1 & 3;
else
vga.pixel_panning = (data & 7) + (vga.char_width & 1);
VGA_LOG("Pixel panning: %d [raw], %d [effective value]\n", data, vga.pixel_panning);
break;
case 20: // Color Select Register
VGA_LOG("Color select register: %02x\n", data);
if (diffxor & 15)
for (int i = 0; i < 16; i++)
vga_change_attr_cache(i);
break;
}
}
}
vga.attr_index ^= 0x80;
break;
case 0x3C2: // Miscellaneous Register
VGA_LOG("Write VGA miscellaneous register: 0x%02x\n", data);
/*
bit 0 If set Color Emulation. Base Address=3Dxh else Mono Emulation. Base
Address=3Bxh.
1 Enable CPU Access to video memory if set
2-3 Clock Select
0: 14MHz(EGA) 25MHz(VGA)
1: 16MHz(EGA) 28MHz(VGA)
2: External(EGA) Reserved(VGA)
4 (EGA Only) Disable internal video drivers if set
5 When in Odd/Even modes Select High 64k bank if set
6 Horizontal Sync Polarity. Negative if set
7 Vertical Sync Polarity. Negative if set
Bit 6-7 indicates the number of lines on the display:
0=200(EGA) Reserved(VGA)
1= 400(VGA)
2=350(EGA) 350(VGA)
3= 480(VGA).
*/
vga.misc = data;
break;
case 0x3B8:
case 0x3BF: // ???
case 0x3C3: // ???
case 0x3DA:
case 0x3D8:
case 0x3CD:
VGA_LOG("Unknown write to %x: %02x\n", port, data);
break;
case 0x3C4: // Sequencer Index
vga.seq_index = data & 7;
break;
case 0x3C5: { // Sequencer Data
const uint8_t mask[8] = {
// which bits are reserved
MASK(0b00000000), // 0
MASK(0b11000010), // 1
MASK(0b11110000), // 2
MASK(0b11000000), // 3
MASK(0b11110001), // 4
MASK(0b11111111), // 5
MASK(0b11111111), // 6
MASK(0b11111111) // 7
};
data &= mask[vga.seq_index];
diffxor = vga.seq[vga.seq_index] ^ data;
if (diffxor) {
vga.seq[vga.seq_index] = data;
switch (vga.seq_index) {
case 0: // Sequencer Reset
VGA_LOG("SEQ: Resetting sequencer\n");
break;
case 1: // Clocking Mode
VGA_LOG("SEQ: Setting Clocking Mode to 0x%02x\n", data);
if (diffxor & 0x20) // Screen Off
vga_change_renderer();
if (diffxor & 0x08) { // Dot Clock Divide (AKA Fat Screen). Each column will be duplicated
vga_change_renderer();
vga_update_size();
}
if (diffxor & 0x01) { // 8/9 Dot Clocks
vga.char_width = 9 ^ (data & 1);
vga_update_size();
vga_complete_redraw();
}
break;
case 2: // Memory Write Access
VGA_LOG("SEQ: Memory plane write access: 0x%02x\n", data);
break;
case 3: // Character Map Select
// Note these are font addresses in plane 2
VGA_LOG("SEQ: Memory plane write access: 0x%02x\n", data);
vga.character_map[0] = vga_char_map_address((data >> 5 & 1) | (data >> 1 & 6));
vga.character_map[1] = vga_char_map_address((data >> 4 & 1) | (data << 1 & 6));
break;
case 4: // Memory Mode
VGA_LOG("SEQ: Memory Mode: 0x%02x\n", data);
if (diffxor & 0b1100)
vga_update_mem_access();
break;
}
}
break;
case 0x3C6: // DAC Palette Mask
// Used to play around with which colors can be accessed in the 256 DAC cache
vga.dac_mask = data;
vga_complete_redraw(); // Doing something as drastic as this deserves a redraw
break;
case 0x3C7: // DAC Read Address
vga.dac_read_address = data;
vga.dac_color = 0;
break;
case 0x3C8: // PEL Address Write Mode
vga.dac_address = data;
vga.dac_color = 0;
break;
case 0x3C9: // PEL Data Write
vga.dac_state = 3;
vga.dac[(vga.dac_address << 2) | vga.dac_color++] = data;
if (vga.dac_color == 3) { // 0: red, 1: green, 2: blue, 3: ???
update_one_dac_entry(vga.dac_address);
vga.dac_address++; // This will wrap around because it is a uint8_t
vga.dac_color = 0;
}
break;
case 0x3CE: // Graphics Register Index
vga.gfx_index = data & 15;
break;
case 0x3CF: { // Graphics Register Data
const uint8_t mask[16] = {
MASK(0b11110000), // 0
MASK(0b11110000), // 1
MASK(0b11110000), // 2
MASK(0b11100000), // 3
MASK(0b11111100), // 4
MASK(0b10000100), // 5
MASK(0b11110000), // 6
MASK(0b11110000), // 7
MASK(0b00000000), // 8
MASK(0b11111111), // 9 - not documented
MASK(0b00001000), // 10 - ???
MASK(0b00000000), // 11 - ???
MASK(0b11111111), // 12 - not documented
MASK(0b11111111), // 13 - not documented
MASK(0b11111111), // 14 - not documented
MASK(0b11111111), // 15 - not documented
//MASK(0b00000000), // 18 - scratch room vga
};
data &= mask[vga.gfx_index];
diffxor = vga.gfx[vga.gfx_index] ^ data;
if (diffxor) {
vga.gfx[vga.gfx_index] = data;
switch (vga.gfx_index) {
case 0: // Set/Reset Plane
VGA_LOG("Set/Reset Plane: %02x\n", data);
break;
case 1: // Enable Set/Reset Plane
VGA_LOG("Enable Set/Reset Plane: %02x\n", data);
break;
case 2: // Color Comare
VGA_LOG("Color Compare: %02x\n", data);
break;
case 3: // Data Rotate/ALU Operation Select
VGA_LOG("Data Rotate: %02x\n", data);
break;
case 4: // Read Plane Select
VGA_LOG("Read Plane Select: %02x\n", data);
break;
case 5: // Graphics Mode
VGA_LOG("Graphics Mode: %02x\n", data);
if (diffxor & (3 << 5)) // Shift Register Control
vga_change_renderer();
if (diffxor & ((1 << 3) | (1 << 4) | 3))
vga_update_mem_access();
break;
case 6: // Miscellaneous Register
VGA_LOG("Miscellaneous Register: %02x\n", data);
switch (data >> 2 & 3) {
case 0:
vga.vram_window_base = 0xA0000;
vga.vram_window_size = 0x20000;
break;
case 1:
vga.vram_window_base = 0xA0000;
vga.vram_window_size = 0x10000;
break;
case 2:
vga.vram_window_base = 0xB0000;
vga.vram_window_size = 0x8000;
break;
case 3:
vga.vram_window_base = 0xB8000;
vga.vram_window_size = 0x8000;
break;
}
if (diffxor & 1)
vga_change_renderer();
break;
case 7:
VGA_LOG("Color Don't Care: %02x\n", data);
break;
case 8:
VGA_LOG("Bit Mask Register: %02x\n", data);
break;
}
}
break;
}
case 0x3D4:
case 0x3B4: // CRT index
vga.crt_index = data/* & 0x3F*/;
break;
case 0x3D5:
case 0x3B5: { // CRT data
static uint8_t mask[64] = {
// 0-7 are changed based on CR11 bit 7
MASK(0b00000000), // 0
MASK(0b00000000), // 1
MASK(0b00000000), // 2
MASK(0b00000000), // 3
MASK(0b00000000), // 4
MASK(0b00000000), // 5
MASK(0b00000000), // 6
MASK(0b00000000), // 7
MASK(0b10000000), // 8
MASK(0b00000000), // 9
MASK(0b11000000), // A
MASK(0b10000000), // B
MASK(0b00000000), // C
MASK(0b00000000), // D
MASK(0b00000000), // E
MASK(0b00000000), // F
MASK(0b00000000), // 10
MASK(0b00110000), // 11
MASK(0b00000000), // 12
MASK(0b00000000), // 13
MASK(0b10000000), // 14
MASK(0b00000000), // 15
MASK(0b10000000), // 16
MASK(0b00010000), // 17
MASK(0b00000000) // 18
};
// Don't allow ourselves to go out of bounds
if(vga.crt_index > 0x3F) break;
// The extra difficulty here comes from the fact that the mask is used here to allow masking of CR0-7 in addition to keeping out undefined bits
data &= mask[vga.crt_index];
// consider the case when we write 0x33 to CR01 (which is currently 0x66) and write protection is own
// In this case, we would be doing (0x33 & 0) ^ 0x66 which would result in 0x66 being put in diffxor
// However, if we masked the result, the following would occur: ((0x33 & 0) ^ 0x66) & 0 = 0
diffxor = (data ^ vga.crt[vga.crt_index]) & mask[vga.crt_index];
if (diffxor) {
vga.crt[vga.crt_index] = data | (vga.crt[vga.crt_index] & ~mask[vga.crt_index]);
switch (vga.crt_index) {
case 1:
VGA_LOG("End Horizontal Display: %02x\n", data);
vga_update_size();
break;
case 2:
VGA_LOG("Start Horizontal Blanking: %02x\n", data);
vga_update_size();
break;
case 7:
VGA_LOG("CRT Overflow: %02x\n", data);
vga_update_size();
break;
case 9:
VGA_LOG("Start Horizontal Blanking: %02x\n", data);
if (diffxor & 0x20)
vga_update_size();
break;
case 0x11:
if (diffxor & 0x80) {
uint8_t fill_value = (int8_t)(vga.crt[0x11] ^ 0x80) >> 7;
//printf("%d: %d [%02x]\n", fill_value, vga.crt_index, data);
for (int i = 0; i < 8; i++)
mask[i] = fill_value;
mask[7] &= ~0x10;
data &= mask[vga.crt_index];
}
break;
case 0x12:
VGA_LOG("Vertical Display End: %02x\n", data);
vga_update_size();
break;
case 0x15:
VGA_LOG("Start Vertical Blanking: %02x\n", data);
vga_update_size();
break;
}
}
break;
}
}
default:
VGA_LOG("VGA write: 0x%x [data: 0x%02x]\n", port, data);
}
}
#ifndef VGA_LIBRARY
static
#endif
uint32_t
vga_read(uint32_t port)
{
if ((port >= 0x3B0 && port <= 0x3BF && (vga.misc & 1)) || (port >= 0x3D0 && port <= 0x3DF && !(vga.misc & 1))) {
return -1;
}
switch (port) {
case 0x1CE:
return vga.vbe_index;
case 0x1CF:
switch (vga.vbe_index) {
case 0:
return vga.vbe_version;
case 1 ... 3: // xres, yres, bpp
if (vga.vbe_enable & VBE_DISPI_GETCAPS)
return vbe_maximums[vga.vbe_index - 1];
else
return vga.vbe_regs[vga.vbe_index]; // vga.vbe_index - 1 not required at this location
break;
case 4:
return vga.vbe_enable & (VBE_DISPI_ENABLED | VBE_DISPI_GETCAPS | VBE_DISPI_8BIT_DAC);
case 5:
return vga.vbe_regs[5] >> 16;
case 6:
return vga.vbe_regs[6];
case 7:
return vga.vbe_regs[7];
case 8 ... 9:
return vga.vbe_regs[vga.vbe_index];
case 10: // Get VBE RAM size in 64 KB banks
return vga.vram_size >> 16;
default:
VGA_FATAL("VBE read: %d\n", vga.vbe_index);
}
break;
case 0x3C0:
return vga.attr_index;
case 0x3C1:
return vga.attr[vga.attr_index & 0x1F];
case 0x3C2:
return vga.misc;
case 0x3C4:
return vga.seq_index;
case 0x3C5:
return vga.seq[vga.seq_index];
case 0x3C6:
return vga.dac_mask;
case 0x3C7:
return vga.dac_state;
case 0x3C8:
return vga.dac_address;
case 0x3C9: {
vga.dac_state = 0;
uint8_t data = vga.dac[(vga.dac_read_address << 2) | (vga.dac_color++)];
if (vga.dac_color == 3) {
vga.dac_read_address++;
vga.dac_color = 0;
}
return data;
}
case 0x3CC:
return vga.misc;
case 0x3CE:
return vga.gfx_index;
case 0x3CF:
return vga.gfx[vga.gfx_index];
case 0x3B8:
case 0x3D8:
case 0x3CD:
return -1;
case 0x3BA:
case 0x3DA: // Input status Register #1
// Some programs poll this register to make sure that graphics registers are only being modified during vertical retrace periods
// Not many programs require this feature to work. For now, we can fake this effect.
vga.status[1] ^= 9;
vga.attr_index &= ~0x80; // Also clears attr flip flop
return vga.status[1];
case 0x3B5:
case 0x3D5:
return vga.crt[vga.crt_index];
default:
VGA_LOG("Unknown read: 0x%x\n", port);
return -1;
}
}
static inline uint8_t bpp4_to_offset(uint8_t i, uint8_t j, uint8_t k)
{
return ((i & (0x80 >> j)) != 0) ? 1 << k : 0;
}
static int framectr = 0;
void vga_update(void)
{
// Note: This function should NOT modify any VGA registers or memory!
framectr = (framectr + 1) & 0x3F;
int scanlines_to_update = vga.scanlines_to_update; // XXX
// Text Mode state
unsigned int cursor_scanline_start = 0, cursor_scanline_end = 0, cursor_enabled = 0, cursor_address = 0,
underline_location = 0, line_graphics = 0;
// 4BPP renderer
unsigned int enableMask = 0, address_bit_mapping = 0;
// All non-VBE renderers
unsigned int offset_between_lines = (((!vga.crt[0x13]) << 8 | vga.crt[0x13]) * 2) << 2;
switch (vga.renderer & ~1) {
case BLANK_RENDERER:
break;
case ALPHANUMERIC_RENDERER:
cursor_scanline_start = vga.crt[0x0A] & 0x1F;
cursor_scanline_end = vga.crt[0x0B] & 0x1F;
cursor_enabled = (vga.crt[0x0B] & 0x20) || (framectr >= 0x20);
cursor_address = (vga.crt[0x0E] << 8 | vga.crt[0x0F]) << 2;
underline_location = vga.crt[0x14] & 0x1F;
line_graphics = vga.char_width == 9 ? ((vga.attr[0x10] & 4) ? 0xE0 : 0) : 0;
break;
case RENDER_4BPP:
enableMask = vga.attr[0x12] & 15;
address_bit_mapping = vga.crt[0x17] & 1;
break;
case RENDER_16BPP: // VBE 16-bit BPP mode
offset_between_lines = vga.total_width * 2;
break;
case RENDER_24BPP: // VBE 24-bit BPP mode
offset_between_lines = vga.total_width * 3;
break;
case RENDER_32BPP: // VBE 32-bit BPP mode
offset_between_lines = vga.total_width * 4;
break;
}
if (!vga.memory_modified)
return;
vga.memory_modified &= ~(1 << (vga.current_scanline != 0));
#ifdef ALLEGRO_BUILD
vga.framebuffer = display_get_pixels();
#endif
uint32_t
//current = vga.current_scanline,
total_scanlines_drawn
= 0;
while (scanlines_to_update--) {
total_scanlines_drawn++;
// Things to account for here
// - Doubling Scanlines
// - Character Scanlines
// - Line Compare (aka split screen)
// - Incrementing & Wrapping Around Scanlines
// - Drawing the scanline itself
// First things first, doubling scanlines
// On a screen without doubling, the scanlines would look like this:
// 0: QWERTYUIOPQWERTYUIOPQWERTYUIOP
// 1: ASDFGHJKLASDFGHJKLASDFGHJKLASD
// 2: ZXCVBNMZXCVBNMZXCVBNMZXCVBNMZX
// 3: ...
// with scanline doubling, however, it looks like this:
// 0: QWERTYUIOPQWERTYUIOPQWERTYUIOP
// 1: QWERTYUIOPQWERTYUIOPQWERTYUIOP <-- dupe
// 2: ASDFGHJKLASDFGHJKLASDFGHJKLASD
// 3: ASDFGHJKLASDFGHJKLASDFGHJKLASD <-- dupe
// 4: ZXCVBNMZXCVBNMZXCVBNMZXCVBNMZX