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fpga_output.txt
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fpga_output.txt
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Warning (292006): Can't contact license server "1717@quartus.license.iet.ntnu.no" -- this server will be ignored
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Wed Nov 23 20:35:48 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RSA -c RSA
Info (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file c:/altera/10.0/quartus/bin/assignment_defaults.qdf
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file u_monpro_datapath.vhd
Info (12022): Found design unit 1: u_monpro_datapath-Behavioral
Info (12023): Found entity 1: u_monpro_datapath
Info (12021): Found 2 design units, including 1 entities, in source file u_monpro_controller.vhd
Info (12022): Found design unit 1: u_monpro_controller-Behavioral
Info (12023): Found entity 1: u_monpro_controller
Info (12021): Found 2 design units, including 1 entities, in source file monpro.vhd
Info (12022): Found design unit 1: monpro-rtl
Info (12023): Found entity 1: monpro
Info (12021): Found 2 design units, including 1 entities, in source file u_rsa_controller.vhd
Info (12022): Found design unit 1: u_rsa_controller-Behavioral
Info (12023): Found entity 1: u_rsa_controller
Info (12021): Found 2 design units, including 1 entities, in source file u_rsa_datapath.vhd
Info (12022): Found design unit 1: u_rsa_datapath-Behavioral
Info (12023): Found entity 1: u_rsa_datapath
Info (12021): Found 2 design units, including 1 entities, in source file rsa.vhd
Info (12022): Found design unit 1: RSACore-rtl
Info (12023): Found entity 1: RSACore
Info (12021): Found 1 design units, including 0 entities, in source file /users/tfe4141/desktop/rsa/link_vhdl_mont/rsaparameters.vhd
Info (12022): Found design unit 1: RSAParameters
Info (12021): Found 1 design units, including 0 entities, in source file /users/tfe4141/desktop/rsa/link_vhdl_mont/compdecl.vhd
Info (12022): Found design unit 1: CompDecl
Info (12021): Found 2 design units, including 1 entities, in source file /users/tfe4141/desktop/rsa/link_vhdl_mont/uart.vhd
Info (12022): Found design unit 1: UART-rtl
Info (12023): Found entity 1: UART
Info (12021): Found 2 design units, including 1 entities, in source file /users/tfe4141/desktop/rsa/link_vhdl_mont/rsaextcom.vhd
Info (12022): Found design unit 1: RSAExtCom-rtl
Info (12023): Found entity 1: RSAExtCom
Info (12021): Found 2 design units, including 1 entities, in source file /users/tfe4141/desktop/rsa/link_vhdl_mont/rsa.vhd
Info (12022): Found design unit 1: RSA-struct
Info (12023): Found entity 1: RSA
Info (12127): Elaborating entity "RSA" for the top level hierarchy
Info (12128): Elaborating entity "RSACore" for hierarchy "RSACore:R"
Info (12128): Elaborating entity "u_rsa_datapath" for hierarchy "RSACore:R|u_rsa_datapath:u_rsa_datapath"
Info (12128): Elaborating entity "u_rsa_controller" for hierarchy "RSACore:R|u_rsa_controller:u_rsa_controller"
Info (12128): Elaborating entity "monpro" for hierarchy "RSACore:R|monpro:monpro"
Info (12128): Elaborating entity "u_monpro_datapath" for hierarchy "RSACore:R|monpro:monpro|u_monpro_datapath:u_monpro_datapath"
Info (12128): Elaborating entity "u_monpro_controller" for hierarchy "RSACore:R|monpro:monpro|u_monpro_controller:u_monpro_controller"
Info (12128): Elaborating entity "UART" for hierarchy "UART:U"
Info (12128): Elaborating entity "RSAExtCom" for hierarchy "RSAExtCom:C"
Warning (10036): Verilog HDL or VHDL warning at RSAExtCom.vhd(71): object "LedCtrlState" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at RSAExtCom.vhd(78): object "LedCtr" assigned a value but never read
Info (19000): Inferred 1 megafunctions from design logic
Info (276034): Inferred altshift_taps megafunction from the following design logic: "RSACore:R|u_rsa_datapath:u_rsa_datapath|X_reg_rtl_0"
Info (286033): Parameter NUMBER_OF_TAPS set to 1
Info (286033): Parameter TAP_DISTANCE set to 4
Info (286033): Parameter WIDTH set to 32
Info (12130): Elaborated megafunction instantiation "RSACore:R|u_rsa_datapath:u_rsa_datapath|altshift_taps:X_reg_rtl_0"
Info (12133): Instantiated megafunction "RSACore:R|u_rsa_datapath:u_rsa_datapath|altshift_taps:X_reg_rtl_0" with the following parameter:
Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
Info (12134): Parameter "TAP_DISTANCE" = "4"
Info (12134): Parameter "WIDTH" = "32"
Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_q5n.tdf
Info (12023): Found entity 1: shift_taps_q5n
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_o1b1.tdf
Info (12023): Found entity 1: altsyncram_o1b1
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_4pf.tdf
Info (12023): Found entity 1: cntr_4pf
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_r8h.tdf
Info (12023): Found entity 1: cntr_r8h
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 3785 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 3 input pins
Info (21059): Implemented 15 output pins
Info (21061): Implemented 3735 logic cells
Info (21064): Implemented 32 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 480 megabytes
Info: Processing ended: Wed Nov 23 20:36:13 2016
Info: Elapsed time: 00:00:25
Info: Total CPU time (on all processors): 00:00:15
Warning (292006): Can't contact license server "1717@quartus.license.iet.ntnu.no" -- this server will be ignored
Info (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file c:/altera/10.0/quartus/bin/assignment_defaults.qdf
Info: *******************************************************************
Info: Running Quartus II 32-bit Fitter
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Wed Nov 23 20:36:14 2016
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off RSA -c RSA
Info: qfit2_default_script.tcl version: #1
Info: Project = RSA
Info: Revision = RSA
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (119006): Selected device EP4CE115F29C7 for design "RSA"
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info (176445): Device EP4CE40F29C7 is compatible
Info (176445): Device EP4CE40F29I7 is compatible
Info (176445): Device EP4CE30F29C7 is compatible
Info (176445): Device EP4CE30F29I7 is compatible
Info (176445): Device EP4CE55F29C7 is compatible
Info (176445): Device EP4CE55F29I7 is compatible
Info (176445): Device EP4CE75F29C7 is compatible
Info (176445): Device EP4CE75F29I7 is compatible
Info (176445): Device EP4CE115F29I7 is compatible
Info (169124): Fitter converted 5 user pins into dedicated programming pins
Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (332104): Reading SDC File: 'RSA.sdc'
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From clk25 (Rise) to clk25 (Rise) (setup and hold)
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 1 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 40.000 clk25
Info (176353): Automatically promoted node Clk25
Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
Info (176357): Destination node Clk25~0
Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:05
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:05
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X58_Y37 to location X68_Y48
Info (170194): Fitter routing operations ending: elapsed time is 00:00:05
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (11888): Total time spent on timing analysis during the Fitter is 3.53 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:03
Info (144001): Generated suppressed messages file C:/Users/tfe4141/Desktop/RSA/user_files/group17/RSA.fit.smsg
Info: Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 919 megabytes
Info: Processing ended: Wed Nov 23 20:36:55 2016
Info: Elapsed time: 00:00:41
Info: Total CPU time (on all processors): 00:00:45
Warning (292006): Can't contact license server "1717@quartus.license.iet.ntnu.no" -- this server will be ignored
Info (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file c:/altera/10.0/quartus/bin/assignment_defaults.qdf
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Wed Nov 23 20:36:55 2016
Info: Command: quartus_sta RSA -c RSA
Info: qsta_default_script.tcl version: #1
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (21077): Core supply voltage is 1.2V
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'RSA.sdc'
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From clk25 (Rise) to clk25 (Rise) (setup and hold)
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 22.441
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 22.441 0.000 clk25
Info (332146): Worst-case hold slack is 0.300
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 0.300 0.000 clk25
Info (332146): Worst-case recovery slack is 38.016
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 38.016 0.000 clk25
Info (332146): Worst-case removal slack is 1.440
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 1.440 0.000 clk25
Info (332146): Worst-case minimum pulse width slack is 19.704
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 19.704 0.000 clk25
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From clk25 (Rise) to clk25 (Rise) (setup and hold)
Info (332146): Worst-case setup slack is 24.126
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 24.126 0.000 clk25
Info (332146): Worst-case hold slack is 0.298
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 0.298 0.000 clk25
Info (332146): Worst-case recovery slack is 38.186
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 38.186 0.000 clk25
Info (332146): Worst-case removal slack is 1.299
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 1.299 0.000 clk25
Info (332146): Worst-case minimum pulse width slack is 19.724
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 19.724 0.000 clk25
Info: Analyzing Fast 1200mV 0C Model
Warning (332060): Node: Clk was determined to be a clock but was found without an associated clock assignment.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From clk25 (Rise) to clk25 (Rise) (setup and hold)
Info (332146): Worst-case setup slack is 31.020
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 31.020 0.000 clk25
Info (332146): Worst-case hold slack is 0.105
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 0.105 0.000 clk25
Info (332146): Worst-case recovery slack is 39.031
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 39.031 0.000 clk25
Info (332146): Worst-case removal slack is 0.686
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 0.686 0.000 clk25
Info (332146): Worst-case minimum pulse width slack is 19.712
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 19.712 0.000 clk25
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 10 warnings
Info: Peak virtual memory: 485 megabytes
Info: Processing ended: Wed Nov 23 20:37:10 2016
Info: Elapsed time: 00:00:15
Info: Total CPU time (on all processors): 00:00:06
Warning (292006): Can't contact license server "1717@quartus.license.iet.ntnu.no" -- this server will be ignored
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Wed Nov 23 20:37:11 2016
Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off RSA -c RSA
Info (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file c:/altera/10.0/quartus/bin/assignment_defaults.qdf
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 386 megabytes
Info: Processing ended: Wed Nov 23 20:37:28 2016
Info: Elapsed time: 00:00:17
Info: Total CPU time (on all processors): 00:00:07
Info: *******************************************************************
Info: Running Quartus II 32-bit Programmer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Wed Nov 23 20:37:28 2016
Info: Command: quartus_pgm -c USB-Blaster -m jtag -o p;RSA.sof
Info (213045): Using programming cable "USB-Blaster [USB-0]"
Info (213011): Using programming file RSA.sof with checksum 0x00790382 for device EP4CE115F29@1
Info (209060): Started Programmer operation at Wed Nov 23 20:37:32 2016
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F70DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Wed Nov 23 20:37:38 2016
Info: Quartus II 32-bit Programmer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 180 megabytes
Info: Processing ended: Wed Nov 23 20:37:38 2016
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:01
Using static key
Short test 1: PASSED
Using static key
Short test 2: PASSED
Using static key
Short test 3: PASSED
Using static key
Short test 4: PASSED
Using static key
Short test 5: PASSED
Using static key
Main test: PASSED
All tests passed!
###################################################################
Congratulations Sindre and Laurits!
Your design passed the test!
Your countless sleepless nights have finally paid off!
,:
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Average cycles per block: 42512
Number of latches: 0
Logic cells used: 1662
fmax: 56.95 MHz
Throughput: 1340 blocks/second