From b7de4c4313e34897b911adb8117382ddb9b988c4 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 2 Oct 2024 14:20:42 +0200 Subject: [PATCH] dt-bindings: some changes to match mt7988 dts(i) --- .../pinctrl/mediatek,mt7988-pinctrl.yaml | 121 +++++++++--------- 1 file changed, 61 insertions(+), 60 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml index 5ad65135fe1c7..3b8f43fa830ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: MediaTek MT7986 Pin Controller @@ -10,13 +10,12 @@ maintainers: - Sean Wang description: - The MediaTek's MT7986 Pin controller is used to control SoC pins. + The MediaTek's MT7988 Pin controller is used to control SoC pins. properties: compatible: enum: - - mediatek,mt7986a-pinctrl - - mediatek,mt7986b-pinctrl + - mediatek,mt7988-pinctrl reg: minItems: 8 @@ -25,11 +24,10 @@ properties: reg-names: items: - const: gpio - - const: iocfg_rt + - const: iocfg_tr + - const: iocfg_br - const: iocfg_rb - - const: iocfg_lt - const: iocfg_lb - - const: iocfg_tr - const: iocfg_tl - const: eint @@ -367,96 +365,99 @@ examples: soc { #address-cells = <2>; #size-cells = <2>; + pio: pinctrl@1001f000 { - compatible = "mediatek,mt7986a-pinctrl"; + compatible = "mediatek,mt7988-pinctrl", "syscon"; reg = <0 0x1001f000 0 0x1000>, - <0 0x11c30000 0 0x1000>, - <0 0x11c40000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11e30000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", - "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_tr", + "iocfg_br", "iocfg_rb", + "iocfg_lb", "iocfg_tl", "eint"; + /* mt7986 order: reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";*/ gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 100>; + gpio-ranges = <&pio 0 0 84>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; #interrupt-cells = <2>; - pcie_pins: pcie-pins { + i2c0_pins: i2c0-pins-g0 { mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + function = "i2c"; + groups = "i2c0_1"; }; }; - pwm_pins: pwm-pins { + mdio0_pins: mdio0-pins { mux { - function = "pwm"; - groups = "pwm0", "pwm1_0"; + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; }; }; - spi0_pins: spi0-pins { + mmc0_pins_emmc_51: mmc0-pins-emmc-51 { mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; + function = "flash"; + groups = "emmc_51"; }; }; - uart1_pins: uart1-pins { + mmc0_pins_sdcard: mmc0-pins-sdcard { mux { - function = "uart"; - groups = "uart1"; + function = "flash"; + groups = "sdcard"; }; }; - uart1_3_pins: uart1-3-pins { + pcie0_pins: pcie0-pins { mux { - function = "uart"; - groups = "uart1_3_rx_tx", "uart1_3_cts_rts"; + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; }; }; - uart2_pins: uart2-pins { + pcie1_pins: pcie1-pins { mux { - function = "uart"; - groups = "uart2"; + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; }; }; - mmc0_pins_default: mmc0-pins { + pcie2_pins: pcie2-pins { mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - bias-pull-down = ; /* pull-down 50K */ + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; }; - conf-ds { - pins = "EMMC_DSL"; - bias-pull-down = ; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - bias-pull-up = ; /* pull-up 10K */ + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; }; }; + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; }; };