From c74a186c4e092f515569d6deaff3d0a0da239907 Mon Sep 17 00:00:00 2001 From: Jesse Braham Date: Tue, 31 Jan 2023 08:43:49 -0800 Subject: [PATCH] Fix the references to the `ets_update_cpu_frequency_rom` ROM function --- esp-hal-common/src/clock/clocks_ll/esp32c2.rs | 6 +++--- esp-hal-common/src/clock/clocks_ll/esp32c3.rs | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/esp-hal-common/src/clock/clocks_ll/esp32c2.rs b/esp-hal-common/src/clock/clocks_ll/esp32c2.rs index 2c6c4462ed4..26466afa06d 100644 --- a/esp-hal-common/src/clock/clocks_ll/esp32c2.rs +++ b/esp-hal-common/src/clock/clocks_ll/esp32c2.rs @@ -8,7 +8,7 @@ use crate::{ }; extern "C" { - fn ets_update_cpu_frequency(ticks_per_us: u32); + fn ets_update_cpu_frequency_rom(ticks_per_us: u32); } const I2C_BBPLL: u32 = 0x66; @@ -132,7 +132,7 @@ pub(crate) fn esp32c2_rtc_update_to_xtal(freq: XtalClock, _div: u32) { let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { - ets_update_cpu_frequency(freq.mhz()); + ets_update_cpu_frequency_rom(freq.mhz()); // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) // first. system_control.sysclk_conf.modify(|_, w| { @@ -164,7 +164,7 @@ pub(crate) fn esp32c2_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) { CpuClock::Clock120MHz => 1, }) }); - ets_update_cpu_frequency(cpu_clock_speed.mhz()); + ets_update_cpu_frequency_rom(cpu_clock_speed.mhz()); } } diff --git a/esp-hal-common/src/clock/clocks_ll/esp32c3.rs b/esp-hal-common/src/clock/clocks_ll/esp32c3.rs index 6afb6d33666..604bf241d28 100644 --- a/esp-hal-common/src/clock/clocks_ll/esp32c3.rs +++ b/esp-hal-common/src/clock/clocks_ll/esp32c3.rs @@ -8,7 +8,7 @@ use crate::{ }; extern "C" { - fn ets_update_cpu_frequency(ticks_per_us: u32); + fn ets_update_cpu_frequency_rom(ticks_per_us: u32); } const I2C_BBPLL: u32 = 0x66; @@ -193,7 +193,7 @@ pub(crate) fn esp32c3_rtc_update_to_xtal(freq: XtalClock, _div: u32) { let system_control = unsafe { &*crate::peripherals::SYSTEM::ptr() }; unsafe { - ets_update_cpu_frequency(freq.mhz()); + ets_update_cpu_frequency_rom(freq.mhz()); // Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) // first. system_control.sysclk_conf.modify(|_, w| { @@ -225,7 +225,7 @@ pub(crate) fn esp32c3_rtc_freq_to_pll_mhz(cpu_clock_speed: CpuClock) { CpuClock::Clock160MHz => 1, }) }); - ets_update_cpu_frequency(cpu_clock_speed.mhz()); + ets_update_cpu_frequency_rom(cpu_clock_speed.mhz()); } }