****** START compiling Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this (MethodHash=c129bf6f) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 16 ldc.i4.0 IL_0001 0a stloc.0 IL_0002 05 ldarg.3 IL_0003 0b stloc.1 IL_0004 2b 77 br.s 119 (IL_007d) IL_0006 16 ldc.i4.0 IL_0007 0c stloc.2 IL_0008 03 ldarg.1 IL_0009 0d stloc.3 IL_000a 2b 64 br.s 100 (IL_0070) IL_000c 12 04 ldloca.s 0x4 IL_000e 09 ldloc.3 IL_000f 07 ldloc.1 IL_0010 28 97 02 00 06 call 0x6000297 IL_0015 11 04 ldloc.s 0x4 IL_0017 13 05 stloc.s 0x5 IL_0019 16 ldc.i4.0 IL_001a 13 06 stloc.s 0x6 IL_001c 22 00 00 00 00 ldc.r4 0.000000 IL_0021 13 07 stloc.s 0x7 IL_0023 12 05 ldloca.s 0x5 IL_0025 28 98 02 00 06 call 0x6000298 IL_002a 13 05 stloc.s 0x5 IL_002c 11 05 ldloc.s 0x5 IL_002e 11 04 ldloc.s 0x4 IL_0030 28 9b 02 00 06 call 0x600029B IL_0035 13 05 stloc.s 0x5 IL_0037 11 06 ldloc.s 0x6 IL_0039 17 ldc.i4.1 IL_003a 58 add IL_003b 13 06 stloc.s 0x6 IL_003d 12 05 ldloca.s 0x5 IL_003f 28 99 02 00 06 call 0x6000299 IL_0044 13 07 stloc.s 0x7 IL_0046 11 07 ldloc.s 0x7 IL_0048 22 00 00 80 40 ldc.r4 4.000000 IL_004d 34 09 bge.un.s 9 (IL_0058) IL_004f 11 06 ldloc.s 0x6 IL_0051 20 e8 03 00 00 ldc.i4 0x3E8 IL_0056 32 cb blt.s -53 (IL_0023) IL_0058 02 ldarg.0 IL_0059 28 a9 02 00 06 call 0x60002A9 IL_005e 08 ldloc.2 IL_005f 06 ldloc.0 IL_0060 11 06 ldloc.s 0x6 IL_0062 6f 99 01 00 0a callvirt 0xA000199 IL_0067 09 ldloc.3 IL_0068 0e 05 ldarg.s 0x5 IL_006a 58 add IL_006b 0d stloc.3 IL_006c 08 ldloc.2 IL_006d 17 ldc.i4.1 IL_006e 58 add IL_006f 0c stloc.2 IL_0070 09 ldloc.3 IL_0071 04 ldarg.2 IL_0072 32 98 blt.s -104 (IL_000c) IL_0074 07 ldloc.1 IL_0075 0e 05 ldarg.s 0x5 IL_0077 58 add IL_0078 0b stloc.1 IL_0079 06 ldloc.0 IL_007a 17 ldc.i4.1 IL_007b 58 add IL_007c 0a stloc.0 IL_007d 07 ldloc.1 IL_007e 0e 04 ldarg.s 0x4 IL_0080 34 0b bge.un.s 11 (IL_008d) IL_0082 02 ldarg.0 IL_0083 28 aa 02 00 06 call 0x60002AA IL_0088 39 79 ff ff ff brfalse -135 (IL_0006) IL_008d 2a ret lvaSetClass: setting class for V00 to (00007FFB23131DF0) Algorithms.ScalarFloatRenderer 'this' passed in register rcx Arg #1 passed in register(s) mm1 Arg #2 passed in register(s) mm2 Arg #3 passed in register(s) mm3 lvaGrabTemp returning 14 (V14 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 float ; V02 arg2 float ; V03 arg3 float ; V04 arg4 float ; V05 arg5 float ; V06 loc0 int ; V07 loc1 float ; V08 loc2 int ; V09 loc3 float ; V10 loc4 struct ( 8) ; V11 loc5 struct ( 8) ; V12 loc6 int ; V13 loc7 float ; V14 OutArgs lclBlk (na) "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 14 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 08Eh 1: 01h 01h V01 arg1 000h 08Eh 2: 02h 02h V02 arg2 000h 08Eh 3: 03h 03h V03 arg3 000h 08Eh 4: 04h 04h V04 arg4 000h 08Eh 5: 05h 05h V05 arg5 000h 08Eh 6: 06h 06h V06 loc0 000h 08Eh 7: 07h 07h V07 loc1 000h 08Eh 8: 08h 08h V08 loc2 000h 08Eh 9: 09h 09h V09 loc3 000h 08Eh 10: 0Ah 0Ah V10 loc4 000h 08Eh 11: 0Bh 0Bh V11 loc5 000h 08Eh 12: 0Ch 0Ch V12 loc6 000h 08Eh 13: 0Dh 0Dh V13 loc7 000h 08Eh info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this Jump targets: IL_0006 IL_000c IL_0023 IL_0058 IL_0070 IL_007d IL_008d New Basic Block BB01 [0000] created. BB01 [000..006) New Basic Block BB02 [0001] created. BB02 [006..00C) New Basic Block BB03 [0002] created. BB03 [00C..023) New Basic Block BB04 [0003] created. BB04 [023..04F) New Basic Block BB05 [0004] created. BB05 [04F..058) New Basic Block BB06 [0005] created. BB06 [058..070) New Basic Block BB07 [0006] created. BB07 [070..074) New Basic Block BB08 [0007] created. BB08 [074..07D) New Basic Block BB09 [0008] created. BB09 [07D..082) New Basic Block BB10 [0009] created. BB10 [082..08D) New Basic Block BB11 [0010] created. BB11 [08D..08E) IL Code Size,Instr 142, 72, Basic Block count 11, Local Variable Num,Ref count 15, 43 for method Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this OPTIONS: opts.MinOpts() == false Basic block list for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) BB02 [0001] 1 1 [006..00C)-> BB07 (always) bwd BB03 [0002] 1 1 [00C..023) bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) bwd BB06 [0005] 2 1 [058..070) bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) bwd BB08 [0007] 1 1 [074..07D) bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) bwd BB11 [0010] 2 1 [08D..08E) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 0 (0x000) ldc.i4.0 0 [ 1] 1 (0x001) stloc.0 STMT00000 (IL 0x000... ???) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V06 loc0 [000000] ------------ \--* CNS_INT int 0 [ 0] 2 (0x002) ldarg.3 [ 1] 3 (0x003) stloc.1 STMT00001 (IL 0x002... ???) [000005] -A---------- * ASG float [000004] D------N---- +--* LCL_VAR float V07 loc1 [000003] ------------ \--* LCL_VAR float V03 arg3 [ 0] 4 (0x004) br.s impImportBlockPending for BB09 Importing BB09 (PC=125) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 125 (0x07d) ldloc.1 [ 1] 126 (0x07e) ldarg.s 4 [ 2] 128 (0x080) bge.un.s STMT00002 (IL 0x07D... ???) [000009] ------------ * JTRUE void [000008] N--------U-- \--* GE int [000006] ------------ +--* LCL_VAR float V07 loc1 [000007] ------------ \--* LCL_VAR float V04 arg4 impImportBlockPending for BB10 impImportBlockPending for BB11 Importing BB11 (PC=141) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 141 (0x08d) ret STMT00003 (IL 0x08D... ???) [000010] ------------ * RETURN void Importing BB10 (PC=130) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 130 (0x082) ldarg.0 [ 1] 131 (0x083) call 060002AA In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 STMT00004 (IL 0x082... ???) [000012] I-C-G------- * CALL int Algorithms.FractalRenderer.get_Abort (exactContextHnd=0x00007FFB2310D9A9) [000011] ------------ this in rcx \--* LCL_VAR ref V00 this [ 1] 136 (0x088) brfalse STMT00005 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000013] --C--------- +--* RET_EXPR int (inl return from call [000012]) [000014] ------------ \--* CNS_INT int 0 impImportBlockPending for BB11 impImportBlockPending for BB02 Importing BB02 (PC=006) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 6 (0x006) ldc.i4.0 0 [ 1] 7 (0x007) stloc.2 STMT00006 (IL 0x006... ???) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V08 loc2 [000017] ------------ \--* CNS_INT int 0 [ 0] 8 (0x008) ldarg.1 [ 1] 9 (0x009) stloc.3 STMT00007 (IL 0x008... ???) [000022] -A---------- * ASG float [000021] D------N---- +--* LCL_VAR float V09 loc3 [000020] ------------ \--* LCL_VAR float V01 arg1 [ 0] 10 (0x00a) br.s impImportBlockPending for BB07 Importing BB07 (PC=112) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 112 (0x070) ldloc.3 [ 1] 113 (0x071) ldarg.2 [ 2] 114 (0x072) blt.s STMT00008 (IL 0x070... ???) [000026] ------------ * JTRUE void [000025] ------------ \--* LT int [000023] ------------ +--* LCL_VAR float V09 loc3 [000024] ------------ \--* LCL_VAR float V02 arg2 impImportBlockPending for BB08 impImportBlockPending for BB03 Importing BB03 (PC=012) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 12 (0x00c) ldloca.s 4 [ 1] 14 (0x00e) ldloc.3 [ 2] 15 (0x00f) ldloc.1 [ 3] 16 (0x010) call 06000297 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00009 (IL 0x00C... ???) [000031] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000028] ------------ this in rcx +--* ADDR byref [000027] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ arg1 +--* LCL_VAR float V09 loc3 [000030] ------------ arg2 \--* LCL_VAR float V07 loc1 [ 0] 21 (0x015) ldloc.s 4 [ 1] 23 (0x017) stloc.s 5 STMT00010 (IL 0x015... ???) [000035] -A---------- * ASG struct (copy) [000033] D----------- +--* LCL_VAR struct V11 loc5 [000032] ------------ \--* LCL_VAR struct V10 loc4 [ 0] 25 (0x019) ldc.i4.0 0 [ 1] 26 (0x01a) stloc.s 6 STMT00011 (IL 0x019... ???) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V12 loc6 [000036] ------------ \--* CNS_INT int 0 [ 0] 28 (0x01c) ldc.r4 0.00000000000000000 [ 1] 33 (0x021) stloc.s 7 STMT00012 (IL 0x01C... ???) [000041] -A---------- * ASG float [000040] D------N---- +--* LCL_VAR float V13 loc7 [000039] ------------ \--* CNS_DBL float 0.00000000000000000 impImportBlockPending for BB04 Importing BB04 (PC=035) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 35 (0x023) ldloca.s 5 [ 1] 37 (0x025) call 06000298 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 8 STMT00013 (IL 0x023... ???) [000044] I-C-G------- * CALL struct Algorithms.ComplexFloat.square (exactContextHnd=0x00007FFB231320D9) [000043] ------------ this in rcx \--* ADDR byref [000042] ------------ \--* LCL_VAR struct V11 loc5 [ 1] 42 (0x02a) stloc.s 5 STMT00014 (IL ???... ???) [000049] -AC--------- * ASG long [000048] *----------- +--* IND long [000047] ------------ | \--* ADDR byref [000046] ------------ | \--* LCL_VAR struct V11 loc5 [000045] --C--------- \--* RET_EXPR long (inl return from call [000044]) [ 0] 44 (0x02c) ldloc.s 5 [ 1] 46 (0x02e) ldloc.s 4 [ 2] 48 (0x030) call 0600029B In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 8 Calling impNormStructVal on: [000051] ------------ * LCL_VAR struct V10 loc4 resulting tree: [000054] n----------- * OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 Calling impNormStructVal on: [000050] ------------ * LCL_VAR struct V11 loc5 resulting tree: [000056] n----------- * OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct V11 loc5 STMT00015 (IL 0x02C... ???) [000052] I-C-G------- * CALL struct Algorithms.ComplexFloat.op_Addition (exactContextHnd=0x00007FFB231320D9) [000056] n----------- arg0 +--* OBJ struct [000055] ------------ | \--* ADDR byref [000050] ------------ | \--* LCL_VAR struct V11 loc5 [000054] n----------- arg1 \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 [ 1] 53 (0x035) stloc.s 5 STMT00016 (IL ???... ???) [000061] -AC--------- * ASG long [000060] *----------- +--* IND long [000059] ------------ | \--* ADDR byref [000058] ------------ | \--* LCL_VAR struct V11 loc5 [000057] --C--------- \--* RET_EXPR long (inl return from call [000052]) [ 0] 55 (0x037) ldloc.s 6 [ 1] 57 (0x039) ldc.i4.1 1 [ 2] 58 (0x03a) add [ 1] 59 (0x03b) stloc.s 6 STMT00017 (IL 0x037... ???) [000066] -A---------- * ASG int [000065] D------N---- +--* LCL_VAR int V12 loc6 [000064] ------------ \--* ADD int [000062] ------------ +--* LCL_VAR int V12 loc6 [000063] ------------ \--* CNS_INT int 1 [ 0] 61 (0x03d) ldloca.s 5 [ 1] 63 (0x03f) call 06000299 In Compiler::impImportCall: opcode is call, kind=0, callRetType is float, structSize is 0 STMT00018 (IL 0x03D... ???) [000069] I-C-G------- * CALL float Algorithms.ComplexFloat.sqabs (exactContextHnd=0x00007FFB231320D9) [000068] ------------ this in rcx \--* ADDR byref [000067] ------------ \--* LCL_VAR struct V11 loc5 [ 1] 68 (0x044) stloc.s 7 STMT00019 (IL ???... ???) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000070] --C--------- \--* RET_EXPR float (inl return from call [000069]) [ 0] 70 (0x046) ldloc.s 7 [ 1] 72 (0x048) ldc.r4 4.0000000000000000 [ 2] 77 (0x04d) bge.un.s STMT00020 (IL 0x046... ???) [000076] ------------ * JTRUE void [000075] N--------U-- \--* GE int [000073] ------------ +--* LCL_VAR float V13 loc7 [000074] ------------ \--* CNS_DBL float 4.0000000000000000 impImportBlockPending for BB05 impImportBlockPending for BB06 Importing BB06 (PC=088) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 88 (0x058) ldarg.0 [ 1] 89 (0x059) call 060002A9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00021 (IL 0x058... ???) [000078] I-C-G------- * CALL ref Algorithms.FractalRenderer.get_DrawPixel (exactContextHnd=0x00007FFB2310D9A9) [000077] ------------ this in rcx \--* LCL_VAR ref V00 this [ 1] 94 (0x05e) ldloc.2 [ 2] 95 (0x05f) ldloc.0 [ 3] 96 (0x060) ldloc.s 6 [ 4] 98 (0x062) callvirt 0A000199 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'cannot get method info' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32]:Invoke(int,int,int):this' INLINER: Marking System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32]:Invoke(int,int,int):this as NOINLINE because of cannot get method info INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'cannot get method info' STMT00022 (IL ???... ???) [000083] --C-G------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000079] --C--------- this in rcx +--* RET_EXPR ref (inl return from call [000078]) [000080] ------------ arg1 +--* LCL_VAR int V08 loc2 [000081] ------------ arg2 +--* LCL_VAR int V06 loc0 [000082] ------------ arg3 \--* LCL_VAR int V12 loc6 [ 0] 103 (0x067) ldloc.3 [ 1] 104 (0x068) ldarg.s 5 [ 2] 106 (0x06a) add [ 1] 107 (0x06b) stloc.3 STMT00023 (IL 0x067... ???) [000088] -A---------- * ASG float [000087] D------N---- +--* LCL_VAR float V09 loc3 [000086] ------------ \--* ADD float [000084] ------------ +--* LCL_VAR float V09 loc3 [000085] ------------ \--* LCL_VAR float V05 arg5 [ 0] 108 (0x06c) ldloc.2 [ 1] 109 (0x06d) ldc.i4.1 1 [ 2] 110 (0x06e) add [ 1] 111 (0x06f) stloc.2 STMT00024 (IL 0x06C... ???) [000093] -A---------- * ASG int [000092] D------N---- +--* LCL_VAR int V08 loc2 [000091] ------------ \--* ADD int [000089] ------------ +--* LCL_VAR int V08 loc2 [000090] ------------ \--* CNS_INT int 1 impImportBlockPending for BB07 Importing BB05 (PC=079) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 79 (0x04f) ldloc.s 6 [ 1] 81 (0x051) ldc.i4 1000 [ 2] 86 (0x056) blt.s STMT00025 (IL 0x04F... ???) [000097] ------------ * JTRUE void [000096] ------------ \--* LT int [000094] ------------ +--* LCL_VAR int V12 loc6 [000095] ------------ \--* CNS_INT int 0x3E8 impImportBlockPending for BB06 impImportBlockPending for BB04 Importing BB08 (PC=116) of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' [ 0] 116 (0x074) ldloc.1 [ 1] 117 (0x075) ldarg.s 5 [ 2] 119 (0x077) add [ 1] 120 (0x078) stloc.1 STMT00026 (IL 0x074... ???) [000102] -A---------- * ASG float [000101] D------N---- +--* LCL_VAR float V07 loc1 [000100] ------------ \--* ADD float [000098] ------------ +--* LCL_VAR float V07 loc1 [000099] ------------ \--* LCL_VAR float V05 arg5 [ 0] 121 (0x079) ldloc.0 [ 1] 122 (0x07a) ldc.i4.1 1 [ 2] 123 (0x07b) add [ 1] 124 (0x07c) stloc.0 STMT00027 (IL 0x079... ???) [000107] -A---------- * ASG int [000106] D------N---- +--* LCL_VAR int V06 loc0 [000105] ------------ \--* ADD int [000103] ------------ +--* LCL_VAR int V06 loc0 [000104] ------------ \--* CNS_INT int 1 impImportBlockPending for BB09 *************** in fgTransformIndirectCalls(root) -- no candidates to transform New BlockSet epoch 1, # of blocks (including unused BB00): 12, bitset array size: 1 (short) *************** In fgMorph() *************** In fgDebugCheckBBlist *************** In fgInline() Expanding INLINE_CANDIDATE in statement STMT00009 in BB03: STMT00009 (IL 0x00C...0x017) [000031] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000028] ------------ this in rcx +--* ADDR byref [000027] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ arg1 +--* LCL_VAR float V09 loc3 [000030] ------------ arg2 \--* LCL_VAR float V07 loc1 thisArg: is a constant is byref to a struct local [000028] ------------ * ADDR byref [000027] ------------ \--* LCL_VAR struct V10 loc4 Argument #1: is a local var [000029] ------------ * LCL_VAR float V09 loc3 Argument #2: is a local var [000030] ------------ * LCL_VAR float V07 loc1 INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.ComplexFloat:.ctor(float,float):this set to 0x00007FFB231320D9: Invoking compiler for the inlinee method Algorithms.ComplexFloat:.ctor(float,float):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7d 6b 01 00 04 stfld 0x400016B IL_0007 02 ldarg.0 IL_0008 04 ldarg.2 IL_0009 7d 6c 01 00 04 stfld 0x400016C IL_000e 2a ret INLINER impTokenLookupContextHandle for Algorithms.ComplexFloat:.ctor(float,float):this is 0x00007FFB231320D9. *************** In fgFindBasicBlocks() for Algorithms.ComplexFloat:.ctor(float,float):this Jump targets: none New Basic Block BB12 [0011] created. BB12 [000..00F) Basic block list for 'Algorithms.ComplexFloat:.ctor(float,float):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB12 [0011] 1 1 [000..00F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ComplexFloat:.ctor(float,float):this impImportBlockPending for BB12 Importing BB12 (PC=000) of 'Algorithms.ComplexFloat:.ctor(float,float):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 [ 2] 2 (0x002) stfld 0400016B [000111] -A---------- * ASG float [000110] -------N---- +--* FIELD float Real [000108] ------------ | \--* ADDR byref [000109] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ \--* LCL_VAR float V09 loc3 [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) ldarg.2 [ 2] 9 (0x009) stfld 0400016C [000115] -A---------- * ASG float [000114] -------N---- +--* FIELD float Imaginary [000112] ------------ | \--* ADDR byref [000113] ------------ | \--* LCL_VAR struct V10 loc4 [000030] ------------ \--* LCL_VAR float V07 loc1 [ 0] 14 (0x00e) ret *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000031] ----------- Arguments setup: Inlinee method body: STMT00028 (IL 0x00C... ???) [000111] -A---------- * ASG float [000110] -------N---- +--* FIELD float Real [000108] ------------ | \--* ADDR byref [000109] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ \--* LCL_VAR float V09 loc3 STMT00029 (IL 0x00C... ???) [000115] -A---------- * ASG float [000114] -------N---- +--* FIELD float Imaginary [000112] ------------ | \--* ADDR byref [000113] ------------ | \--* LCL_VAR struct V10 loc4 [000030] ------------ \--* LCL_VAR float V07 loc1 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined Algorithms.ComplexFloat:.ctor(float,float):this (15 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.ComplexFloat:.ctor(float,float):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00013 in BB04: STMT00013 (IL 0x023...0x02A) [000044] I-C-G------- * CALL long Algorithms.ComplexFloat.square (exactContextHnd=0x00007FFB231320D9) [000043] ------------ this in rcx \--* ADDR byref [000042] ------------ \--* LCL_VAR struct V11 loc5 thisArg: is a constant is byref to a struct local [000043] ------------ * ADDR byref [000042] ------------ \--* LCL_VAR struct V11 loc5 INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this set to 0x00007FFB231320D9: Invoking compiler for the inlinee method Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 6b 01 00 04 ldfld 0x400016B IL_0006 02 ldarg.0 IL_0007 7b 6b 01 00 04 ldfld 0x400016B IL_000c 5a mul IL_000d 02 ldarg.0 IL_000e 7b 6c 01 00 04 ldfld 0x400016C IL_0013 02 ldarg.0 IL_0014 7b 6c 01 00 04 ldfld 0x400016C IL_0019 5a mul IL_001a 59 sub IL_001b 22 00 00 00 40 ldc.r4 2.000000 IL_0020 02 ldarg.0 IL_0021 7b 6b 01 00 04 ldfld 0x400016B IL_0026 5a mul IL_0027 02 ldarg.0 IL_0028 7b 6c 01 00 04 ldfld 0x400016C IL_002d 5a mul IL_002e 73 97 02 00 06 newobj 0x6000297 IL_0033 2a ret INLINER impTokenLookupContextHandle for Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this is 0x00007FFB231320D9. *************** In fgFindBasicBlocks() for Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this Jump targets: none New Basic Block BB13 [0012] created. BB13 [000..034) Basic block list for 'Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB13 [0012] 1 1 [000..034) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this impImportBlockPending for BB13 Importing BB13 (PC=000) of 'Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0400016B [ 1] 6 (0x006) ldarg.0 [ 2] 7 (0x007) ldfld 0400016B [ 2] 12 (0x00c) mul [ 1] 13 (0x00d) ldarg.0 [ 2] 14 (0x00e) ldfld 0400016C [ 2] 19 (0x013) ldarg.0 [ 3] 20 (0x014) ldfld 0400016C [ 3] 25 (0x019) mul [ 2] 26 (0x01a) sub [ 1] 27 (0x01b) ldc.r4 2.0000000000000000 [ 2] 32 (0x020) ldarg.0 [ 3] 33 (0x021) ldfld 0400016B [ 3] 38 (0x026) mul [ 2] 39 (0x027) ldarg.0 [ 3] 40 (0x028) ldfld 0400016C [ 3] 45 (0x02d) mul [ 2] 46 (0x02e) newobj lvaGrabTemp returning 15 (V15 tmp1) called for NewObj constructor temp. [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct V15 tmp1 [000142] ------------ \--* CNS_INT int 0 06000297 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000146] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000145] ------------ this in rcx +--* ADDR byref [000144] ------------ | \--* LCL_VAR struct V15 tmp1 [000131] ------------ arg1 +--* SUB float [000123] ------------ | +--* MUL float [000119] ------------ | | +--* FIELD float Real [000117] ------------ | | | \--* ADDR byref [000118] ------------ | | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | | \--* FIELD float Real [000120] ------------ | | \--* ADDR byref [000121] ------------ | | \--* LCL_VAR struct V11 loc5 [000130] ------------ | \--* MUL float [000126] ------------ | +--* FIELD float Imaginary [000124] ------------ | | \--* ADDR byref [000125] ------------ | | \--* LCL_VAR struct V11 loc5 [000129] ------------ | \--* FIELD float Imaginary [000127] ------------ | \--* ADDR byref [000128] ------------ | \--* LCL_VAR struct V11 loc5 [000140] ------------ arg2 \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 [ 1] 51 (0x033) ret Inlinee Return expression (before normalization) => [000147] ------------ * LCL_VAR struct V15 tmp1 impFixupStructReturnType: retyping [000147] ------------ * LCL_VAR struct V15 tmp1 impFixupStructReturnType: result of retyping is [000147] ------------ * LCL_FLD long V15 tmp1 [+0] Inlinee Return expression (after normalization) => [000147] ------------ * LCL_FLD long V15 tmp1 [+0] *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000044] ----------- Arguments setup: Inlinee method body: STMT00030 (IL 0x023... ???) [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct V15 tmp1 [000142] ------------ \--* CNS_INT int 0 STMT00031 (IL 0x023... ???) [000146] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000145] ------------ this in rcx +--* ADDR byref [000144] ------------ | \--* LCL_VAR struct V15 tmp1 [000131] ------------ arg1 +--* SUB float [000123] ------------ | +--* MUL float [000119] ------------ | | +--* FIELD float Real [000117] ------------ | | | \--* ADDR byref [000118] ------------ | | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | | \--* FIELD float Real [000120] ------------ | | \--* ADDR byref [000121] ------------ | | \--* LCL_VAR struct V11 loc5 [000130] ------------ | \--* MUL float [000126] ------------ | +--* FIELD float Imaginary [000124] ------------ | | \--* ADDR byref [000125] ------------ | | \--* LCL_VAR struct V11 loc5 [000129] ------------ | \--* FIELD float Imaginary [000127] ------------ | \--* ADDR byref [000128] ------------ | \--* LCL_VAR struct V11 loc5 [000140] ------------ arg2 \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000044] is [000147] ------------ * LCL_FLD long V15 tmp1 [+0] Successfully inlined Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this (52 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00031 in BB04: STMT00031 (IL 0x023... ???) [000146] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000145] ------------ this in rcx +--* ADDR byref [000144] ------------ | \--* LCL_VAR struct V15 tmp1 [000131] ------------ arg1 +--* SUB float [000123] ------------ | +--* MUL float [000119] ------------ | | +--* FIELD float Real [000117] ------------ | | | \--* ADDR byref [000118] ------------ | | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | | \--* FIELD float Real [000120] ------------ | | \--* ADDR byref [000121] ------------ | | \--* LCL_VAR struct V11 loc5 [000130] ------------ | \--* MUL float [000126] ------------ | +--* FIELD float Imaginary [000124] ------------ | | \--* ADDR byref [000125] ------------ | | \--* LCL_VAR struct V11 loc5 [000129] ------------ | \--* FIELD float Imaginary [000127] ------------ | \--* ADDR byref [000128] ------------ | \--* LCL_VAR struct V11 loc5 [000140] ------------ arg2 \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 thisArg: is a constant is byref to a struct local [000145] ------------ * ADDR byref [000144] ------------ \--* LCL_VAR struct V15 tmp1 Argument #1: has caller local ref [000131] ------------ * SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* FIELD float Real [000117] ------------ | | \--* ADDR byref [000118] ------------ | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | \--* FIELD float Real [000120] ------------ | \--* ADDR byref [000121] ------------ | \--* LCL_VAR struct V11 loc5 [000130] ------------ \--* MUL float [000126] ------------ +--* FIELD float Imaginary [000124] ------------ | \--* ADDR byref [000125] ------------ | \--* LCL_VAR struct V11 loc5 [000129] ------------ \--* FIELD float Imaginary [000127] ------------ \--* ADDR byref [000128] ------------ \--* LCL_VAR struct V11 loc5 Argument #2: has caller local ref [000140] ------------ * MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.ComplexFloat:.ctor(float,float):this set to 0x00007FFB231320D9: Invoking compiler for the inlinee method Algorithms.ComplexFloat:.ctor(float,float):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7d 6b 01 00 04 stfld 0x400016B IL_0007 02 ldarg.0 IL_0008 04 ldarg.2 IL_0009 7d 6c 01 00 04 stfld 0x400016C IL_000e 2a ret INLINER impTokenLookupContextHandle for Algorithms.ComplexFloat:.ctor(float,float):this is 0x00007FFB231320D9. *************** In fgFindBasicBlocks() for Algorithms.ComplexFloat:.ctor(float,float):this Jump targets: none New Basic Block BB14 [0013] created. BB14 [000..00F) Basic block list for 'Algorithms.ComplexFloat:.ctor(float,float):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB14 [0013] 1 1 [000..00F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ComplexFloat:.ctor(float,float):this impImportBlockPending for BB14 Importing BB14 (PC=000) of 'Algorithms.ComplexFloat:.ctor(float,float):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 16 (V16 tmp2) called for Inlining Arg. [ 2] 2 (0x002) stfld 0400016B [000153] -A---------- * ASG float [000152] -------N---- +--* FIELD float Real [000149] ------------ | \--* ADDR byref [000150] ------------ | \--* LCL_VAR struct V15 tmp1 [000151] ------------ \--* LCL_VAR float V16 tmp2 [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) ldarg.2 lvaGrabTemp returning 17 (V17 tmp3) called for Inlining Arg. [ 2] 9 (0x009) stfld 0400016C [000158] -A---------- * ASG float [000157] -------N---- +--* FIELD float Imaginary [000154] ------------ | \--* ADDR byref [000155] ------------ | \--* LCL_VAR struct V15 tmp1 [000156] ------------ \--* LCL_VAR float V17 tmp3 [ 0] 14 (0x00e) ret *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000146] ----------- Arguments setup: STMT00034 (IL 0x023... ???) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* FIELD float Real [000117] ------------ | | \--* ADDR byref [000118] ------------ | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | \--* FIELD float Real [000120] ------------ | \--* ADDR byref [000121] ------------ | \--* LCL_VAR struct V11 loc5 [000130] ------------ \--* MUL float [000126] ------------ +--* FIELD float Imaginary [000124] ------------ | \--* ADDR byref [000125] ------------ | \--* LCL_VAR struct V11 loc5 [000129] ------------ \--* FIELD float Imaginary [000127] ------------ \--* ADDR byref [000128] ------------ \--* LCL_VAR struct V11 loc5 STMT00035 (IL 0x023... ???) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 Inlinee method body: STMT00032 (IL 0x023... ???) [000153] -A---------- * ASG float [000152] -------N---- +--* FIELD float Real [000149] ------------ | \--* ADDR byref [000150] ------------ | \--* LCL_VAR struct V15 tmp1 [000151] ------------ \--* LCL_VAR float V16 tmp2 STMT00033 (IL 0x023... ???) [000158] -A---------- * ASG float [000157] -------N---- +--* FIELD float Imaginary [000154] ------------ | \--* ADDR byref [000155] ------------ | \--* LCL_VAR struct V15 tmp1 [000156] ------------ \--* LCL_VAR float V17 tmp3 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined Algorithms.ComplexFloat:.ctor(float,float):this (15 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.ComplexFloat:.ctor(float,float):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000045] with [000147] [000045] --C--------- * RET_EXPR long (inl return from call [000147]) Inserting the inline return expression [000147] ------------ * LCL_FLD long V15 tmp1 [+0] Expanding INLINE_CANDIDATE in statement STMT00015 in BB04: STMT00015 (IL 0x02C...0x035) [000052] I-C-G------- * CALL long Algorithms.ComplexFloat.op_Addition (exactContextHnd=0x00007FFB231320D9) [000056] n----------- arg0 +--* OBJ struct [000055] ------------ | \--* ADDR byref [000050] ------------ | \--* LCL_VAR struct V11 loc5 [000054] n----------- arg1 \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 Argument #0: has caller local ref [000056] n----------- * OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct V11 loc5 Argument #1: has caller local ref [000054] n----------- * OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat set to 0x00007FFB231320D9: Invoking compiler for the inlinee method Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 6b 01 00 04 ldfld 0x400016B IL_0006 03 ldarg.1 IL_0007 7b 6b 01 00 04 ldfld 0x400016B IL_000c 58 add IL_000d 02 ldarg.0 IL_000e 7b 6c 01 00 04 ldfld 0x400016C IL_0013 03 ldarg.1 IL_0014 7b 6c 01 00 04 ldfld 0x400016C IL_0019 58 add IL_001a 73 97 02 00 06 newobj 0x6000297 IL_001f 2a ret INLINER impTokenLookupContextHandle for Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat is 0x00007FFB231320D9. *************** In fgFindBasicBlocks() for Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat Jump targets: none New Basic Block BB15 [0014] created. BB15 [000..020) Basic block list for 'Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB15 [0014] 1 1 [000..020) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat impImportBlockPending for BB15 Importing BB15 (PC=000) of 'Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 18 (V18 tmp4) called for Inlining Arg. [ 1] 1 (0x001) ldfld 0400016B [ 1] 6 (0x006) ldarg.1 lvaGrabTemp returning 19 (V19 tmp5) called for Inlining Arg. [ 2] 7 (0x007) ldfld 0400016B [ 2] 12 (0x00c) add [ 1] 13 (0x00d) ldarg.0 [ 2] 14 (0x00e) ldfld 0400016C [ 2] 19 (0x013) ldarg.1 [ 3] 20 (0x014) ldfld 0400016C [ 3] 25 (0x019) add [ 2] 26 (0x01a) newobj lvaGrabTemp returning 20 (V20 tmp6) called for NewObj constructor temp. [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct V20 tmp6 [000179] ------------ \--* CNS_INT int 0 06000297 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000183] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000182] ------------ this in rcx +--* ADDR byref [000181] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ arg1 +--* ADD float [000166] ------------ | +--* FIELD float Real [000165] ------------ | | \--* ADDR byref [000164] ------------ | | \--* LCL_VAR struct V18 tmp4 [000169] ------------ | \--* FIELD float Real [000168] ------------ | \--* ADDR byref [000167] ------------ | \--* LCL_VAR struct V19 tmp5 [000177] ------------ arg2 \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 [ 1] 31 (0x01f) ret Inlinee Return expression (before normalization) => [000184] ------------ * LCL_VAR struct V20 tmp6 impFixupStructReturnType: retyping [000184] ------------ * LCL_VAR struct V20 tmp6 impFixupStructReturnType: result of retyping is [000184] ------------ * LCL_FLD long V20 tmp6 [+0] Inlinee Return expression (after normalization) => [000184] ------------ * LCL_FLD long V20 tmp6 [+0] *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000052] ----------- Arguments setup: STMT00038 (IL 0x02C... ???) [000187] -A---------- * ASG struct (copy) [000185] D----------- +--* LCL_VAR struct V18 tmp4 [000056] n----------- \--* OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct V11 loc5 STMT00039 (IL 0x02C... ???) [000190] -A---------- * ASG struct (copy) [000188] D----------- +--* LCL_VAR struct V19 tmp5 [000054] n----------- \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 Inlinee method body: STMT00036 (IL 0x02C... ???) [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct V20 tmp6 [000179] ------------ \--* CNS_INT int 0 STMT00037 (IL 0x02C... ???) [000183] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000182] ------------ this in rcx +--* ADDR byref [000181] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ arg1 +--* ADD float [000166] ------------ | +--* FIELD float Real [000165] ------------ | | \--* ADDR byref [000164] ------------ | | \--* LCL_VAR struct V18 tmp4 [000169] ------------ | \--* FIELD float Real [000168] ------------ | \--* ADDR byref [000167] ------------ | \--* LCL_VAR struct V19 tmp5 [000177] ------------ arg2 \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000052] is [000184] ------------ * LCL_FLD long V20 tmp6 [+0] Successfully inlined Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat (32 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00037 in BB04: STMT00037 (IL 0x02C... ???) [000183] I-C-G------- * CALL void Algorithms.ComplexFloat..ctor (exactContextHnd=0x00007FFB231320D9) [000182] ------------ this in rcx +--* ADDR byref [000181] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ arg1 +--* ADD float [000166] ------------ | +--* FIELD float Real [000165] ------------ | | \--* ADDR byref [000164] ------------ | | \--* LCL_VAR struct V18 tmp4 [000169] ------------ | \--* FIELD float Real [000168] ------------ | \--* ADDR byref [000167] ------------ | \--* LCL_VAR struct V19 tmp5 [000177] ------------ arg2 \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 thisArg: is a constant is byref to a struct local [000182] ------------ * ADDR byref [000181] ------------ \--* LCL_VAR struct V20 tmp6 Argument #1: [000170] ------------ * ADD float [000166] ------------ +--* FIELD float Real [000165] ------------ | \--* ADDR byref [000164] ------------ | \--* LCL_VAR struct V18 tmp4 [000169] ------------ \--* FIELD float Real [000168] ------------ \--* ADDR byref [000167] ------------ \--* LCL_VAR struct V19 tmp5 Argument #2: [000177] ------------ * ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.ComplexFloat:.ctor(float,float):this set to 0x00007FFB231320D9: Invoking compiler for the inlinee method Algorithms.ComplexFloat:.ctor(float,float):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7d 6b 01 00 04 stfld 0x400016B IL_0007 02 ldarg.0 IL_0008 04 ldarg.2 IL_0009 7d 6c 01 00 04 stfld 0x400016C IL_000e 2a ret INLINER impTokenLookupContextHandle for Algorithms.ComplexFloat:.ctor(float,float):this is 0x00007FFB231320D9. *************** In fgFindBasicBlocks() for Algorithms.ComplexFloat:.ctor(float,float):this Jump targets: none New Basic Block BB16 [0015] created. BB16 [000..00F) Basic block list for 'Algorithms.ComplexFloat:.ctor(float,float):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB16 [0015] 1 1 [000..00F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ComplexFloat:.ctor(float,float):this impImportBlockPending for BB16 Importing BB16 (PC=000) of 'Algorithms.ComplexFloat:.ctor(float,float):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 21 (V21 tmp7) called for Inlining Arg. [ 2] 2 (0x002) stfld 0400016B [000196] -A---------- * ASG float [000195] -------N---- +--* FIELD float Real [000192] ------------ | \--* ADDR byref [000193] ------------ | \--* LCL_VAR struct V20 tmp6 [000194] ------------ \--* LCL_VAR float V21 tmp7 [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) ldarg.2 lvaGrabTemp returning 22 (V22 tmp8) called for Inlining Arg. [ 2] 9 (0x009) stfld 0400016C [000201] -A---------- * ASG float [000200] -------N---- +--* FIELD float Imaginary [000197] ------------ | \--* ADDR byref [000198] ------------ | \--* LCL_VAR struct V20 tmp6 [000199] ------------ \--* LCL_VAR float V22 tmp8 [ 0] 14 (0x00e) ret *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000183] ----------- Arguments setup: Inlinee method body: STMT00040 (IL 0x02C... ???) [000196] -A---------- * ASG float [000195] -------N---- +--* FIELD float Real [000192] ------------ | \--* ADDR byref [000193] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ \--* ADD float [000166] ------------ +--* FIELD float Real [000165] ------------ | \--* ADDR byref [000164] ------------ | \--* LCL_VAR struct V18 tmp4 [000169] ------------ \--* FIELD float Real [000168] ------------ \--* ADDR byref [000167] ------------ \--* LCL_VAR struct V19 tmp5 STMT00041 (IL 0x02C... ???) [000201] -A---------- * ASG float [000200] -------N---- +--* FIELD float Imaginary [000197] ------------ | \--* ADDR byref [000198] ------------ | \--* LCL_VAR struct V20 tmp6 [000177] ------------ \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined Algorithms.ComplexFloat:.ctor(float,float):this (15 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.ComplexFloat:.ctor(float,float):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000057] with [000184] [000057] --C--------- * RET_EXPR long (inl return from call [000184]) Inserting the inline return expression [000184] ------------ * LCL_FLD long V20 tmp6 [+0] Expanding INLINE_CANDIDATE in statement STMT00018 in BB04: STMT00018 (IL 0x03D...0x044) [000069] I-C-G------- * CALL float Algorithms.ComplexFloat.sqabs (exactContextHnd=0x00007FFB231320D9) [000068] ------------ this in rcx \--* ADDR byref [000067] ------------ \--* LCL_VAR struct V11 loc5 thisArg: is a constant is byref to a struct local [000068] ------------ * ADDR byref [000067] ------------ \--* LCL_VAR struct V11 loc5 INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.ComplexFloat:sqabs():float:this set to 0x00007FFB231320D9: Invoking compiler for the inlinee method Algorithms.ComplexFloat:sqabs():float:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 6b 01 00 04 ldfld 0x400016B IL_0006 02 ldarg.0 IL_0007 7b 6b 01 00 04 ldfld 0x400016B IL_000c 5a mul IL_000d 02 ldarg.0 IL_000e 7b 6c 01 00 04 ldfld 0x400016C IL_0013 02 ldarg.0 IL_0014 7b 6c 01 00 04 ldfld 0x400016C IL_0019 5a mul IL_001a 58 add IL_001b 2a ret INLINER impTokenLookupContextHandle for Algorithms.ComplexFloat:sqabs():float:this is 0x00007FFB231320D9. *************** In fgFindBasicBlocks() for Algorithms.ComplexFloat:sqabs():float:this Jump targets: none New Basic Block BB17 [0016] created. BB17 [000..01C) Basic block list for 'Algorithms.ComplexFloat:sqabs():float:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB17 [0016] 1 1 [000..01C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.ComplexFloat:sqabs():float:this impImportBlockPending for BB17 Importing BB17 (PC=000) of 'Algorithms.ComplexFloat:sqabs():float:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0400016B [ 1] 6 (0x006) ldarg.0 [ 2] 7 (0x007) ldfld 0400016B [ 2] 12 (0x00c) mul [ 1] 13 (0x00d) ldarg.0 [ 2] 14 (0x00e) ldfld 0400016C [ 2] 19 (0x013) ldarg.0 [ 3] 20 (0x014) ldfld 0400016C [ 3] 25 (0x019) mul [ 2] 26 (0x01a) add [ 1] 27 (0x01b) ret Inlinee Return expression (before normalization) => [000217] ------------ * ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 Inlinee Return expression (after normalization) => [000217] ------------ * ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 ** Note: inlinee IL was partially imported -- imported 0 of 28 bytes of method IL *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000069] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000069] is [000217] ------------ * ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 Successfully inlined Algorithms.ComplexFloat:sqabs():float:this (28 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.ComplexFloat:sqabs():float:this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000070] with [000217] [000070] --C--------- * RET_EXPR float (inl return from call [000217]) Inserting the inline return expression [000217] ------------ * ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 Expanding INLINE_CANDIDATE in statement STMT00021 in BB06: STMT00021 (IL 0x058...0x06B) [000078] I-C-G------- * CALL ref Algorithms.FractalRenderer.get_DrawPixel (exactContextHnd=0x00007FFB2310D9A9) [000077] ------------ this in rcx \--* LCL_VAR ref V00 this thisArg: is a local var [000077] ------------ * LCL_VAR ref V00 this INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this set to 0x00007FFB2310D9A9: Invoking compiler for the inlinee method Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 72 01 00 04 ldfld 0x4000172 IL_0006 2a ret INLINER impTokenLookupContextHandle for Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this is 0x00007FFB2310D9A9. *************** In fgFindBasicBlocks() for Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this Jump targets: none New Basic Block BB18 [0017] created. BB18 [000..007) Basic block list for 'Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB18 [0017] 1 1 [000..007) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this impImportBlockPending for BB18 Importing BB18 (PC=000) of 'Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000172 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000219] ---XG------- * FIELD ref _drawPixel [000077] ------------ \--* LCL_VAR ref V00 this Inlinee Return expression (after normalization) => [000219] ---XG------- * FIELD ref _drawPixel [000077] ------------ \--* LCL_VAR ref V00 this ** Note: inlinee IL was partially imported -- imported 0 of 7 bytes of method IL *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform ----------- Statements (and blocks) added due to the inlining of call [000078] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000078] is [000219] ---XG------- * FIELD ref _drawPixel [000077] ------------ \--* LCL_VAR ref V00 this Successfully inlined Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000079] with [000219] [000079] --C--------- * RET_EXPR ref (inl return from call [000219]) Inserting the inline return expression [000219] ---XG------- * FIELD ref _drawPixel [000077] ------------ \--* LCL_VAR ref V00 this Expanding INLINE_CANDIDATE in statement STMT00004 in BB10: STMT00004 (IL 0x082...0x088) [000012] I-C-G------- * CALL int Algorithms.FractalRenderer.get_Abort (exactContextHnd=0x00007FFB2310D9A9) [000011] ------------ this in rcx \--* LCL_VAR ref V00 this thisArg: is a local var [000011] ------------ * LCL_VAR ref V00 this INLINER: inlineInfo.tokenLookupContextHandle for Algorithms.FractalRenderer:get_Abort():bool:this set to 0x00007FFB2310D9A9: Invoking compiler for the inlinee method Algorithms.FractalRenderer:get_Abort():bool:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 71 01 00 04 ldfld 0x4000171 IL_0006 6f 97 01 00 0a callvirt 0xA000197 IL_000b 2a ret INLINER impTokenLookupContextHandle for Algorithms.FractalRenderer:get_Abort():bool:this is 0x00007FFB2310D9A9. *************** In fgFindBasicBlocks() for Algorithms.FractalRenderer:get_Abort():bool:this Jump targets: none New Basic Block BB19 [0018] created. BB19 [000..00C) Basic block list for 'Algorithms.FractalRenderer:get_Abort():bool:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB19 [0018] 1 1 [000..00C) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Algorithms.FractalRenderer:get_Abort():bool:this impImportBlockPending for BB19 Importing BB19 (PC=000) of 'Algorithms.FractalRenderer:get_Abort():bool:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 04000171 [ 1] 6 (0x006) callvirt 0A000197 In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is bool, structSize is 0 ** Note: inlinee IL was partially imported -- imported 0 of 12 bytes of method IL *************** in fgTransformIndirectCalls(inlinee) -- no candidates to transform Inlining [000012] failed, so bashing STMT00004 to NOP INLINER: during 'fgInline' result 'failed this callee' reason 'delegate invoke' for 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' calling 'Algorithms.FractalRenderer:get_Abort():bool:this' INLINER: Marking Algorithms.FractalRenderer:get_Abort():bool:this as NOINLINE because of delegate invoke INLINER: during 'fgInline' result 'failed this callee' reason 'delegate invoke' Replacing the return expression placeholder [000013] with [000012] [000013] --C--------- * RET_EXPR int (inl return from call [000012]) Inserting the inline return expression [000012] --C-G------- * CALL int Algorithms.FractalRenderer.get_Abort [000011] ------------ this in rcx \--* LCL_VAR ref V00 this *************** After fgInline() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i BB02 [0001] 1 1 [006..00C)-> BB07 (always) i bwd BB03 [0002] 1 1 [00C..023) i bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) i bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 1 [058..070) i bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) i bwd BB08 [0007] 1 1 [074..07D) i bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) i bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) i bwd BB11 [0010] 2 1 [08D..08E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB09 (always), preds={} succs={BB09} ***** BB01 STMT00000 (IL 0x000...0x001) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V06 loc0 [000000] ------------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) [000005] -A---------- * ASG float [000004] D------N---- +--* LCL_VAR float V07 loc1 [000003] ------------ \--* LCL_VAR float V03 arg3 ------------ BB02 [006..00C) -> BB07 (always), preds={} succs={BB07} ***** BB02 STMT00006 (IL 0x006...0x007) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V08 loc2 [000017] ------------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) [000022] -A---------- * ASG float [000021] D------N---- +--* LCL_VAR float V09 loc3 [000020] ------------ \--* LCL_VAR float V01 arg1 ------------ BB03 [00C..023), preds={} succs={BB04} ***** BB03 STMT00028 (IL 0x00C... ???) [000111] -A---------- * ASG float [000110] -------N---- +--* FIELD float Real [000108] ------------ | \--* ADDR byref [000109] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ \--* LCL_VAR float V09 loc3 ***** BB03 STMT00029 (IL 0x00C... ???) [000115] -A---------- * ASG float [000114] -------N---- +--* FIELD float Imaginary [000112] ------------ | \--* ADDR byref [000113] ------------ | \--* LCL_VAR struct V10 loc4 [000030] ------------ \--* LCL_VAR float V07 loc1 ***** BB03 STMT00010 (IL 0x015... ???) [000035] -A---------- * ASG struct (copy) [000033] D----------- +--* LCL_VAR struct V11 loc5 [000032] ------------ \--* LCL_VAR struct V10 loc4 ***** BB03 STMT00011 (IL 0x019...0x01A) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V12 loc6 [000036] ------------ \--* CNS_INT int 0 ***** BB03 STMT00012 (IL 0x01C...0x021) [000041] -A---------- * ASG float [000040] D------N---- +--* LCL_VAR float V13 loc7 [000039] ------------ \--* CNS_DBL float 0.00000000000000000 ------------ BB04 [023..04F) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00030 (IL 0x023... ???) [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct V15 tmp1 [000142] ------------ \--* CNS_INT int 0 ***** BB04 STMT00034 (IL 0x023... ???) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* FIELD float Real [000117] ------------ | | \--* ADDR byref [000118] ------------ | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | \--* FIELD float Real [000120] ------------ | \--* ADDR byref [000121] ------------ | \--* LCL_VAR struct V11 loc5 [000130] ------------ \--* MUL float [000126] ------------ +--* FIELD float Imaginary [000124] ------------ | \--* ADDR byref [000125] ------------ | \--* LCL_VAR struct V11 loc5 [000129] ------------ \--* FIELD float Imaginary [000127] ------------ \--* ADDR byref [000128] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00035 (IL 0x023... ???) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00032 (IL 0x023... ???) [000153] -A---------- * ASG float [000152] -------N---- +--* FIELD float Real [000149] ------------ | \--* ADDR byref [000150] ------------ | \--* LCL_VAR struct V15 tmp1 [000151] ------------ \--* LCL_VAR float V16 tmp2 ***** BB04 STMT00033 (IL 0x023... ???) [000158] -A---------- * ASG float [000157] -------N---- +--* FIELD float Imaginary [000154] ------------ | \--* ADDR byref [000155] ------------ | \--* LCL_VAR struct V15 tmp1 [000156] ------------ \--* LCL_VAR float V17 tmp3 ***** BB04 STMT00014 (IL ???... ???) [000049] -AC--------- * ASG long [000048] *----------- +--* IND long [000047] ------------ | \--* ADDR byref [000046] ------------ | \--* LCL_VAR struct V11 loc5 [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] ***** BB04 STMT00038 (IL 0x02C... ???) [000187] -A---------- * ASG struct (copy) [000185] D----------- +--* LCL_VAR struct V18 tmp4 [000056] n----------- \--* OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00039 (IL 0x02C... ???) [000190] -A---------- * ASG struct (copy) [000188] D----------- +--* LCL_VAR struct V19 tmp5 [000054] n----------- \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 ***** BB04 STMT00036 (IL 0x02C... ???) [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct V20 tmp6 [000179] ------------ \--* CNS_INT int 0 ***** BB04 STMT00040 (IL 0x02C... ???) [000196] -A---------- * ASG float [000195] -------N---- +--* FIELD float Real [000192] ------------ | \--* ADDR byref [000193] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ \--* ADD float [000166] ------------ +--* FIELD float Real [000165] ------------ | \--* ADDR byref [000164] ------------ | \--* LCL_VAR struct V18 tmp4 [000169] ------------ \--* FIELD float Real [000168] ------------ \--* ADDR byref [000167] ------------ \--* LCL_VAR struct V19 tmp5 ***** BB04 STMT00041 (IL 0x02C... ???) [000201] -A---------- * ASG float [000200] -------N---- +--* FIELD float Imaginary [000197] ------------ | \--* ADDR byref [000198] ------------ | \--* LCL_VAR struct V20 tmp6 [000177] ------------ \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 ***** BB04 STMT00016 (IL ???... ???) [000061] -AC--------- * ASG long [000060] *----------- +--* IND long [000059] ------------ | \--* ADDR byref [000058] ------------ | \--* LCL_VAR struct V11 loc5 [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] ***** BB04 STMT00017 (IL 0x037...0x03B) [000066] -A---------- * ASG int [000065] D------N---- +--* LCL_VAR int V12 loc6 [000064] ------------ \--* ADD int [000062] ------------ +--* LCL_VAR int V12 loc6 [000063] ------------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000217] ------------ \--* ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00020 (IL 0x046...0x04D) [000076] ------------ * JTRUE void [000075] N--------U-- \--* GE int [000073] ------------ +--* LCL_VAR float V13 loc7 [000074] ------------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) [000097] ------------ * JTRUE void [000096] ------------ \--* LT int [000094] ------------ +--* LCL_VAR int V12 loc6 [000095] ------------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..070), preds={} succs={BB07} ***** BB06 STMT00022 (IL ???... ???) [000083] --C-G------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG------- this in rcx +--* FIELD ref _drawPixel [000077] ------------ | \--* LCL_VAR ref V00 this [000080] ------------ arg1 +--* LCL_VAR int V08 loc2 [000081] ------------ arg2 +--* LCL_VAR int V06 loc0 [000082] ------------ arg3 \--* LCL_VAR int V12 loc6 ***** BB06 STMT00023 (IL 0x067... ???) [000088] -A---------- * ASG float [000087] D------N---- +--* LCL_VAR float V09 loc3 [000086] ------------ \--* ADD float [000084] ------------ +--* LCL_VAR float V09 loc3 [000085] ------------ \--* LCL_VAR float V05 arg5 ***** BB06 STMT00024 (IL 0x06C...0x06F) [000093] -A---------- * ASG int [000092] D------N---- +--* LCL_VAR int V08 loc2 [000091] ------------ \--* ADD int [000089] ------------ +--* LCL_VAR int V08 loc2 [000090] ------------ \--* CNS_INT int 1 ------------ BB07 [070..074) -> BB03 (cond), preds={} succs={BB08,BB03} ***** BB07 STMT00008 (IL 0x070...0x072) [000026] ------------ * JTRUE void [000025] ------------ \--* LT int [000023] ------------ +--* LCL_VAR float V09 loc3 [000024] ------------ \--* LCL_VAR float V02 arg2 ------------ BB08 [074..07D), preds={} succs={BB09} ***** BB08 STMT00026 (IL 0x074...0x078) [000102] -A---------- * ASG float [000101] D------N---- +--* LCL_VAR float V07 loc1 [000100] ------------ \--* ADD float [000098] ------------ +--* LCL_VAR float V07 loc1 [000099] ------------ \--* LCL_VAR float V05 arg5 ***** BB08 STMT00027 (IL 0x079...0x07C) [000107] -A---------- * ASG int [000106] D------N---- +--* LCL_VAR int V06 loc0 [000105] ------------ \--* ADD int [000103] ------------ +--* LCL_VAR int V06 loc0 [000104] ------------ \--* CNS_INT int 1 ------------ BB09 [07D..082) -> BB11 (cond), preds={} succs={BB10,BB11} ***** BB09 STMT00002 (IL 0x07D...0x080) [000009] ------------ * JTRUE void [000008] N--------U-- \--* GE int [000006] ------------ +--* LCL_VAR float V07 loc1 [000007] ------------ \--* LCL_VAR float V04 arg4 ------------ BB10 [082..08D) -> BB02 (cond), preds={} succs={BB11,BB02} ***** BB10 STMT00005 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000012] --C-G------- +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this [000014] ------------ \--* CNS_INT int 0 ------------ BB11 [08D..08E) (return), preds={} succs={} ***** BB11 STMT00003 (IL 0x08D...0x08D) [000010] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty **************** Inline Tree Inlines into 060002B2 Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this [1 IL=0016 TR=000031 06000297] [aggressive inline attribute] Algorithms.ComplexFloat:.ctor(float,float):this [2 IL=0037 TR=000044 06000298] [aggressive inline attribute] Algorithms.ComplexFloat:square():Algorithms.ComplexFloat:this [3 IL=0046 TR=000146 06000297] [aggressive inline attribute] Algorithms.ComplexFloat:.ctor(float,float):this [4 IL=0048 TR=000052 0600029B] [aggressive inline attribute] Algorithms.ComplexFloat:op_Addition(Algorithms.ComplexFloat,Algorithms.ComplexFloat):Algorithms.ComplexFloat [5 IL=0026 TR=000183 06000297] [aggressive inline attribute] Algorithms.ComplexFloat:.ctor(float,float):this [6 IL=0063 TR=000069 06000299] [aggressive inline attribute] Algorithms.ComplexFloat:sqabs():float:this [7 IL=0089 TR=000078 060002A9] [below ALWAYS_INLINE size] Algorithms.FractalRenderer:get_DrawPixel():System.Action`3[Int32,Int32,Int32]:this [0 IL=0098 TR=000083 06000E3F] [FAILED: cannot get method info] System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32]:Invoke(int,int,int):this [0 IL=0131 TR=000012 060002AA] [FAILED: delegate invoke] Algorithms.FractalRenderer:get_Abort():bool:this Budget: initialTime=486, finalTime=646, initialBudget=4860, currentBudget=5048 Budget: increased by 188 because of force inlines Budget: initialSize=3368, finalSize=3368 *************** In Allocate Objects Trees before Allocate Objects ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i BB02 [0001] 1 1 [006..00C)-> BB07 (always) i bwd BB03 [0002] 1 1 [00C..023) i bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) i bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 1 [058..070) i bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) i bwd BB08 [0007] 1 1 [074..07D) i bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) i bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) i bwd BB11 [0010] 2 1 [08D..08E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB09 (always), preds={} succs={BB09} ***** BB01 STMT00000 (IL 0x000...0x001) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V06 loc0 [000000] ------------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) [000005] -A---------- * ASG float [000004] D------N---- +--* LCL_VAR float V07 loc1 [000003] ------------ \--* LCL_VAR float V03 arg3 ------------ BB02 [006..00C) -> BB07 (always), preds={} succs={BB07} ***** BB02 STMT00006 (IL 0x006...0x007) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V08 loc2 [000017] ------------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) [000022] -A---------- * ASG float [000021] D------N---- +--* LCL_VAR float V09 loc3 [000020] ------------ \--* LCL_VAR float V01 arg1 ------------ BB03 [00C..023), preds={} succs={BB04} ***** BB03 STMT00028 (IL 0x00C... ???) [000111] -A---------- * ASG float [000110] -------N---- +--* FIELD float Real [000108] ------------ | \--* ADDR byref [000109] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ \--* LCL_VAR float V09 loc3 ***** BB03 STMT00029 (IL 0x00C... ???) [000115] -A---------- * ASG float [000114] -------N---- +--* FIELD float Imaginary [000112] ------------ | \--* ADDR byref [000113] ------------ | \--* LCL_VAR struct V10 loc4 [000030] ------------ \--* LCL_VAR float V07 loc1 ***** BB03 STMT00010 (IL 0x015... ???) [000035] -A---------- * ASG struct (copy) [000033] D----------- +--* LCL_VAR struct V11 loc5 [000032] ------------ \--* LCL_VAR struct V10 loc4 ***** BB03 STMT00011 (IL 0x019...0x01A) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V12 loc6 [000036] ------------ \--* CNS_INT int 0 ***** BB03 STMT00012 (IL 0x01C...0x021) [000041] -A---------- * ASG float [000040] D------N---- +--* LCL_VAR float V13 loc7 [000039] ------------ \--* CNS_DBL float 0.00000000000000000 ------------ BB04 [023..04F) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00030 (IL 0x023... ???) [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct V15 tmp1 [000142] ------------ \--* CNS_INT int 0 ***** BB04 STMT00034 (IL 0x023... ???) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* FIELD float Real [000117] ------------ | | \--* ADDR byref [000118] ------------ | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | \--* FIELD float Real [000120] ------------ | \--* ADDR byref [000121] ------------ | \--* LCL_VAR struct V11 loc5 [000130] ------------ \--* MUL float [000126] ------------ +--* FIELD float Imaginary [000124] ------------ | \--* ADDR byref [000125] ------------ | \--* LCL_VAR struct V11 loc5 [000129] ------------ \--* FIELD float Imaginary [000127] ------------ \--* ADDR byref [000128] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00035 (IL 0x023... ???) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00032 (IL 0x023... ???) [000153] -A---------- * ASG float [000152] -------N---- +--* FIELD float Real [000149] ------------ | \--* ADDR byref [000150] ------------ | \--* LCL_VAR struct V15 tmp1 [000151] ------------ \--* LCL_VAR float V16 tmp2 ***** BB04 STMT00033 (IL 0x023... ???) [000158] -A---------- * ASG float [000157] -------N---- +--* FIELD float Imaginary [000154] ------------ | \--* ADDR byref [000155] ------------ | \--* LCL_VAR struct V15 tmp1 [000156] ------------ \--* LCL_VAR float V17 tmp3 ***** BB04 STMT00014 (IL ???... ???) [000049] -AC--------- * ASG long [000048] *----------- +--* IND long [000047] ------------ | \--* ADDR byref [000046] ------------ | \--* LCL_VAR struct V11 loc5 [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] ***** BB04 STMT00038 (IL 0x02C... ???) [000187] -A---------- * ASG struct (copy) [000185] D----------- +--* LCL_VAR struct V18 tmp4 [000056] n----------- \--* OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00039 (IL 0x02C... ???) [000190] -A---------- * ASG struct (copy) [000188] D----------- +--* LCL_VAR struct V19 tmp5 [000054] n----------- \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 ***** BB04 STMT00036 (IL 0x02C... ???) [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct V20 tmp6 [000179] ------------ \--* CNS_INT int 0 ***** BB04 STMT00040 (IL 0x02C... ???) [000196] -A---------- * ASG float [000195] -------N---- +--* FIELD float Real [000192] ------------ | \--* ADDR byref [000193] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ \--* ADD float [000166] ------------ +--* FIELD float Real [000165] ------------ | \--* ADDR byref [000164] ------------ | \--* LCL_VAR struct V18 tmp4 [000169] ------------ \--* FIELD float Real [000168] ------------ \--* ADDR byref [000167] ------------ \--* LCL_VAR struct V19 tmp5 ***** BB04 STMT00041 (IL 0x02C... ???) [000201] -A---------- * ASG float [000200] -------N---- +--* FIELD float Imaginary [000197] ------------ | \--* ADDR byref [000198] ------------ | \--* LCL_VAR struct V20 tmp6 [000177] ------------ \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 ***** BB04 STMT00016 (IL ???... ???) [000061] -AC--------- * ASG long [000060] *----------- +--* IND long [000059] ------------ | \--* ADDR byref [000058] ------------ | \--* LCL_VAR struct V11 loc5 [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] ***** BB04 STMT00017 (IL 0x037...0x03B) [000066] -A---------- * ASG int [000065] D------N---- +--* LCL_VAR int V12 loc6 [000064] ------------ \--* ADD int [000062] ------------ +--* LCL_VAR int V12 loc6 [000063] ------------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000217] ------------ \--* ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00020 (IL 0x046...0x04D) [000076] ------------ * JTRUE void [000075] N--------U-- \--* GE int [000073] ------------ +--* LCL_VAR float V13 loc7 [000074] ------------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) [000097] ------------ * JTRUE void [000096] ------------ \--* LT int [000094] ------------ +--* LCL_VAR int V12 loc6 [000095] ------------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..070), preds={} succs={BB07} ***** BB06 STMT00022 (IL ???... ???) [000083] --C-G------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG------- this in rcx +--* FIELD ref _drawPixel [000077] ------------ | \--* LCL_VAR ref V00 this [000080] ------------ arg1 +--* LCL_VAR int V08 loc2 [000081] ------------ arg2 +--* LCL_VAR int V06 loc0 [000082] ------------ arg3 \--* LCL_VAR int V12 loc6 ***** BB06 STMT00023 (IL 0x067... ???) [000088] -A---------- * ASG float [000087] D------N---- +--* LCL_VAR float V09 loc3 [000086] ------------ \--* ADD float [000084] ------------ +--* LCL_VAR float V09 loc3 [000085] ------------ \--* LCL_VAR float V05 arg5 ***** BB06 STMT00024 (IL 0x06C...0x06F) [000093] -A---------- * ASG int [000092] D------N---- +--* LCL_VAR int V08 loc2 [000091] ------------ \--* ADD int [000089] ------------ +--* LCL_VAR int V08 loc2 [000090] ------------ \--* CNS_INT int 1 ------------ BB07 [070..074) -> BB03 (cond), preds={} succs={BB08,BB03} ***** BB07 STMT00008 (IL 0x070...0x072) [000026] ------------ * JTRUE void [000025] ------------ \--* LT int [000023] ------------ +--* LCL_VAR float V09 loc3 [000024] ------------ \--* LCL_VAR float V02 arg2 ------------ BB08 [074..07D), preds={} succs={BB09} ***** BB08 STMT00026 (IL 0x074...0x078) [000102] -A---------- * ASG float [000101] D------N---- +--* LCL_VAR float V07 loc1 [000100] ------------ \--* ADD float [000098] ------------ +--* LCL_VAR float V07 loc1 [000099] ------------ \--* LCL_VAR float V05 arg5 ***** BB08 STMT00027 (IL 0x079...0x07C) [000107] -A---------- * ASG int [000106] D------N---- +--* LCL_VAR int V06 loc0 [000105] ------------ \--* ADD int [000103] ------------ +--* LCL_VAR int V06 loc0 [000104] ------------ \--* CNS_INT int 1 ------------ BB09 [07D..082) -> BB11 (cond), preds={} succs={BB10,BB11} ***** BB09 STMT00002 (IL 0x07D...0x080) [000009] ------------ * JTRUE void [000008] N--------U-- \--* GE int [000006] ------------ +--* LCL_VAR float V07 loc1 [000007] ------------ \--* LCL_VAR float V04 arg4 ------------ BB10 [082..08D) -> BB02 (cond), preds={} succs={BB11,BB02} ***** BB10 STMT00005 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000012] --C-G------- +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this [000014] ------------ \--* CNS_INT int 0 ------------ BB11 [08D..08E) (return), preds={} succs={} ***** BB11 STMT00003 (IL 0x08D...0x08D) [000010] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *** ObjectAllocationPhase: no newobjs in this method; punting *************** Exiting Allocate Objects Trees after Allocate Objects ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i BB02 [0001] 1 1 [006..00C)-> BB07 (always) i bwd BB03 [0002] 1 1 [00C..023) i bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) i bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 1 [058..070) i bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) i bwd BB08 [0007] 1 1 [074..07D) i bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) i bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) i bwd BB11 [0010] 2 1 [08D..08E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB09 (always), preds={} succs={BB09} ***** BB01 STMT00000 (IL 0x000...0x001) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V06 loc0 [000000] ------------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) [000005] -A---------- * ASG float [000004] D------N---- +--* LCL_VAR float V07 loc1 [000003] ------------ \--* LCL_VAR float V03 arg3 ------------ BB02 [006..00C) -> BB07 (always), preds={} succs={BB07} ***** BB02 STMT00006 (IL 0x006...0x007) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V08 loc2 [000017] ------------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) [000022] -A---------- * ASG float [000021] D------N---- +--* LCL_VAR float V09 loc3 [000020] ------------ \--* LCL_VAR float V01 arg1 ------------ BB03 [00C..023), preds={} succs={BB04} ***** BB03 STMT00028 (IL 0x00C... ???) [000111] -A---------- * ASG float [000110] -------N---- +--* FIELD float Real [000108] ------------ | \--* ADDR byref [000109] ------------ | \--* LCL_VAR struct V10 loc4 [000029] ------------ \--* LCL_VAR float V09 loc3 ***** BB03 STMT00029 (IL 0x00C... ???) [000115] -A---------- * ASG float [000114] -------N---- +--* FIELD float Imaginary [000112] ------------ | \--* ADDR byref [000113] ------------ | \--* LCL_VAR struct V10 loc4 [000030] ------------ \--* LCL_VAR float V07 loc1 ***** BB03 STMT00010 (IL 0x015... ???) [000035] -A---------- * ASG struct (copy) [000033] D----------- +--* LCL_VAR struct V11 loc5 [000032] ------------ \--* LCL_VAR struct V10 loc4 ***** BB03 STMT00011 (IL 0x019...0x01A) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V12 loc6 [000036] ------------ \--* CNS_INT int 0 ***** BB03 STMT00012 (IL 0x01C...0x021) [000041] -A---------- * ASG float [000040] D------N---- +--* LCL_VAR float V13 loc7 [000039] ------------ \--* CNS_DBL float 0.00000000000000000 ------------ BB04 [023..04F) -> BB06 (cond), preds={} succs={BB05,BB06} ***** BB04 STMT00030 (IL 0x023... ???) [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct V15 tmp1 [000142] ------------ \--* CNS_INT int 0 ***** BB04 STMT00034 (IL 0x023... ???) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* FIELD float Real [000117] ------------ | | \--* ADDR byref [000118] ------------ | | \--* LCL_VAR struct V11 loc5 [000122] ------------ | \--* FIELD float Real [000120] ------------ | \--* ADDR byref [000121] ------------ | \--* LCL_VAR struct V11 loc5 [000130] ------------ \--* MUL float [000126] ------------ +--* FIELD float Imaginary [000124] ------------ | \--* ADDR byref [000125] ------------ | \--* LCL_VAR struct V11 loc5 [000129] ------------ \--* FIELD float Imaginary [000127] ------------ \--* ADDR byref [000128] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00035 (IL 0x023... ???) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct V11 loc5 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00032 (IL 0x023... ???) [000153] -A---------- * ASG float [000152] -------N---- +--* FIELD float Real [000149] ------------ | \--* ADDR byref [000150] ------------ | \--* LCL_VAR struct V15 tmp1 [000151] ------------ \--* LCL_VAR float V16 tmp2 ***** BB04 STMT00033 (IL 0x023... ???) [000158] -A---------- * ASG float [000157] -------N---- +--* FIELD float Imaginary [000154] ------------ | \--* ADDR byref [000155] ------------ | \--* LCL_VAR struct V15 tmp1 [000156] ------------ \--* LCL_VAR float V17 tmp3 ***** BB04 STMT00014 (IL ???... ???) [000049] -AC--------- * ASG long [000048] *----------- +--* IND long [000047] ------------ | \--* ADDR byref [000046] ------------ | \--* LCL_VAR struct V11 loc5 [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] ***** BB04 STMT00038 (IL 0x02C... ???) [000187] -A---------- * ASG struct (copy) [000185] D----------- +--* LCL_VAR struct V18 tmp4 [000056] n----------- \--* OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00039 (IL 0x02C... ???) [000190] -A---------- * ASG struct (copy) [000188] D----------- +--* LCL_VAR struct V19 tmp5 [000054] n----------- \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct V10 loc4 ***** BB04 STMT00036 (IL 0x02C... ???) [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct V20 tmp6 [000179] ------------ \--* CNS_INT int 0 ***** BB04 STMT00040 (IL 0x02C... ???) [000196] -A---------- * ASG float [000195] -------N---- +--* FIELD float Real [000192] ------------ | \--* ADDR byref [000193] ------------ | \--* LCL_VAR struct V20 tmp6 [000170] ------------ \--* ADD float [000166] ------------ +--* FIELD float Real [000165] ------------ | \--* ADDR byref [000164] ------------ | \--* LCL_VAR struct V18 tmp4 [000169] ------------ \--* FIELD float Real [000168] ------------ \--* ADDR byref [000167] ------------ \--* LCL_VAR struct V19 tmp5 ***** BB04 STMT00041 (IL 0x02C... ???) [000201] -A---------- * ASG float [000200] -------N---- +--* FIELD float Imaginary [000197] ------------ | \--* ADDR byref [000198] ------------ | \--* LCL_VAR struct V20 tmp6 [000177] ------------ \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct V18 tmp4 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct V19 tmp5 ***** BB04 STMT00016 (IL ???... ???) [000061] -AC--------- * ASG long [000060] *----------- +--* IND long [000059] ------------ | \--* ADDR byref [000058] ------------ | \--* LCL_VAR struct V11 loc5 [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] ***** BB04 STMT00017 (IL 0x037...0x03B) [000066] -A---------- * ASG int [000065] D------N---- +--* LCL_VAR int V12 loc6 [000064] ------------ \--* ADD int [000062] ------------ +--* LCL_VAR int V12 loc6 [000063] ------------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000217] ------------ \--* ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct V11 loc5 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct V11 loc5 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct V11 loc5 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct V11 loc5 ***** BB04 STMT00020 (IL 0x046...0x04D) [000076] ------------ * JTRUE void [000075] N--------U-- \--* GE int [000073] ------------ +--* LCL_VAR float V13 loc7 [000074] ------------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) [000097] ------------ * JTRUE void [000096] ------------ \--* LT int [000094] ------------ +--* LCL_VAR int V12 loc6 [000095] ------------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..070), preds={} succs={BB07} ***** BB06 STMT00022 (IL ???... ???) [000083] --C-G------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG------- this in rcx +--* FIELD ref _drawPixel [000077] ------------ | \--* LCL_VAR ref V00 this [000080] ------------ arg1 +--* LCL_VAR int V08 loc2 [000081] ------------ arg2 +--* LCL_VAR int V06 loc0 [000082] ------------ arg3 \--* LCL_VAR int V12 loc6 ***** BB06 STMT00023 (IL 0x067... ???) [000088] -A---------- * ASG float [000087] D------N---- +--* LCL_VAR float V09 loc3 [000086] ------------ \--* ADD float [000084] ------------ +--* LCL_VAR float V09 loc3 [000085] ------------ \--* LCL_VAR float V05 arg5 ***** BB06 STMT00024 (IL 0x06C...0x06F) [000093] -A---------- * ASG int [000092] D------N---- +--* LCL_VAR int V08 loc2 [000091] ------------ \--* ADD int [000089] ------------ +--* LCL_VAR int V08 loc2 [000090] ------------ \--* CNS_INT int 1 ------------ BB07 [070..074) -> BB03 (cond), preds={} succs={BB08,BB03} ***** BB07 STMT00008 (IL 0x070...0x072) [000026] ------------ * JTRUE void [000025] ------------ \--* LT int [000023] ------------ +--* LCL_VAR float V09 loc3 [000024] ------------ \--* LCL_VAR float V02 arg2 ------------ BB08 [074..07D), preds={} succs={BB09} ***** BB08 STMT00026 (IL 0x074...0x078) [000102] -A---------- * ASG float [000101] D------N---- +--* LCL_VAR float V07 loc1 [000100] ------------ \--* ADD float [000098] ------------ +--* LCL_VAR float V07 loc1 [000099] ------------ \--* LCL_VAR float V05 arg5 ***** BB08 STMT00027 (IL 0x079...0x07C) [000107] -A---------- * ASG int [000106] D------N---- +--* LCL_VAR int V06 loc0 [000105] ------------ \--* ADD int [000103] ------------ +--* LCL_VAR int V06 loc0 [000104] ------------ \--* CNS_INT int 1 ------------ BB09 [07D..082) -> BB11 (cond), preds={} succs={BB10,BB11} ***** BB09 STMT00002 (IL 0x07D...0x080) [000009] ------------ * JTRUE void [000008] N--------U-- \--* GE int [000006] ------------ +--* LCL_VAR float V07 loc1 [000007] ------------ \--* LCL_VAR float V04 arg4 ------------ BB10 [082..08D) -> BB02 (cond), preds={} succs={BB11,BB02} ***** BB10 STMT00005 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000012] --C-G------- +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this [000014] ------------ \--* CNS_INT int 0 ------------ BB11 [08D..08E) (return), preds={} succs={} ***** BB11 STMT00003 (IL 0x08D...0x08D) [000010] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i BB02 [0001] 1 1 [006..00C)-> BB07 (always) i bwd BB03 [0002] 1 1 [00C..023) i bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) i bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 1 [058..070) i bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) i bwd BB08 [0007] 1 1 [074..07D) i bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) i bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) i bwd BB11 [0010] 2 1 [08D..08E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** In fgRemoveEmptyFinally() No EH in this method, nothing to remove. *************** In fgMergeFinallyChains() No EH in this method, nothing to merge. *************** In fgCloneFinally() No EH in this method, no cloning. *************** In fgResetImplicitByRefRefCount() *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 float ; V02 arg2 float ; V03 arg3 float ; V04 arg4 float ; V05 arg5 float ; V06 loc0 int ; V07 loc1 float ; V08 loc2 int ; V09 loc3 float ; V10 loc4 struct ( 8) ld-addr-op ; V11 loc5 struct ( 8) ld-addr-op ; V12 loc6 int ; V13 loc7 float ; V14 OutArgs lclBlk (na) "OutgoingArgSpace" ; V15 tmp1 struct ( 8) "NewObj constructor temp" ; V16 tmp2 float "Inlining Arg" ; V17 tmp3 float "Inlining Arg" ; V18 tmp4 struct ( 8) "Inlining Arg" ; V19 tmp5 struct ( 8) "Inlining Arg" ; V20 tmp6 struct ( 8) "NewObj constructor temp" ; V21 tmp7 float "Inlining Arg" ; V22 tmp8 float "Inlining Arg" Promoting struct local V10 (Algorithms.ComplexFloat): lvaGrabTemp returning 23 (V23 tmp9) (a long lifetime temp) called for field V10.Real (fldOffset=0x0). lvaGrabTemp returning 24 (V24 tmp10) (a long lifetime temp) called for field V10.Imaginary (fldOffset=0x4). Promoting struct local V11 (Algorithms.ComplexFloat): lvaGrabTemp returning 25 (V25 tmp11) (a long lifetime temp) called for field V11.Real (fldOffset=0x0). lvaGrabTemp returning 26 (V26 tmp12) (a long lifetime temp) called for field V11.Imaginary (fldOffset=0x4). Promoting struct local V15 (Algorithms.ComplexFloat): lvaGrabTemp returning 27 (V27 tmp13) (a long lifetime temp) called for field V15.Real (fldOffset=0x0). lvaGrabTemp returning 28 (V28 tmp14) (a long lifetime temp) called for field V15.Imaginary (fldOffset=0x4). Promoting struct local V18 (Algorithms.ComplexFloat): lvaGrabTemp returning 29 (V29 tmp15) (a long lifetime temp) called for field V18.Real (fldOffset=0x0). lvaGrabTemp returning 30 (V30 tmp16) (a long lifetime temp) called for field V18.Imaginary (fldOffset=0x4). Promoting struct local V19 (Algorithms.ComplexFloat): lvaGrabTemp returning 31 (V31 tmp17) (a long lifetime temp) called for field V19.Real (fldOffset=0x0). lvaGrabTemp returning 32 (V32 tmp18) (a long lifetime temp) called for field V19.Imaginary (fldOffset=0x4). Promoting struct local V20 (Algorithms.ComplexFloat): lvaGrabTemp returning 33 (V33 tmp19) (a long lifetime temp) called for field V20.Real (fldOffset=0x0). lvaGrabTemp returning 34 (V34 tmp20) (a long lifetime temp) called for field V20.Imaginary (fldOffset=0x4). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 float ; V02 arg2 float ; V03 arg3 float ; V04 arg4 float ; V05 arg5 float ; V06 loc0 int ; V07 loc1 float ; V08 loc2 int ; V09 loc3 float ; V10 loc4 struct ( 8) ld-addr-op ; V11 loc5 struct ( 8) ld-addr-op ; V12 loc6 int ; V13 loc7 float ; V14 OutArgs lclBlk (na) "OutgoingArgSpace" ; V15 tmp1 struct ( 8) "NewObj constructor temp" ; V16 tmp2 float "Inlining Arg" ; V17 tmp3 float "Inlining Arg" ; V18 tmp4 struct ( 8) "Inlining Arg" ; V19 tmp5 struct ( 8) "Inlining Arg" ; V20 tmp6 struct ( 8) "NewObj constructor temp" ; V21 tmp7 float "Inlining Arg" ; V22 tmp8 float "Inlining Arg" ; V23 tmp9 float V10.Real(offs=0x00) P-INDEP "field V10.Real (fldOffset=0x0)" ; V24 tmp10 float V10.Imaginary(offs=0x04) P-INDEP "field V10.Imaginary (fldOffset=0x4)" ; V25 tmp11 float V11.Real(offs=0x00) P-INDEP "field V11.Real (fldOffset=0x0)" ; V26 tmp12 float V11.Imaginary(offs=0x04) P-INDEP "field V11.Imaginary (fldOffset=0x4)" ; V27 tmp13 float V15.Real(offs=0x00) P-INDEP "field V15.Real (fldOffset=0x0)" ; V28 tmp14 float V15.Imaginary(offs=0x04) P-INDEP "field V15.Imaginary (fldOffset=0x4)" ; V29 tmp15 float V18.Real(offs=0x00) P-INDEP "field V18.Real (fldOffset=0x0)" ; V30 tmp16 float V18.Imaginary(offs=0x04) P-INDEP "field V18.Imaginary (fldOffset=0x4)" ; V31 tmp17 float V19.Real(offs=0x00) P-INDEP "field V19.Real (fldOffset=0x0)" ; V32 tmp18 float V19.Imaginary(offs=0x04) P-INDEP "field V19.Imaginary (fldOffset=0x4)" ; V33 tmp19 float V20.Real(offs=0x00) P-INDEP "field V20.Real (fldOffset=0x0)" ; V34 tmp20 float V20.Imaginary(offs=0x04) P-INDEP "field V20.Imaginary (fldOffset=0x4)" *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x001) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V06 loc0 [000000] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00001 (IL 0x002...0x003) [000005] -A---------- * ASG float [000004] D------N---- +--* LCL_VAR float V07 loc1 [000003] ------------ \--* LCL_VAR float V03 arg3 LocalAddressVisitor visiting statement: STMT00006 (IL 0x006...0x007) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V08 loc2 [000017] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00007 (IL 0x008...0x009) [000022] -A---------- * ASG float [000021] D------N---- +--* LCL_VAR float V09 loc3 [000020] ------------ \--* LCL_VAR float V01 arg1 LocalAddressVisitor visiting statement: STMT00028 (IL 0x00C... ???) [000111] -A---------- * ASG float [000110] -------N---- +--* FIELD float Real [000108] ------------ | \--* ADDR byref [000109] ------------ | \--* LCL_VAR struct(P) V10 loc4 | \--* float V10.Real (offs=0x00) -> V23 tmp9 | \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 [000029] ------------ \--* LCL_VAR float V09 loc3 Replacing the field in promoted struct with local var V23 LocalAddressVisitor modified statement: STMT00028 (IL 0x00C... ???) [000111] -A---------- * ASG float [000110] D------N---- +--* LCL_VAR float V23 tmp9 [000029] ------------ \--* LCL_VAR float V09 loc3 LocalAddressVisitor visiting statement: STMT00029 (IL 0x00C... ???) [000115] -A---------- * ASG float [000114] -------N---- +--* FIELD float Imaginary [000112] ------------ | \--* ADDR byref [000113] ------------ | \--* LCL_VAR struct(P) V10 loc4 | \--* float V10.Real (offs=0x00) -> V23 tmp9 | \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 [000030] ------------ \--* LCL_VAR float V07 loc1 Replacing the field in promoted struct with local var V24 LocalAddressVisitor modified statement: STMT00029 (IL 0x00C... ???) [000115] -A---------- * ASG float [000114] D------N---- +--* LCL_VAR float V24 tmp10 [000030] ------------ \--* LCL_VAR float V07 loc1 LocalAddressVisitor visiting statement: STMT00010 (IL 0x015... ???) [000035] -A---------- * ASG struct (copy) [000033] D----------- +--* LCL_VAR struct(P) V11 loc5 +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000032] ------------ \--* LCL_VAR struct(P) V10 loc4 \--* float V10.Real (offs=0x00) -> V23 tmp9 \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 LocalAddressVisitor visiting statement: STMT00011 (IL 0x019...0x01A) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V12 loc6 [000036] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00012 (IL 0x01C...0x021) [000041] -A---------- * ASG float [000040] D------N---- +--* LCL_VAR float V13 loc7 [000039] ------------ \--* CNS_DBL float 0.00000000000000000 LocalAddressVisitor visiting statement: STMT00030 (IL 0x023... ???) [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct(P) V15 tmp1 +--* float V15.Real (offs=0x00) -> V27 tmp13 +--* float V15.Imaginary (offs=0x04) -> V28 tmp14 [000142] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00034 (IL 0x023... ???) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* FIELD float Real [000117] ------------ | | \--* ADDR byref [000118] ------------ | | \--* LCL_VAR struct(P) V11 loc5 | | \--* float V11.Real (offs=0x00) -> V25 tmp11 | | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000122] ------------ | \--* FIELD float Real [000120] ------------ | \--* ADDR byref [000121] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000130] ------------ \--* MUL float [000126] ------------ +--* FIELD float Imaginary [000124] ------------ | \--* ADDR byref [000125] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000129] ------------ \--* FIELD float Imaginary [000127] ------------ \--* ADDR byref [000128] ------------ \--* LCL_VAR struct(P) V11 loc5 \--* float V11.Real (offs=0x00) -> V25 tmp11 \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 Replacing the field in promoted struct with local var V25 Replacing the field in promoted struct with local var V25 Replacing the field in promoted struct with local var V26 Replacing the field in promoted struct with local var V26 LocalAddressVisitor modified statement: STMT00034 (IL 0x023... ???) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* LCL_VAR float V25 tmp11 [000122] ------------ | \--* LCL_VAR float V25 tmp11 [000130] ------------ \--* MUL float [000126] ------------ +--* LCL_VAR float V26 tmp12 [000129] ------------ \--* LCL_VAR float V26 tmp12 LocalAddressVisitor visiting statement: STMT00035 (IL 0x023... ???) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* FIELD float Real [000133] ------------ | \--* ADDR byref [000134] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000139] ------------ \--* FIELD float Imaginary [000137] ------------ \--* ADDR byref [000138] ------------ \--* LCL_VAR struct(P) V11 loc5 \--* float V11.Real (offs=0x00) -> V25 tmp11 \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 Replacing the field in promoted struct with local var V25 Replacing the field in promoted struct with local var V26 LocalAddressVisitor modified statement: STMT00035 (IL 0x023... ???) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* LCL_VAR float V25 tmp11 [000139] ------------ \--* LCL_VAR float V26 tmp12 LocalAddressVisitor visiting statement: STMT00032 (IL 0x023... ???) [000153] -A---------- * ASG float [000152] -------N---- +--* FIELD float Real [000149] ------------ | \--* ADDR byref [000150] ------------ | \--* LCL_VAR struct(P) V15 tmp1 | \--* float V15.Real (offs=0x00) -> V27 tmp13 | \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 [000151] ------------ \--* LCL_VAR float V16 tmp2 Replacing the field in promoted struct with local var V27 LocalAddressVisitor modified statement: STMT00032 (IL 0x023... ???) [000153] -A---------- * ASG float [000152] D------N---- +--* LCL_VAR float V27 tmp13 [000151] ------------ \--* LCL_VAR float V16 tmp2 LocalAddressVisitor visiting statement: STMT00033 (IL 0x023... ???) [000158] -A---------- * ASG float [000157] -------N---- +--* FIELD float Imaginary [000154] ------------ | \--* ADDR byref [000155] ------------ | \--* LCL_VAR struct(P) V15 tmp1 | \--* float V15.Real (offs=0x00) -> V27 tmp13 | \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 [000156] ------------ \--* LCL_VAR float V17 tmp3 Replacing the field in promoted struct with local var V28 LocalAddressVisitor modified statement: STMT00033 (IL 0x023... ???) [000158] -A---------- * ASG float [000157] D------N---- +--* LCL_VAR float V28 tmp14 [000156] ------------ \--* LCL_VAR float V17 tmp3 LocalAddressVisitor visiting statement: STMT00014 (IL ???... ???) [000049] -AC--------- * ASG long [000048] *----------- +--* IND long [000047] ------------ | \--* ADDR byref [000046] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 Local V15 should not be enregistered because: was accessed as a local field LocalAddressVisitor visiting statement: STMT00038 (IL 0x02C... ???) [000187] -A---------- * ASG struct (copy) [000185] D----------- +--* LCL_VAR struct(P) V18 tmp4 +--* float V18.Real (offs=0x00) -> V29 tmp15 +--* float V18.Imaginary (offs=0x04) -> V30 tmp16 [000056] n----------- \--* OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct(P) V11 loc5 \--* float V11.Real (offs=0x00) -> V25 tmp11 \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 LocalAddressVisitor visiting statement: STMT00039 (IL 0x02C... ???) [000190] -A---------- * ASG struct (copy) [000188] D----------- +--* LCL_VAR struct(P) V19 tmp5 +--* float V19.Real (offs=0x00) -> V31 tmp17 +--* float V19.Imaginary (offs=0x04) -> V32 tmp18 [000054] n----------- \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct(P) V10 loc4 \--* float V10.Real (offs=0x00) -> V23 tmp9 \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 LocalAddressVisitor visiting statement: STMT00036 (IL 0x02C... ???) [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct(P) V20 tmp6 +--* float V20.Real (offs=0x00) -> V33 tmp19 +--* float V20.Imaginary (offs=0x04) -> V34 tmp20 [000179] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00040 (IL 0x02C... ???) [000196] -A---------- * ASG float [000195] -------N---- +--* FIELD float Real [000192] ------------ | \--* ADDR byref [000193] ------------ | \--* LCL_VAR struct(P) V20 tmp6 | \--* float V20.Real (offs=0x00) -> V33 tmp19 | \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 [000170] ------------ \--* ADD float [000166] ------------ +--* FIELD float Real [000165] ------------ | \--* ADDR byref [000164] ------------ | \--* LCL_VAR struct(P) V18 tmp4 | \--* float V18.Real (offs=0x00) -> V29 tmp15 | \--* float V18.Imaginary (offs=0x04) -> V30 tmp16 [000169] ------------ \--* FIELD float Real [000168] ------------ \--* ADDR byref [000167] ------------ \--* LCL_VAR struct(P) V19 tmp5 \--* float V19.Real (offs=0x00) -> V31 tmp17 \--* float V19.Imaginary (offs=0x04) -> V32 tmp18 Replacing the field in promoted struct with local var V33 Replacing the field in promoted struct with local var V29 Replacing the field in promoted struct with local var V31 LocalAddressVisitor modified statement: STMT00040 (IL 0x02C... ???) [000196] -A---------- * ASG float [000195] D------N---- +--* LCL_VAR float V33 tmp19 [000170] ------------ \--* ADD float [000166] ------------ +--* LCL_VAR float V29 tmp15 [000169] ------------ \--* LCL_VAR float V31 tmp17 LocalAddressVisitor visiting statement: STMT00041 (IL 0x02C... ???) [000201] -A---------- * ASG float [000200] -------N---- +--* FIELD float Imaginary [000197] ------------ | \--* ADDR byref [000198] ------------ | \--* LCL_VAR struct(P) V20 tmp6 | \--* float V20.Real (offs=0x00) -> V33 tmp19 | \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 [000177] ------------ \--* ADD float [000173] ------------ +--* FIELD float Imaginary [000172] ------------ | \--* ADDR byref [000171] ------------ | \--* LCL_VAR struct(P) V18 tmp4 | \--* float V18.Real (offs=0x00) -> V29 tmp15 | \--* float V18.Imaginary (offs=0x04) -> V30 tmp16 [000176] ------------ \--* FIELD float Imaginary [000175] ------------ \--* ADDR byref [000174] ------------ \--* LCL_VAR struct(P) V19 tmp5 \--* float V19.Real (offs=0x00) -> V31 tmp17 \--* float V19.Imaginary (offs=0x04) -> V32 tmp18 Replacing the field in promoted struct with local var V34 Replacing the field in promoted struct with local var V30 Replacing the field in promoted struct with local var V32 LocalAddressVisitor modified statement: STMT00041 (IL 0x02C... ???) [000201] -A---------- * ASG float [000200] D------N---- +--* LCL_VAR float V34 tmp20 [000177] ------------ \--* ADD float [000173] ------------ +--* LCL_VAR float V30 tmp16 [000176] ------------ \--* LCL_VAR float V32 tmp18 LocalAddressVisitor visiting statement: STMT00016 (IL ???... ???) [000061] -AC--------- * ASG long [000060] *----------- +--* IND long [000059] ------------ | \--* ADDR byref [000058] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 Local V20 should not be enregistered because: was accessed as a local field LocalAddressVisitor visiting statement: STMT00017 (IL 0x037...0x03B) [000066] -A---------- * ASG int [000065] D------N---- +--* LCL_VAR int V12 loc6 [000064] ------------ \--* ADD int [000062] ------------ +--* LCL_VAR int V12 loc6 [000063] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00019 (IL ???... ???) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000217] ------------ \--* ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* FIELD float Real [000203] ------------ | | \--* ADDR byref [000204] ------------ | | \--* LCL_VAR struct(P) V11 loc5 | | \--* float V11.Real (offs=0x00) -> V25 tmp11 | | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000208] ------------ | \--* FIELD float Real [000206] ------------ | \--* ADDR byref [000207] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000216] ------------ \--* MUL float [000212] ------------ +--* FIELD float Imaginary [000210] ------------ | \--* ADDR byref [000211] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000215] ------------ \--* FIELD float Imaginary [000213] ------------ \--* ADDR byref [000214] ------------ \--* LCL_VAR struct(P) V11 loc5 \--* float V11.Real (offs=0x00) -> V25 tmp11 \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 Replacing the field in promoted struct with local var V25 Replacing the field in promoted struct with local var V25 Replacing the field in promoted struct with local var V26 Replacing the field in promoted struct with local var V26 LocalAddressVisitor modified statement: STMT00019 (IL ???... ???) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000217] ------------ \--* ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* LCL_VAR float V25 tmp11 [000208] ------------ | \--* LCL_VAR float V25 tmp11 [000216] ------------ \--* MUL float [000212] ------------ +--* LCL_VAR float V26 tmp12 [000215] ------------ \--* LCL_VAR float V26 tmp12 LocalAddressVisitor visiting statement: STMT00020 (IL 0x046...0x04D) [000076] ------------ * JTRUE void [000075] N--------U-- \--* GE int [000073] ------------ +--* LCL_VAR float V13 loc7 [000074] ------------ \--* CNS_DBL float 4.0000000000000000 LocalAddressVisitor visiting statement: STMT00025 (IL 0x04F...0x056) [000097] ------------ * JTRUE void [000096] ------------ \--* LT int [000094] ------------ +--* LCL_VAR int V12 loc6 [000095] ------------ \--* CNS_INT int 0x3E8 LocalAddressVisitor visiting statement: STMT00022 (IL ???... ???) [000083] --C-G------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG------- this in rcx +--* FIELD ref _drawPixel [000077] ------------ | \--* LCL_VAR ref V00 this [000080] ------------ arg1 +--* LCL_VAR int V08 loc2 [000081] ------------ arg2 +--* LCL_VAR int V06 loc0 [000082] ------------ arg3 \--* LCL_VAR int V12 loc6 LocalAddressVisitor visiting statement: STMT00023 (IL 0x067... ???) [000088] -A---------- * ASG float [000087] D------N---- +--* LCL_VAR float V09 loc3 [000086] ------------ \--* ADD float [000084] ------------ +--* LCL_VAR float V09 loc3 [000085] ------------ \--* LCL_VAR float V05 arg5 LocalAddressVisitor visiting statement: STMT00024 (IL 0x06C...0x06F) [000093] -A---------- * ASG int [000092] D------N---- +--* LCL_VAR int V08 loc2 [000091] ------------ \--* ADD int [000089] ------------ +--* LCL_VAR int V08 loc2 [000090] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00008 (IL 0x070...0x072) [000026] ------------ * JTRUE void [000025] ------------ \--* LT int [000023] ------------ +--* LCL_VAR float V09 loc3 [000024] ------------ \--* LCL_VAR float V02 arg2 LocalAddressVisitor visiting statement: STMT00026 (IL 0x074...0x078) [000102] -A---------- * ASG float [000101] D------N---- +--* LCL_VAR float V07 loc1 [000100] ------------ \--* ADD float [000098] ------------ +--* LCL_VAR float V07 loc1 [000099] ------------ \--* LCL_VAR float V05 arg5 LocalAddressVisitor visiting statement: STMT00027 (IL 0x079...0x07C) [000107] -A---------- * ASG int [000106] D------N---- +--* LCL_VAR int V06 loc0 [000105] ------------ \--* ADD int [000103] ------------ +--* LCL_VAR int V06 loc0 [000104] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00002 (IL 0x07D...0x080) [000009] ------------ * JTRUE void [000008] N--------U-- \--* GE int [000006] ------------ +--* LCL_VAR float V07 loc1 [000007] ------------ \--* LCL_VAR float V04 arg4 LocalAddressVisitor visiting statement: STMT00005 (IL ???... ???) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000012] --C-G------- +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this [000014] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00003 (IL 0x08D...0x08D) [000010] ------------ * RETURN void *************** In fgRetypeImplicitByRefArgs() *************** In fgMorphBlocks() Morphing BB01 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB01, STMT00000 (before) [000002] -A---------- * ASG int [000001] D------N---- +--* LCL_VAR int V06 loc0 [000000] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000002] -A---------- * ASG int In BB01 New Local Constant Assertion: V06 == 0 index=#01, mask=0000000000000001 fgMorphTree BB01, STMT00001 (before) [000005] -A---------- * ASG float [000004] D------N---- +--* LCL_VAR float V07 loc1 [000003] ------------ \--* LCL_VAR float V03 arg3 GenTreeNode creates assertion: [000005] -A---------- * ASG float In BB01 New Local Copy Assertion: V07 == V03 index=#02, mask=0000000000000002 Morphing BB02 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB02, STMT00006 (before) [000019] -A---------- * ASG int [000018] D------N---- +--* LCL_VAR int V08 loc2 [000017] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000019] -A---------- * ASG int In BB02 New Local Constant Assertion: V08 == 0 index=#01, mask=0000000000000001 fgMorphTree BB02, STMT00007 (before) [000022] -A---------- * ASG float [000021] D------N---- +--* LCL_VAR float V09 loc3 [000020] ------------ \--* LCL_VAR float V01 arg1 GenTreeNode creates assertion: [000022] -A---------- * ASG float In BB02 New Local Copy Assertion: V09 == V01 index=#02, mask=0000000000000002 Morphing BB03 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB03, STMT00028 (before) [000111] -A---------- * ASG float [000110] D------N---- +--* LCL_VAR float V23 tmp9 [000029] ------------ \--* LCL_VAR float V09 loc3 GenTreeNode creates assertion: [000111] -A---------- * ASG float In BB03 New Local Copy Assertion: V23 == V09 index=#01, mask=0000000000000001 fgMorphTree BB03, STMT00029 (before) [000115] -A---------- * ASG float [000114] D------N---- +--* LCL_VAR float V24 tmp10 [000030] ------------ \--* LCL_VAR float V07 loc1 GenTreeNode creates assertion: [000115] -A---------- * ASG float In BB03 New Local Copy Assertion: V24 == V07 index=#02, mask=0000000000000002 fgMorphTree BB03, STMT00010 (before) [000035] -A---------- * ASG struct (copy) [000033] D----------- +--* LCL_VAR struct(P) V11 loc5 +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000032] ------------ \--* LCL_VAR struct(P) V10 loc4 \--* float V10.Real (offs=0x00) -> V23 tmp9 \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 fgMorphCopyBlock:block assignment to morph: [000035] -A---------- * ASG struct (copy) [000033] D----+-N---- +--* LCL_VAR struct(P) V11 loc5 +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000032] -----+------ \--* LCL_VAR struct(P) V10 loc4 \--* float V10.Real (offs=0x00) -> V23 tmp9 \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000225] -A---------- * ASG float In BB03 New Local Copy Assertion: V25 == V23 index=#03, mask=0000000000000004 GenTreeNode creates assertion: [000228] -A---------- * ASG float In BB03 New Local Copy Assertion: V26 == V24 index=#04, mask=0000000000000008 fgMorphCopyBlock (after): [000229] -A---+------ * COMMA void [000225] -A---------- +--* ASG float [000223] D------N---- | +--* LCL_VAR float V25 tmp11 [000224] ------------ | \--* LCL_VAR float V23 tmp9 [000228] -A---------- \--* ASG float [000226] D------N---- +--* LCL_VAR float V26 tmp12 [000227] ------------ \--* LCL_VAR float V24 tmp10 fgMorphTree BB03, STMT00010 (after) [000229] -A---+------ * COMMA void [000225] -A---------- +--* ASG float [000223] D------N---- | +--* LCL_VAR float V25 tmp11 [000224] ------------ | \--* LCL_VAR float V23 tmp9 [000228] -A---------- \--* ASG float [000226] D------N---- +--* LCL_VAR float V26 tmp12 [000227] ------------ \--* LCL_VAR float V24 tmp10 fgMorphTree BB03, STMT00011 (before) [000038] -A---------- * ASG int [000037] D------N---- +--* LCL_VAR int V12 loc6 [000036] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000038] -A---------- * ASG int In BB03 New Local Constant Assertion: V12 == 0 index=#05, mask=0000000000000010 fgMorphTree BB03, STMT00012 (before) [000041] -A---------- * ASG float [000040] D------N---- +--* LCL_VAR float V13 loc7 [000039] ------------ \--* CNS_DBL float 0.00000000000000000 GenTreeNode creates assertion: [000041] -A---------- * ASG float In BB03 New Local Constant Assertion: V13 == 0.000000 index=#06, mask=0000000000000020 Morphing BB04 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB04, STMT00030 (before) [000143] IA---------- * ASG struct (init) [000141] D------N---- +--* LCL_VAR struct(P) V15 tmp1 +--* float V15.Real (offs=0x00) -> V27 tmp13 +--* float V15.Imaginary (offs=0x04) -> V28 tmp14 [000142] ------------ \--* CNS_INT int 0 fgMorphInitBlock: using field by field initialization. GenTreeNode creates assertion: [000232] -A---------- * ASG float In BB04 New Local Constant Assertion: V27 == 0.000000 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000235] -A---------- * ASG float In BB04 New Local Constant Assertion: V28 == 0.000000 index=#02, mask=0000000000000002 fgMorphInitBlock (after): [000236] -A---+------ * COMMA void [000232] -A---------- +--* ASG float [000230] D------N---- | +--* LCL_VAR float V27 tmp13 [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 [000235] -A---------- \--* ASG float [000233] D------N---- +--* LCL_VAR float V28 tmp14 [000234] ------------ \--* CNS_DBL float 0.00000000000000000 fgMorphTree BB04, STMT00030 (after) [000236] -A---+------ * COMMA void [000232] -A---------- +--* ASG float [000230] D------N---- | +--* LCL_VAR float V27 tmp13 [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 [000235] -A---------- \--* ASG float [000233] D------N---- +--* LCL_VAR float V28 tmp14 [000234] ------------ \--* CNS_DBL float 0.00000000000000000 fgMorphTree BB04, STMT00034 (before) [000160] -A---------- * ASG float [000159] D------N---- +--* LCL_VAR float V16 tmp2 [000131] ------------ \--* SUB float [000123] ------------ +--* MUL float [000119] ------------ | +--* LCL_VAR float V25 tmp11 [000122] ------------ | \--* LCL_VAR float V25 tmp11 [000130] ------------ \--* MUL float [000126] ------------ +--* LCL_VAR float V26 tmp12 [000129] ------------ \--* LCL_VAR float V26 tmp12 fgMorphTree BB04, STMT00035 (before) [000162] -A---------- * ASG float [000161] D------N---- +--* LCL_VAR float V17 tmp3 [000140] ------------ \--* MUL float [000136] ------------ +--* MUL float [000132] ------------ | +--* CNS_DBL float 2.0000000000000000 [000135] ------------ | \--* LCL_VAR float V25 tmp11 [000139] ------------ \--* LCL_VAR float V26 tmp12 fgMorphTree BB04, STMT00035 (after) [000162] -A---+------ * ASG float [000161] D----+-N---- +--* LCL_VAR float V17 tmp3 [000140] -----+------ \--* MUL float [000136] -----+------ +--* MUL float [000135] -----+------ | +--* LCL_VAR float V25 tmp11 [000132] -----+------ | \--* CNS_DBL float 2.0000000000000000 [000139] -----+------ \--* LCL_VAR float V26 tmp12 fgMorphTree BB04, STMT00032 (before) [000153] -A---------- * ASG float [000152] D------N---- +--* LCL_VAR float V27 tmp13 [000151] ------------ \--* LCL_VAR float V16 tmp2 The assignment [000153] using V27 removes: Constant Assertion: V27 == 0.000000 GenTreeNode creates assertion: [000153] -A---------- * ASG float In BB04 New Local Copy Assertion: V27 == V16 index=#02, mask=0000000000000002 fgMorphTree BB04, STMT00033 (before) [000158] -A---------- * ASG float [000157] D------N---- +--* LCL_VAR float V28 tmp14 [000156] ------------ \--* LCL_VAR float V17 tmp3 The assignment [000158] using V28 removes: Constant Assertion: V28 == 0.000000 GenTreeNode creates assertion: [000158] -A---------- * ASG float In BB04 New Local Copy Assertion: V28 == V17 index=#02, mask=0000000000000002 fgMorphTree BB04, STMT00014 (before) [000049] -AC--------- * ASG long [000048] *----------- +--* IND long [000047] ------------ | \--* ADDR byref [000046] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 Local V11 should not be enregistered because: was accessed as a local field fgMorphTree BB04, STMT00014 (after) [000049] -A---+------ * ASG long [000046] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000147] -----+------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 fgMorphTree BB04, STMT00038 (before) [000187] -A---------- * ASG struct (copy) [000185] D----------- +--* LCL_VAR struct(P) V18 tmp4 +--* float V18.Real (offs=0x00) -> V29 tmp15 +--* float V18.Imaginary (offs=0x04) -> V30 tmp16 [000056] n----------- \--* OBJ struct [000055] ------------ \--* ADDR byref [000050] ------------ \--* LCL_VAR struct(P) V11 loc5 \--* float V11.Real (offs=0x00) -> V25 tmp11 \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 fgMorphCopyBlock:block assignment to morph: [000187] -A---------- * ASG struct (copy) [000185] D----+-N---- +--* LCL_VAR struct(P) V18 tmp4 +--* float V18.Real (offs=0x00) -> V29 tmp15 +--* float V18.Imaginary (offs=0x04) -> V30 tmp16 [000056] n----+------ \--* OBJ struct [000055] -----+------ \--* ADDR byref [000050] -----+-N---- \--* LCL_VAR struct(P) V11 loc5 \--* float V11.Real (offs=0x00) -> V25 tmp11 \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000239] -A---------- * ASG float In BB04 New Local Copy Assertion: V29 == V25 index=#03, mask=0000000000000004 GenTreeNode creates assertion: [000242] -A---------- * ASG float In BB04 New Local Copy Assertion: V30 == V26 index=#04, mask=0000000000000008 fgMorphCopyBlock (after): [000243] -A---+------ * COMMA void [000239] -A---------- +--* ASG float [000237] D------N---- | +--* LCL_VAR float V29 tmp15 [000238] -------N---- | \--* LCL_VAR float V25 tmp11 [000242] -A---------- \--* ASG float [000240] D------N---- +--* LCL_VAR float V30 tmp16 [000241] -------N---- \--* LCL_VAR float V26 tmp12 fgMorphTree BB04, STMT00038 (after) [000243] -A---+------ * COMMA void [000239] -A---------- +--* ASG float [000237] D------N---- | +--* LCL_VAR float V29 tmp15 [000238] -------N---- | \--* LCL_VAR float V25 tmp11 [000242] -A---------- \--* ASG float [000240] D------N---- +--* LCL_VAR float V30 tmp16 [000241] -------N---- \--* LCL_VAR float V26 tmp12 fgMorphTree BB04, STMT00039 (before) [000190] -A---------- * ASG struct (copy) [000188] D----------- +--* LCL_VAR struct(P) V19 tmp5 +--* float V19.Real (offs=0x00) -> V31 tmp17 +--* float V19.Imaginary (offs=0x04) -> V32 tmp18 [000054] n----------- \--* OBJ struct [000053] ------------ \--* ADDR byref [000051] ------------ \--* LCL_VAR struct(P) V10 loc4 \--* float V10.Real (offs=0x00) -> V23 tmp9 \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 fgMorphCopyBlock:block assignment to morph: [000190] -A---------- * ASG struct (copy) [000188] D----+-N---- +--* LCL_VAR struct(P) V19 tmp5 +--* float V19.Real (offs=0x00) -> V31 tmp17 +--* float V19.Imaginary (offs=0x04) -> V32 tmp18 [000054] n----+------ \--* OBJ struct [000053] -----+------ \--* ADDR byref [000051] -----+-N---- \--* LCL_VAR struct(P) V10 loc4 \--* float V10.Real (offs=0x00) -> V23 tmp9 \--* float V10.Imaginary (offs=0x04) -> V24 tmp10 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000246] -A---------- * ASG float In BB04 New Local Copy Assertion: V31 == V23 index=#05, mask=0000000000000010 GenTreeNode creates assertion: [000249] -A---------- * ASG float In BB04 New Local Copy Assertion: V32 == V24 index=#06, mask=0000000000000020 fgMorphCopyBlock (after): [000250] -A---+------ * COMMA void [000246] -A---------- +--* ASG float [000244] D------N---- | +--* LCL_VAR float V31 tmp17 [000245] -------N---- | \--* LCL_VAR float V23 tmp9 [000249] -A---------- \--* ASG float [000247] D------N---- +--* LCL_VAR float V32 tmp18 [000248] -------N---- \--* LCL_VAR float V24 tmp10 fgMorphTree BB04, STMT00039 (after) [000250] -A---+------ * COMMA void [000246] -A---------- +--* ASG float [000244] D------N---- | +--* LCL_VAR float V31 tmp17 [000245] -------N---- | \--* LCL_VAR float V23 tmp9 [000249] -A---------- \--* ASG float [000247] D------N---- +--* LCL_VAR float V32 tmp18 [000248] -------N---- \--* LCL_VAR float V24 tmp10 fgMorphTree BB04, STMT00036 (before) [000180] IA---------- * ASG struct (init) [000178] D------N---- +--* LCL_VAR struct(P) V20 tmp6 +--* float V20.Real (offs=0x00) -> V33 tmp19 +--* float V20.Imaginary (offs=0x04) -> V34 tmp20 [000179] ------------ \--* CNS_INT int 0 fgMorphInitBlock: using field by field initialization. GenTreeNode creates assertion: [000253] -A---------- * ASG float In BB04 New Local Constant Assertion: V33 == 0.000000 index=#07, mask=0000000000000040 GenTreeNode creates assertion: [000256] -A---------- * ASG float In BB04 New Local Constant Assertion: V34 == 0.000000 index=#08, mask=0000000000000080 fgMorphInitBlock (after): [000257] -A---+------ * COMMA void [000253] -A---------- +--* ASG float [000251] D------N---- | +--* LCL_VAR float V33 tmp19 [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 [000256] -A---------- \--* ASG float [000254] D------N---- +--* LCL_VAR float V34 tmp20 [000255] ------------ \--* CNS_DBL float 0.00000000000000000 fgMorphTree BB04, STMT00036 (after) [000257] -A---+------ * COMMA void [000253] -A---------- +--* ASG float [000251] D------N---- | +--* LCL_VAR float V33 tmp19 [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 [000256] -A---------- \--* ASG float [000254] D------N---- +--* LCL_VAR float V34 tmp20 [000255] ------------ \--* CNS_DBL float 0.00000000000000000 fgMorphTree BB04, STMT00040 (before) [000196] -A---------- * ASG float [000195] D------N---- +--* LCL_VAR float V33 tmp19 [000170] ------------ \--* ADD float [000166] ------------ +--* LCL_VAR float V29 tmp15 [000169] ------------ \--* LCL_VAR float V31 tmp17 Assertion prop in BB04: Copy Assertion: V29 == V25 index=#03, mask=0000000000000004 [000166] ------------ * LCL_VAR float V25 tmp11 Assertion prop in BB04: Copy Assertion: V31 == V23 index=#05, mask=0000000000000010 [000169] ------------ * LCL_VAR float V23 tmp9 The assignment [000196] using V33 removes: Constant Assertion: V33 == 0.000000 fgMorphTree BB04, STMT00040 (after) [000196] -A---+------ * ASG float [000195] D----+-N---- +--* LCL_VAR float V33 tmp19 [000170] -----+------ \--* ADD float [000166] -----+------ +--* LCL_VAR float V25 tmp11 [000169] -----+------ \--* LCL_VAR float V23 tmp9 fgMorphTree BB04, STMT00041 (before) [000201] -A---------- * ASG float [000200] D------N---- +--* LCL_VAR float V34 tmp20 [000177] ------------ \--* ADD float [000173] ------------ +--* LCL_VAR float V30 tmp16 [000176] ------------ \--* LCL_VAR float V32 tmp18 Assertion prop in BB04: Copy Assertion: V30 == V26 index=#04, mask=0000000000000008 [000173] ------------ * LCL_VAR float V26 tmp12 Assertion prop in BB04: Copy Assertion: V32 == V24 index=#06, mask=0000000000000020 [000176] ------------ * LCL_VAR float V24 tmp10 The assignment [000201] using V34 removes: Constant Assertion: V34 == 0.000000 fgMorphTree BB04, STMT00041 (after) [000201] -A---+------ * ASG float [000200] D----+-N---- +--* LCL_VAR float V34 tmp20 [000177] -----+------ \--* ADD float [000173] -----+------ +--* LCL_VAR float V26 tmp12 [000176] -----+------ \--* LCL_VAR float V24 tmp10 fgMorphTree BB04, STMT00016 (before) [000061] -AC--------- * ASG long [000060] *----------- +--* IND long [000059] ------------ | \--* ADDR byref [000058] ------------ | \--* LCL_VAR struct(P) V11 loc5 | \--* float V11.Real (offs=0x00) -> V25 tmp11 | \--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 Local V11 should not be enregistered because: was accessed as a local field The assignment [000061] using V29 removes: Copy Assertion: V29 == V25 The assignment [000061] using V30 removes: Copy Assertion: V30 == V26 fgMorphTree BB04, STMT00016 (after) [000061] -A---+------ * ASG long [000058] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000184] -----+------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 fgMorphTree BB04, STMT00017 (before) [000066] -A---------- * ASG int [000065] D------N---- +--* LCL_VAR int V12 loc6 [000064] ------------ \--* ADD int [000062] ------------ +--* LCL_VAR int V12 loc6 [000063] ------------ \--* CNS_INT int 1 fgMorphTree BB04, STMT00019 (before) [000072] -AC--------- * ASG float [000071] D------N---- +--* LCL_VAR float V13 loc7 [000217] ------------ \--* ADD float [000209] ------------ +--* MUL float [000205] ------------ | +--* LCL_VAR float V25 tmp11 [000208] ------------ | \--* LCL_VAR float V25 tmp11 [000216] ------------ \--* MUL float [000212] ------------ +--* LCL_VAR float V26 tmp12 [000215] ------------ \--* LCL_VAR float V26 tmp12 fgMorphTree BB04, STMT00020 (before) [000076] ------------ * JTRUE void [000075] N--------U-- \--* GE int [000073] ------------ +--* LCL_VAR float V13 loc7 [000074] ------------ \--* CNS_DBL float 4.0000000000000000 Morphing BB05 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB05, STMT00025 (before) [000097] ------------ * JTRUE void [000096] ------------ \--* LT int [000094] ------------ +--* LCL_VAR int V12 loc6 [000095] ------------ \--* CNS_INT int 0x3E8 Morphing BB06 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB06, STMT00022 (before) [000083] --C-G------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG------- this in rcx +--* FIELD ref _drawPixel [000077] ------------ | \--* LCL_VAR ref V00 this [000080] ------------ arg1 +--* LCL_VAR int V08 loc2 [000081] ------------ arg2 +--* LCL_VAR int V06 loc0 [000082] ------------ arg3 \--* LCL_VAR int V12 loc6 Initializing arg info for 83.CALL: ArgTable for 83.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 219.FIELD ref, 1 reg: rcx, align=1] fgArgTabEntry[arg 1 80.LCL_VAR int, 1 reg: rdx, align=1] fgArgTabEntry[arg 2 81.LCL_VAR int, 1 reg: r8, align=1] fgArgTabEntry[arg 3 82.LCL_VAR int, 1 reg: r9, align=1] Morphing args for 83.CALL: Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000219] ---XG------- * IND ref [000259] -----+------ \--* ADD byref [000077] -----+------ +--* LCL_VAR ref V00 this [000258] -----+------ \--* CNS_INT long 16 field offset Fseq[_drawPixel] GenTreeNode creates assertion: [000219] ---XG------- * IND ref In BB06 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000219] ---XG+------ * IND ref [000259] -----+------ \--* ADD byref [000077] -----+------ +--* LCL_VAR ref V00 this [000258] -----+------ \--* CNS_INT long 16 field offset Fseq[_drawPixel] Replaced with placeholder node: [000260] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000080] -----+------ * LCL_VAR int V08 loc2 Replaced with placeholder node: [000261] ----------L- * ARGPLACE int Deferred argument ('r8'): [000081] -----+------ * LCL_VAR int V06 loc0 Replaced with placeholder node: [000262] ----------L- * ARGPLACE int Deferred argument ('r9'): [000082] -----+------ * LCL_VAR int V12 loc6 Replaced with placeholder node: [000263] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r8 r9 ArgTable for 83.CALL after fgMorphArgs: fgArgTabEntry[arg 0 219.IND ref, 1 reg: rcx, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 80.LCL_VAR int, 1 reg: rdx, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 81.LCL_VAR int, 1 reg: r8, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 3 82.LCL_VAR int, 1 reg: r9, align=1, lateArgInx=3, processed] fgMorphTree BB06, STMT00022 (after) [000083] --CXG+------ * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG+------ this in rcx +--* IND ref [000259] -----+------ | \--* ADD byref [000077] -----+------ | +--* LCL_VAR ref V00 this [000258] -----+------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] [000080] -----+------ arg1 in rdx +--* LCL_VAR int V08 loc2 [000081] -----+------ arg2 in r8 +--* LCL_VAR int V06 loc0 [000082] -----+------ arg3 in r9 \--* LCL_VAR int V12 loc6 fgMorphTree BB06, STMT00023 (before) [000088] -A---------- * ASG float [000087] D------N---- +--* LCL_VAR float V09 loc3 [000086] ------------ \--* ADD float [000084] ------------ +--* LCL_VAR float V09 loc3 [000085] ------------ \--* LCL_VAR float V05 arg5 fgMorphTree BB06, STMT00024 (before) [000093] -A---------- * ASG int [000092] D------N---- +--* LCL_VAR int V08 loc2 [000091] ------------ \--* ADD int [000089] ------------ +--* LCL_VAR int V08 loc2 [000090] ------------ \--* CNS_INT int 1 Morphing BB07 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB07, STMT00008 (before) [000026] ------------ * JTRUE void [000025] ------------ \--* LT int [000023] ------------ +--* LCL_VAR float V09 loc3 [000024] ------------ \--* LCL_VAR float V02 arg2 Morphing BB08 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB08, STMT00026 (before) [000102] -A---------- * ASG float [000101] D------N---- +--* LCL_VAR float V07 loc1 [000100] ------------ \--* ADD float [000098] ------------ +--* LCL_VAR float V07 loc1 [000099] ------------ \--* LCL_VAR float V05 arg5 fgMorphTree BB08, STMT00027 (before) [000107] -A---------- * ASG int [000106] D------N---- +--* LCL_VAR int V06 loc0 [000105] ------------ \--* ADD int [000103] ------------ +--* LCL_VAR int V06 loc0 [000104] ------------ \--* CNS_INT int 1 Morphing BB09 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB09, STMT00002 (before) [000009] ------------ * JTRUE void [000008] N--------U-- \--* GE int [000006] ------------ +--* LCL_VAR float V07 loc1 [000007] ------------ \--* LCL_VAR float V04 arg4 Morphing BB10 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB10, STMT00005 (before) [000016] --C--------- * JTRUE void [000015] --C--------- \--* EQ int [000012] --C-G------- +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this [000014] ------------ \--* CNS_INT int 0 Initializing arg info for 12.CALL: ArgTable for 12.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 11.LCL_VAR ref, 1 reg: rcx, align=1] Morphing args for 12.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000011] -----+------ * LCL_VAR ref V00 this Replaced with placeholder node: [000264] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 12.CALL after fgMorphArgs: fgArgTabEntry[arg 0 11.LCL_VAR ref, 1 reg: rcx, align=1, lateArgInx=0, processed] fgMorphTree BB10, STMT00005 (after) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000012] --CXG+------ +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] -----+------ this in rcx | \--* LCL_VAR ref V00 this [000014] -----+------ \--* CNS_INT int 0 Morphing BB11 of 'Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this' fgMorphTree BB11, STMT00003 (before) [000010] ------------ * RETURN void Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i BB02 [0001] 1 1 [006..00C)-> BB07 (always) i bwd BB03 [0002] 1 1 [00C..023) i bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) i bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 1 [058..070) i gcsafe bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) i bwd BB08 [0007] 1 1 [074..07D) i bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) i bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 1 [08D..08E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! New BlockSet epoch 2, # of blocks (including unused BB00): 12, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i BB02 [0001] 1 1 [006..00C)-> BB07 (always) i bwd BB03 [0002] 1 1 [00C..023) i bwd BB04 [0003] 2 1 [023..04F)-> BB06 ( cond ) i bwd BB05 [0004] 1 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 1 [058..070) i gcsafe bwd BB07 [0006] 2 1 [070..074)-> BB03 ( cond ) i bwd BB08 [0007] 1 1 [074..07D) i bwd BB09 [0008] 2 1 [07D..082)-> BB11 ( cond ) i bwd BB10 [0009] 1 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 1 [08D..08E) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB07 (always) i label target bwd BB03 [0002] 1 BB07 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..070) i label target gcsafe bwd BB07 [0006] 2 BB02,BB06 1 [070..074)-> BB03 ( cond ) i label target bwd BB08 [0007] 1 BB07 1 [074..07D) i bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB07 (always) i label target bwd BB03 [0002] 1 BB07 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..070) i label target gcsafe bwd BB07 [0006] 2 BB02,BB06 1 [070..074)-> BB03 ( cond ) i label target bwd BB08 [0007] 1 BB07 1 [074..07D) i bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB07 (always) i label target bwd BB03 [0002] 1 BB07 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..070) i label target gcsafe bwd BB07 [0006] 2 BB02,BB06 1 [070..074)-> BB03 ( cond ) i label target bwd BB08 [0007] 1 BB07 1 [074..07D) i bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist Duplication of loop condition [000025] is performed, because the cost of duplication (9) is less or equal than 32, loopIterations = 8.000, countOfHelpers = 0, validProfileWeights = false Duplicating loop condition in BB02 for loop (BB03 - BB07) Estimated code size expansion is 9 STMT00042 (IL 0x070... ???) [000268] ------------ * JTRUE void ( 7, 9) [000265] N------N---- \--* GE int ( 3, 4) [000266] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000267] ------------ \--* LCL_VAR float V02 arg2 fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB08 ( cond ) i label target bwd BB03 [0002] 2 BB02,BB07 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..070) i label target gcsafe bwd BB07 [0006] 1 BB06 1 [070..074)-> BB03 ( cond ) i label target bwd BB08 [0007] 2 BB02,BB07 1 [074..07D) i label target bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB06 and BB07: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB08 ( cond ) i label target bwd BB03 [0002] 2 BB02,BB06 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB08 [0007] 2 BB02,BB06 1 [074..07D) i label target bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB08 ( cond ) i label target bwd BB03 [0002] 2 BB02,BB06 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB08 [0007] 2 BB02,BB06 1 [074..07D) i label target bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB08 ( cond ) i label target bwd BB03 [0002] 2 BB02,BB06 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB08 [0007] 2 BB02,BB06 1 [074..07D) i label target bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB09 (always) i label target BB02 [0001] 1 BB10 1 [006..00C)-> BB08 ( cond ) i label target bwd BB03 [0002] 2 BB02,BB06 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB08 [0007] 2 BB02,BB06 1 [074..07D) i label target bwd BB09 [0008] 2 BB01,BB08 1 [07D..082)-> BB11 ( cond ) i label target bwd BB10 [0009] 1 BB09 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB11 [0010] 2 BB09,BB10 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB08 to BB07 Renumber BB09 to BB08 Renumber BB10 to BB09 Renumber BB11 to BB10 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 1 [006..00C)-> BB07 ( cond ) i label target bwd BB03 [0002] 2 BB02,BB06 1 [00C..023) i label target bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 1 [074..07D) i label target bwd BB08 [0008] 2 BB01,BB07 1 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 11, bitset array size: 1 (short) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB03 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB04 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB05 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 1 [006..00C)-> BB07 ( cond ) i Loop label target gcsafe bwd BB03 [0002] 2 BB02,BB06 1 [00C..023) i Loop label target gcsafe bwd BB04 [0003] 2 BB03,BB05 1 [023..04F)-> BB06 ( cond ) i Loop label target bwd BB05 [0004] 1 BB04 1 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 1 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 1 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 1 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB08: BB08 BB01 BB09: BB09 BB08 BB01 BB02: BB02 BB09 BB08 BB01 BB03: BB03 BB02 BB09 BB08 BB01 BB04: BB04 BB03 BB02 BB09 BB08 BB01 BB05: BB05 BB04 BB03 BB02 BB09 BB08 BB01 BB06: BB06 BB04 BB03 BB02 BB09 BB08 BB01 BB07: BB07 BB02 BB09 BB08 BB01 BB10: BB10 BB08 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB08 BB02 : BB07 BB03 BB03 : BB04 BB04 : BB06 BB05 BB08 : BB10 BB09 BB09 : BB02 After numbering the dominator tree: BB01: pre=01, post=10 BB02: pre=05, post=07 BB03: pre=07, post=06 BB04: pre=08, post=05 BB05: pre=10, post=04 BB06: pre=09, post=03 BB07: pre=06, post=02 BB08: pre=02, post=09 BB09: pre=04, post=08 BB10: pre=03, post=01 *************** In optOptimizeLoops() After optSetBlockWeights: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 0.50 [006..00C)-> BB07 ( cond ) i Loop label target gcsafe bwd BB03 [0002] 2 BB02,BB06 0.50 [00C..023) i Loop label target gcsafe bwd BB04 [0003] 2 BB03,BB05 0.50 [023..04F)-> BB06 ( cond ) i Loop label target bwd BB05 [0004] 1 BB04 0.50 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 0.50 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 0.50 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 1 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 0.50 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In optFindNaturalLoops() Recorded loop L00, from BB02 to BB09 (Head=BB01, Entry=BB08, ExitCnt=2) Recorded loop L01, from BB03 to BB06 (Head=BB02, Entry=BB03, ExitCnt=1 at BB06) Recorded loop L02, from BB04 to BB05 (Head=BB03, Entry=BB04, ExitCnt=2) Final natural loop table: L00, from BB02 to BB09 (Head=BB01, Entry=BB08, ExitCnt=2) L01, from BB03 to BB06 (Head=BB02, Entry=BB03, ExitCnt=1 at BB06, parent loop = L00) L02, from BB04 to BB05 (Head=BB03, Entry=BB04, ExitCnt=2, parent loop = L01) Marking loop L01 BB02(wt=2 ) BB03(wt=2 ) BB04(wt=2 ) BB05(wt=2 ) BB06(wt=2 ) BB07(wt=2 ) BB08(wt=8 ) BB09(wt=4 ) Marking loop L02 BB03(wt=16 ) BB04(wt=16 ) BB05(wt=8 ) BB06(wt=16 ) Marking loop L03 BB04(wt=128 ) BB05(wt=64 ) Found a total of 3 loops. After loop weight marking: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** In optCloneLoops() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) [000002] -A---+------ * ASG int [000001] D----+-N---- +--* LCL_VAR int V06 loc0 [000000] -----+------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) [000005] -A---+------ * ASG float [000004] D----+-N---- +--* LCL_VAR float V07 loc1 [000003] -----+------ \--* LCL_VAR float V03 arg3 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) [000019] -A---+------ * ASG int [000018] D----+-N---- +--* LCL_VAR int V08 loc2 [000017] -----+------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) [000022] -A---+------ * ASG float [000021] D----+-N---- +--* LCL_VAR float V09 loc3 [000020] -----+------ \--* LCL_VAR float V01 arg1 ***** BB02 STMT00042 (IL 0x070... ???) [000268] ------------ * JTRUE void ( 7, 9) [000265] N------N---- \--* GE int ( 3, 4) [000266] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000267] ------------ \--* LCL_VAR float V02 arg2 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00028 (IL 0x00C... ???) [000111] -A---+------ * ASG float [000110] D----+-N---- +--* LCL_VAR float V23 tmp9 [000029] -----+------ \--* LCL_VAR float V09 loc3 ***** BB03 STMT00029 (IL 0x00C... ???) [000115] -A---+------ * ASG float [000114] D----+-N---- +--* LCL_VAR float V24 tmp10 [000030] -----+------ \--* LCL_VAR float V07 loc1 ***** BB03 STMT00010 (IL 0x015... ???) [000229] -A---+------ * COMMA void [000225] -A---------- +--* ASG float [000223] D------N---- | +--* LCL_VAR float V25 tmp11 [000224] ------------ | \--* LCL_VAR float V23 tmp9 [000228] -A---------- \--* ASG float [000226] D------N---- +--* LCL_VAR float V26 tmp12 [000227] ------------ \--* LCL_VAR float V24 tmp10 ***** BB03 STMT00011 (IL 0x019...0x01A) [000038] -A---+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V12 loc6 [000036] -----+------ \--* CNS_INT int 0 ***** BB03 STMT00012 (IL 0x01C...0x021) [000041] -A---+------ * ASG float [000040] D----+-N---- +--* LCL_VAR float V13 loc7 [000039] -----+------ \--* CNS_DBL float 0.00000000000000000 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00030 (IL 0x023... ???) [000236] -A---+------ * COMMA void [000232] -A---------- +--* ASG float [000230] D------N---- | +--* LCL_VAR float V27 tmp13 [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 [000235] -A---------- \--* ASG float [000233] D------N---- +--* LCL_VAR float V28 tmp14 [000234] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00034 (IL 0x023... ???) [000160] -A---+------ * ASG float [000159] D----+-N---- +--* LCL_VAR float V16 tmp2 [000131] -----+------ \--* SUB float [000123] -----+------ +--* MUL float [000119] -----+------ | +--* LCL_VAR float V25 tmp11 [000122] -----+------ | \--* LCL_VAR float V25 tmp11 [000130] -----+------ \--* MUL float [000126] -----+------ +--* LCL_VAR float V26 tmp12 [000129] -----+------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00035 (IL 0x023... ???) [000162] -A---+------ * ASG float [000161] D----+-N---- +--* LCL_VAR float V17 tmp3 [000140] -----+------ \--* MUL float [000136] -----+------ +--* MUL float [000135] -----+------ | +--* LCL_VAR float V25 tmp11 [000132] -----+------ | \--* CNS_DBL float 2.0000000000000000 [000139] -----+------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00032 (IL 0x023... ???) [000153] -A---+------ * ASG float [000152] D----+-N---- +--* LCL_VAR float V27 tmp13 [000151] -----+------ \--* LCL_VAR float V16 tmp2 ***** BB04 STMT00033 (IL 0x023... ???) [000158] -A---+------ * ASG float [000157] D----+-N---- +--* LCL_VAR float V28 tmp14 [000156] -----+------ \--* LCL_VAR float V17 tmp3 ***** BB04 STMT00014 (IL ???... ???) [000049] -A---+------ * ASG long [000046] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000147] -----+------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 ***** BB04 STMT00038 (IL 0x02C... ???) [000243] -A---+------ * COMMA void [000239] -A---------- +--* ASG float [000237] D------N---- | +--* LCL_VAR float V29 tmp15 [000238] -------N---- | \--* LCL_VAR float V25 tmp11 [000242] -A---------- \--* ASG float [000240] D------N---- +--* LCL_VAR float V30 tmp16 [000241] -------N---- \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00039 (IL 0x02C... ???) [000250] -A---+------ * COMMA void [000246] -A---------- +--* ASG float [000244] D------N---- | +--* LCL_VAR float V31 tmp17 [000245] -------N---- | \--* LCL_VAR float V23 tmp9 [000249] -A---------- \--* ASG float [000247] D------N---- +--* LCL_VAR float V32 tmp18 [000248] -------N---- \--* LCL_VAR float V24 tmp10 ***** BB04 STMT00036 (IL 0x02C... ???) [000257] -A---+------ * COMMA void [000253] -A---------- +--* ASG float [000251] D------N---- | +--* LCL_VAR float V33 tmp19 [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 [000256] -A---------- \--* ASG float [000254] D------N---- +--* LCL_VAR float V34 tmp20 [000255] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00040 (IL 0x02C... ???) [000196] -A---+------ * ASG float [000195] D----+-N---- +--* LCL_VAR float V33 tmp19 [000170] -----+------ \--* ADD float [000166] -----+------ +--* LCL_VAR float V25 tmp11 [000169] -----+------ \--* LCL_VAR float V23 tmp9 ***** BB04 STMT00041 (IL 0x02C... ???) [000201] -A---+------ * ASG float [000200] D----+-N---- +--* LCL_VAR float V34 tmp20 [000177] -----+------ \--* ADD float [000173] -----+------ +--* LCL_VAR float V26 tmp12 [000176] -----+------ \--* LCL_VAR float V24 tmp10 ***** BB04 STMT00016 (IL ???... ???) [000061] -A---+------ * ASG long [000058] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000184] -----+------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 ***** BB04 STMT00017 (IL 0x037...0x03B) [000066] -A---+------ * ASG int [000065] D----+-N---- +--* LCL_VAR int V12 loc6 [000064] -----+------ \--* ADD int [000062] -----+------ +--* LCL_VAR int V12 loc6 [000063] -----+------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) [000072] -A---+------ * ASG float [000071] D----+-N---- +--* LCL_VAR float V13 loc7 [000217] -----+------ \--* ADD float [000209] -----+------ +--* MUL float [000205] -----+------ | +--* LCL_VAR float V25 tmp11 [000208] -----+------ | \--* LCL_VAR float V25 tmp11 [000216] -----+------ \--* MUL float [000212] -----+------ +--* LCL_VAR float V26 tmp12 [000215] -----+------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00020 (IL 0x046...0x04D) [000076] -----+------ * JTRUE void [000075] N----+-N-U-- \--* GE int [000073] -----+------ +--* LCL_VAR float V13 loc7 [000074] -----+------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) [000097] -----+------ * JTRUE void [000096] J----+-N---- \--* LT int [000094] -----+------ +--* LCL_VAR int V12 loc6 [000095] -----+------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) [000083] --CXG+------ * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG+------ this in rcx +--* IND ref [000259] -----+------ | \--* ADD byref [000077] -----+------ | +--* LCL_VAR ref V00 this [000258] -----+------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] [000080] -----+------ arg1 in rdx +--* LCL_VAR int V08 loc2 [000081] -----+------ arg2 in r8 +--* LCL_VAR int V06 loc0 [000082] -----+------ arg3 in r9 \--* LCL_VAR int V12 loc6 ***** BB06 STMT00023 (IL 0x067... ???) [000088] -A---+------ * ASG float [000087] D----+-N---- +--* LCL_VAR float V09 loc3 [000086] -----+------ \--* ADD float [000084] -----+------ +--* LCL_VAR float V09 loc3 [000085] -----+------ \--* LCL_VAR float V05 arg5 ***** BB06 STMT00024 (IL 0x06C...0x06F) [000093] -A---+------ * ASG int [000092] D----+-N---- +--* LCL_VAR int V08 loc2 [000091] -----+------ \--* ADD int [000089] -----+------ +--* LCL_VAR int V08 loc2 [000090] -----+------ \--* CNS_INT int 1 ***** BB06 STMT00008 (IL 0x070...0x072) [000026] -----+------ * JTRUE void ( 7, 9) [000025] J------N---- \--* LT int ( 3, 4) [000023] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000024] ------------ \--* LCL_VAR float V02 arg2 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) [000102] -A---+------ * ASG float [000101] D----+-N---- +--* LCL_VAR float V07 loc1 [000100] -----+------ \--* ADD float [000098] -----+------ +--* LCL_VAR float V07 loc1 [000099] -----+------ \--* LCL_VAR float V05 arg5 ***** BB07 STMT00027 (IL 0x079...0x07C) [000107] -A---+------ * ASG int [000106] D----+-N---- +--* LCL_VAR int V06 loc0 [000105] -----+------ \--* ADD int [000103] -----+------ +--* LCL_VAR int V06 loc0 [000104] -----+------ \--* CNS_INT int 1 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00002 (IL 0x07D...0x080) [000009] -----+------ * JTRUE void [000008] N----+-N-U-- \--* GE int [000006] -----+------ +--* LCL_VAR float V07 loc1 [000007] -----+------ \--* LCL_VAR float V04 arg4 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000012] --CXG+------ +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] -----+------ this in rcx | \--* LCL_VAR ref V00 this [000014] -----+------ \--* CNS_INT int 0 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) [000010] -----+------ * RETURN void ------------------------------------------------------------------------------------------------------------------- Considering loop 0 to clone for optimizations. > No iter flag on loop 0. ------------------------------------------------------------ Considering loop 1 to clone for optimizations. > No iter flag on loop 1. ------------------------------------------------------------ Considering loop 2 to clone for optimizations. > No iter flag on loop 2. ------------------------------------------------------------ After loop cloning: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) [000002] -A---+------ * ASG int [000001] D----+-N---- +--* LCL_VAR int V06 loc0 [000000] -----+------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) [000005] -A---+------ * ASG float [000004] D----+-N---- +--* LCL_VAR float V07 loc1 [000003] -----+------ \--* LCL_VAR float V03 arg3 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) [000019] -A---+------ * ASG int [000018] D----+-N---- +--* LCL_VAR int V08 loc2 [000017] -----+------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) [000022] -A---+------ * ASG float [000021] D----+-N---- +--* LCL_VAR float V09 loc3 [000020] -----+------ \--* LCL_VAR float V01 arg1 ***** BB02 STMT00042 (IL 0x070... ???) [000268] ------------ * JTRUE void ( 7, 9) [000265] N------N---- \--* GE int ( 3, 4) [000266] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000267] ------------ \--* LCL_VAR float V02 arg2 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00028 (IL 0x00C... ???) [000111] -A---+------ * ASG float [000110] D----+-N---- +--* LCL_VAR float V23 tmp9 [000029] -----+------ \--* LCL_VAR float V09 loc3 ***** BB03 STMT00029 (IL 0x00C... ???) [000115] -A---+------ * ASG float [000114] D----+-N---- +--* LCL_VAR float V24 tmp10 [000030] -----+------ \--* LCL_VAR float V07 loc1 ***** BB03 STMT00010 (IL 0x015... ???) [000229] -A---+------ * COMMA void [000225] -A---------- +--* ASG float [000223] D------N---- | +--* LCL_VAR float V25 tmp11 [000224] ------------ | \--* LCL_VAR float V23 tmp9 [000228] -A---------- \--* ASG float [000226] D------N---- +--* LCL_VAR float V26 tmp12 [000227] ------------ \--* LCL_VAR float V24 tmp10 ***** BB03 STMT00011 (IL 0x019...0x01A) [000038] -A---+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V12 loc6 [000036] -----+------ \--* CNS_INT int 0 ***** BB03 STMT00012 (IL 0x01C...0x021) [000041] -A---+------ * ASG float [000040] D----+-N---- +--* LCL_VAR float V13 loc7 [000039] -----+------ \--* CNS_DBL float 0.00000000000000000 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00030 (IL 0x023... ???) [000236] -A---+------ * COMMA void [000232] -A---------- +--* ASG float [000230] D------N---- | +--* LCL_VAR float V27 tmp13 [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 [000235] -A---------- \--* ASG float [000233] D------N---- +--* LCL_VAR float V28 tmp14 [000234] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00034 (IL 0x023... ???) [000160] -A---+------ * ASG float [000159] D----+-N---- +--* LCL_VAR float V16 tmp2 [000131] -----+------ \--* SUB float [000123] -----+------ +--* MUL float [000119] -----+------ | +--* LCL_VAR float V25 tmp11 [000122] -----+------ | \--* LCL_VAR float V25 tmp11 [000130] -----+------ \--* MUL float [000126] -----+------ +--* LCL_VAR float V26 tmp12 [000129] -----+------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00035 (IL 0x023... ???) [000162] -A---+------ * ASG float [000161] D----+-N---- +--* LCL_VAR float V17 tmp3 [000140] -----+------ \--* MUL float [000136] -----+------ +--* MUL float [000135] -----+------ | +--* LCL_VAR float V25 tmp11 [000132] -----+------ | \--* CNS_DBL float 2.0000000000000000 [000139] -----+------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00032 (IL 0x023... ???) [000153] -A---+------ * ASG float [000152] D----+-N---- +--* LCL_VAR float V27 tmp13 [000151] -----+------ \--* LCL_VAR float V16 tmp2 ***** BB04 STMT00033 (IL 0x023... ???) [000158] -A---+------ * ASG float [000157] D----+-N---- +--* LCL_VAR float V28 tmp14 [000156] -----+------ \--* LCL_VAR float V17 tmp3 ***** BB04 STMT00014 (IL ???... ???) [000049] -A---+------ * ASG long [000046] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000147] -----+------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 ***** BB04 STMT00038 (IL 0x02C... ???) [000243] -A---+------ * COMMA void [000239] -A---------- +--* ASG float [000237] D------N---- | +--* LCL_VAR float V29 tmp15 [000238] -------N---- | \--* LCL_VAR float V25 tmp11 [000242] -A---------- \--* ASG float [000240] D------N---- +--* LCL_VAR float V30 tmp16 [000241] -------N---- \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00039 (IL 0x02C... ???) [000250] -A---+------ * COMMA void [000246] -A---------- +--* ASG float [000244] D------N---- | +--* LCL_VAR float V31 tmp17 [000245] -------N---- | \--* LCL_VAR float V23 tmp9 [000249] -A---------- \--* ASG float [000247] D------N---- +--* LCL_VAR float V32 tmp18 [000248] -------N---- \--* LCL_VAR float V24 tmp10 ***** BB04 STMT00036 (IL 0x02C... ???) [000257] -A---+------ * COMMA void [000253] -A---------- +--* ASG float [000251] D------N---- | +--* LCL_VAR float V33 tmp19 [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 [000256] -A---------- \--* ASG float [000254] D------N---- +--* LCL_VAR float V34 tmp20 [000255] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00040 (IL 0x02C... ???) [000196] -A---+------ * ASG float [000195] D----+-N---- +--* LCL_VAR float V33 tmp19 [000170] -----+------ \--* ADD float [000166] -----+------ +--* LCL_VAR float V25 tmp11 [000169] -----+------ \--* LCL_VAR float V23 tmp9 ***** BB04 STMT00041 (IL 0x02C... ???) [000201] -A---+------ * ASG float [000200] D----+-N---- +--* LCL_VAR float V34 tmp20 [000177] -----+------ \--* ADD float [000173] -----+------ +--* LCL_VAR float V26 tmp12 [000176] -----+------ \--* LCL_VAR float V24 tmp10 ***** BB04 STMT00016 (IL ???... ???) [000061] -A---+------ * ASG long [000058] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000184] -----+------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 ***** BB04 STMT00017 (IL 0x037...0x03B) [000066] -A---+------ * ASG int [000065] D----+-N---- +--* LCL_VAR int V12 loc6 [000064] -----+------ \--* ADD int [000062] -----+------ +--* LCL_VAR int V12 loc6 [000063] -----+------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) [000072] -A---+------ * ASG float [000071] D----+-N---- +--* LCL_VAR float V13 loc7 [000217] -----+------ \--* ADD float [000209] -----+------ +--* MUL float [000205] -----+------ | +--* LCL_VAR float V25 tmp11 [000208] -----+------ | \--* LCL_VAR float V25 tmp11 [000216] -----+------ \--* MUL float [000212] -----+------ +--* LCL_VAR float V26 tmp12 [000215] -----+------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00020 (IL 0x046...0x04D) [000076] -----+------ * JTRUE void [000075] N----+-N-U-- \--* GE int [000073] -----+------ +--* LCL_VAR float V13 loc7 [000074] -----+------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) [000097] -----+------ * JTRUE void [000096] J----+-N---- \--* LT int [000094] -----+------ +--* LCL_VAR int V12 loc6 [000095] -----+------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) [000083] --CXG+------ * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG+------ this in rcx +--* IND ref [000259] -----+------ | \--* ADD byref [000077] -----+------ | +--* LCL_VAR ref V00 this [000258] -----+------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] [000080] -----+------ arg1 in rdx +--* LCL_VAR int V08 loc2 [000081] -----+------ arg2 in r8 +--* LCL_VAR int V06 loc0 [000082] -----+------ arg3 in r9 \--* LCL_VAR int V12 loc6 ***** BB06 STMT00023 (IL 0x067... ???) [000088] -A---+------ * ASG float [000087] D----+-N---- +--* LCL_VAR float V09 loc3 [000086] -----+------ \--* ADD float [000084] -----+------ +--* LCL_VAR float V09 loc3 [000085] -----+------ \--* LCL_VAR float V05 arg5 ***** BB06 STMT00024 (IL 0x06C...0x06F) [000093] -A---+------ * ASG int [000092] D----+-N---- +--* LCL_VAR int V08 loc2 [000091] -----+------ \--* ADD int [000089] -----+------ +--* LCL_VAR int V08 loc2 [000090] -----+------ \--* CNS_INT int 1 ***** BB06 STMT00008 (IL 0x070...0x072) [000026] -----+------ * JTRUE void ( 7, 9) [000025] J------N---- \--* LT int ( 3, 4) [000023] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000024] ------------ \--* LCL_VAR float V02 arg2 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) [000102] -A---+------ * ASG float [000101] D----+-N---- +--* LCL_VAR float V07 loc1 [000100] -----+------ \--* ADD float [000098] -----+------ +--* LCL_VAR float V07 loc1 [000099] -----+------ \--* LCL_VAR float V05 arg5 ***** BB07 STMT00027 (IL 0x079...0x07C) [000107] -A---+------ * ASG int [000106] D----+-N---- +--* LCL_VAR int V06 loc0 [000105] -----+------ \--* ADD int [000103] -----+------ +--* LCL_VAR int V06 loc0 [000104] -----+------ \--* CNS_INT int 1 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00002 (IL 0x07D...0x080) [000009] -----+------ * JTRUE void [000008] N----+-N-U-- \--* GE int [000006] -----+------ +--* LCL_VAR float V07 loc1 [000007] -----+------ \--* LCL_VAR float V04 arg4 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000012] --CXG+------ +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] -----+------ this in rcx | \--* LCL_VAR ref V00 this [000014] -----+------ \--* CNS_INT int 0 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) [000010] -----+------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In optUnrollLoops() *************** In fgDebugCheckBBlist *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00000 (IL 0x000...0x001) [000002] -A---+------ * ASG int [000001] D----+-N---- +--* LCL_VAR int V06 loc0 [000000] -----+------ \--* CNS_INT int 0 New refCnts for V06: refCnt = 1, refCntWtd = 1 STMT00001 (IL 0x002...0x003) [000005] -A---+------ * ASG float [000004] D----+-N---- +--* LCL_VAR float V07 loc1 [000003] -----+------ \--* LCL_VAR float V03 arg3 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB02 (weight=2 ) STMT00006 (IL 0x006...0x007) [000019] -A---+------ * ASG int [000018] D----+-N---- +--* LCL_VAR int V08 loc2 [000017] -----+------ \--* CNS_INT int 0 New refCnts for V08: refCnt = 1, refCntWtd = 2 STMT00007 (IL 0x008...0x009) [000022] -A---+------ * ASG float [000021] D----+-N---- +--* LCL_VAR float V09 loc3 [000020] -----+------ \--* LCL_VAR float V01 arg1 New refCnts for V09: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 1, refCntWtd = 2 STMT00042 (IL 0x070... ???) [000268] ------------ * JTRUE void ( 7, 9) [000265] N------N---- \--* GE int ( 3, 4) [000266] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000267] ------------ \--* LCL_VAR float V02 arg2 New refCnts for V09: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 1, refCntWtd = 2 *** marking local variables in block BB03 (weight=16 ) STMT00028 (IL 0x00C... ???) [000111] -A---+------ * ASG float [000110] D----+-N---- +--* LCL_VAR float V23 tmp9 [000029] -----+------ \--* LCL_VAR float V09 loc3 New refCnts for V23: refCnt = 1, refCntWtd = 16 New refCnts for V09: refCnt = 3, refCntWtd = 20 STMT00029 (IL 0x00C... ???) [000115] -A---+------ * ASG float [000114] D----+-N---- +--* LCL_VAR float V24 tmp10 [000030] -----+------ \--* LCL_VAR float V07 loc1 New refCnts for V24: refCnt = 1, refCntWtd = 16 New refCnts for V07: refCnt = 2, refCntWtd = 17 STMT00010 (IL 0x015... ???) [000229] -A---+------ * COMMA void [000225] -A---------- +--* ASG float [000223] D------N---- | +--* LCL_VAR float V25 tmp11 [000224] ------------ | \--* LCL_VAR float V23 tmp9 [000228] -A---------- \--* ASG float [000226] D------N---- +--* LCL_VAR float V26 tmp12 [000227] ------------ \--* LCL_VAR float V24 tmp10 New refCnts for V11: refCnt = 1, refCntWtd = 16 New refCnts for V25: refCnt = 1, refCntWtd = 16 New refCnts for V23: refCnt = 2, refCntWtd = 32 New refCnts for V11: refCnt = 2, refCntWtd = 32 New refCnts for V26: refCnt = 1, refCntWtd = 16 New refCnts for V24: refCnt = 2, refCntWtd = 32 STMT00011 (IL 0x019...0x01A) [000038] -A---+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V12 loc6 [000036] -----+------ \--* CNS_INT int 0 New refCnts for V12: refCnt = 1, refCntWtd = 16 STMT00012 (IL 0x01C...0x021) [000041] -A---+------ * ASG float [000040] D----+-N---- +--* LCL_VAR float V13 loc7 [000039] -----+------ \--* CNS_DBL float 0.00000000000000000 New refCnts for V13: refCnt = 1, refCntWtd = 16 *** marking local variables in block BB04 (weight=128 ) STMT00030 (IL 0x023... ???) [000236] -A---+------ * COMMA void [000232] -A---------- +--* ASG float [000230] D------N---- | +--* LCL_VAR float V27 tmp13 [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 [000235] -A---------- \--* ASG float [000233] D------N---- +--* LCL_VAR float V28 tmp14 [000234] ------------ \--* CNS_DBL float 0.00000000000000000 New refCnts for V15: refCnt = 1, refCntWtd = 256 New refCnts for V27: refCnt = 1, refCntWtd = 128 New refCnts for V15: refCnt = 2, refCntWtd = 512 New refCnts for V28: refCnt = 1, refCntWtd = 128 STMT00034 (IL 0x023... ???) [000160] -A---+------ * ASG float [000159] D----+-N---- +--* LCL_VAR float V16 tmp2 [000131] -----+------ \--* SUB float [000123] -----+------ +--* MUL float [000119] -----+------ | +--* LCL_VAR float V25 tmp11 [000122] -----+------ | \--* LCL_VAR float V25 tmp11 [000130] -----+------ \--* MUL float [000126] -----+------ +--* LCL_VAR float V26 tmp12 [000129] -----+------ \--* LCL_VAR float V26 tmp12 New refCnts for V16: refCnt = 1, refCntWtd = 256 New refCnts for V11: refCnt = 3, refCntWtd = 160 New refCnts for V25: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 4, refCntWtd = 288 New refCnts for V25: refCnt = 3, refCntWtd = 272 New refCnts for V11: refCnt = 5, refCntWtd = 416 New refCnts for V26: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 6, refCntWtd = 544 New refCnts for V26: refCnt = 3, refCntWtd = 272 STMT00035 (IL 0x023... ???) [000162] -A---+------ * ASG float [000161] D----+-N---- +--* LCL_VAR float V17 tmp3 [000140] -----+------ \--* MUL float [000136] -----+------ +--* MUL float [000135] -----+------ | +--* LCL_VAR float V25 tmp11 [000132] -----+------ | \--* CNS_DBL float 2.0000000000000000 [000139] -----+------ \--* LCL_VAR float V26 tmp12 New refCnts for V17: refCnt = 1, refCntWtd = 256 New refCnts for V11: refCnt = 7, refCntWtd = 672 New refCnts for V25: refCnt = 4, refCntWtd = 400 New refCnts for V11: refCnt = 8, refCntWtd = 800 New refCnts for V26: refCnt = 4, refCntWtd = 400 STMT00032 (IL 0x023... ???) [000153] -A---+------ * ASG float [000152] D----+-N---- +--* LCL_VAR float V27 tmp13 [000151] -----+------ \--* LCL_VAR float V16 tmp2 New refCnts for V15: refCnt = 3, refCntWtd = 768 New refCnts for V27: refCnt = 2, refCntWtd = 256 New refCnts for V16: refCnt = 2, refCntWtd = 512 STMT00033 (IL 0x023... ???) [000158] -A---+------ * ASG float [000157] D----+-N---- +--* LCL_VAR float V28 tmp14 [000156] -----+------ \--* LCL_VAR float V17 tmp3 New refCnts for V15: refCnt = 4, refCntWtd = 1024 New refCnts for V28: refCnt = 2, refCntWtd = 256 New refCnts for V17: refCnt = 2, refCntWtd = 512 STMT00014 (IL ???... ???) [000049] -A---+------ * ASG long [000046] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000147] -----+------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 New refCnts for V25: refCnt = 5, refCntWtd = 528 New refCnts for V26: refCnt = 5, refCntWtd = 528 New refCnts for V11: refCnt = 9, refCntWtd = 928 New refCnts for V27: refCnt = 3, refCntWtd = 512 New refCnts for V28: refCnt = 3, refCntWtd = 512 New refCnts for V15: refCnt = 5, refCntWtd = 1280 STMT00038 (IL 0x02C... ???) [000243] -A---+------ * COMMA void [000239] -A---------- +--* ASG float [000237] D------N---- | +--* LCL_VAR float V29 tmp15 [000238] -------N---- | \--* LCL_VAR float V25 tmp11 [000242] -A---------- \--* ASG float [000240] D------N---- +--* LCL_VAR float V30 tmp16 [000241] -------N---- \--* LCL_VAR float V26 tmp12 New refCnts for V29: refCnt = 1, refCntWtd = 128 New refCnts for V11: refCnt = 10, refCntWtd = 1056 New refCnts for V25: refCnt = 6, refCntWtd = 656 New refCnts for V30: refCnt = 1, refCntWtd = 128 New refCnts for V11: refCnt = 11, refCntWtd = 1184 New refCnts for V26: refCnt = 6, refCntWtd = 656 STMT00039 (IL 0x02C... ???) [000250] -A---+------ * COMMA void [000246] -A---------- +--* ASG float [000244] D------N---- | +--* LCL_VAR float V31 tmp17 [000245] -------N---- | \--* LCL_VAR float V23 tmp9 [000249] -A---------- \--* ASG float [000247] D------N---- +--* LCL_VAR float V32 tmp18 [000248] -------N---- \--* LCL_VAR float V24 tmp10 New refCnts for V31: refCnt = 1, refCntWtd = 128 New refCnts for V23: refCnt = 3, refCntWtd = 160 New refCnts for V32: refCnt = 1, refCntWtd = 128 New refCnts for V24: refCnt = 3, refCntWtd = 160 STMT00036 (IL 0x02C... ???) [000257] -A---+------ * COMMA void [000253] -A---------- +--* ASG float [000251] D------N---- | +--* LCL_VAR float V33 tmp19 [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 [000256] -A---------- \--* ASG float [000254] D------N---- +--* LCL_VAR float V34 tmp20 [000255] ------------ \--* CNS_DBL float 0.00000000000000000 New refCnts for V20: refCnt = 1, refCntWtd = 256 New refCnts for V33: refCnt = 1, refCntWtd = 128 New refCnts for V20: refCnt = 2, refCntWtd = 512 New refCnts for V34: refCnt = 1, refCntWtd = 128 STMT00040 (IL 0x02C... ???) [000196] -A---+------ * ASG float [000195] D----+-N---- +--* LCL_VAR float V33 tmp19 [000170] -----+------ \--* ADD float [000166] -----+------ +--* LCL_VAR float V25 tmp11 [000169] -----+------ \--* LCL_VAR float V23 tmp9 New refCnts for V20: refCnt = 3, refCntWtd = 768 New refCnts for V33: refCnt = 2, refCntWtd = 256 New refCnts for V11: refCnt = 12, refCntWtd = 1312 New refCnts for V25: refCnt = 7, refCntWtd = 784 New refCnts for V23: refCnt = 4, refCntWtd = 288 STMT00041 (IL 0x02C... ???) [000201] -A---+------ * ASG float [000200] D----+-N---- +--* LCL_VAR float V34 tmp20 [000177] -----+------ \--* ADD float [000173] -----+------ +--* LCL_VAR float V26 tmp12 [000176] -----+------ \--* LCL_VAR float V24 tmp10 New refCnts for V20: refCnt = 4, refCntWtd = 1024 New refCnts for V34: refCnt = 2, refCntWtd = 256 New refCnts for V11: refCnt = 13, refCntWtd = 1440 New refCnts for V26: refCnt = 7, refCntWtd = 784 New refCnts for V24: refCnt = 4, refCntWtd = 288 STMT00016 (IL ???... ???) [000061] -A---+------ * ASG long [000058] D----+-N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 [000184] -----+------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 New refCnts for V25: refCnt = 8, refCntWtd = 912 New refCnts for V26: refCnt = 8, refCntWtd = 912 New refCnts for V11: refCnt = 14, refCntWtd = 1568 New refCnts for V33: refCnt = 3, refCntWtd = 512 New refCnts for V34: refCnt = 3, refCntWtd = 512 New refCnts for V20: refCnt = 5, refCntWtd = 1280 STMT00017 (IL 0x037...0x03B) [000066] -A---+------ * ASG int [000065] D----+-N---- +--* LCL_VAR int V12 loc6 [000064] -----+------ \--* ADD int [000062] -----+------ +--* LCL_VAR int V12 loc6 [000063] -----+------ \--* CNS_INT int 1 New refCnts for V12: refCnt = 2, refCntWtd = 144 New refCnts for V12: refCnt = 3, refCntWtd = 272 STMT00019 (IL ???... ???) [000072] -A---+------ * ASG float [000071] D----+-N---- +--* LCL_VAR float V13 loc7 [000217] -----+------ \--* ADD float [000209] -----+------ +--* MUL float [000205] -----+------ | +--* LCL_VAR float V25 tmp11 [000208] -----+------ | \--* LCL_VAR float V25 tmp11 [000216] -----+------ \--* MUL float [000212] -----+------ +--* LCL_VAR float V26 tmp12 [000215] -----+------ \--* LCL_VAR float V26 tmp12 New refCnts for V13: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 15, refCntWtd = 1696 New refCnts for V25: refCnt = 9, refCntWtd = 1040 New refCnts for V11: refCnt = 16, refCntWtd = 1824 New refCnts for V25: refCnt = 10, refCntWtd = 1168 New refCnts for V11: refCnt = 17, refCntWtd = 1952 New refCnts for V26: refCnt = 9, refCntWtd = 1040 New refCnts for V11: refCnt = 18, refCntWtd = 2080 New refCnts for V26: refCnt = 10, refCntWtd = 1168 STMT00020 (IL 0x046...0x04D) [000076] -----+------ * JTRUE void [000075] N----+-N-U-- \--* GE int [000073] -----+------ +--* LCL_VAR float V13 loc7 [000074] -----+------ \--* CNS_DBL float 4.0000000000000000 New refCnts for V13: refCnt = 3, refCntWtd = 272 *** marking local variables in block BB05 (weight=64 ) STMT00025 (IL 0x04F...0x056) [000097] -----+------ * JTRUE void [000096] J----+-N---- \--* LT int [000094] -----+------ +--* LCL_VAR int V12 loc6 [000095] -----+------ \--* CNS_INT int 0x3E8 New refCnts for V12: refCnt = 4, refCntWtd = 336 *** marking local variables in block BB06 (weight=16 ) STMT00022 (IL ???... ???) [000083] --CXG+------ * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke [000219] ---XG+------ this in rcx +--* IND ref [000259] -----+------ | \--* ADD byref [000077] -----+------ | +--* LCL_VAR ref V00 this [000258] -----+------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] [000080] -----+------ arg1 in rdx +--* LCL_VAR int V08 loc2 [000081] -----+------ arg2 in r8 +--* LCL_VAR int V06 loc0 [000082] -----+------ arg3 in r9 \--* LCL_VAR int V12 loc6 New refCnts for V00: refCnt = 1, refCntWtd = 16 New refCnts for V08: refCnt = 2, refCntWtd = 18 New refCnts for V06: refCnt = 2, refCntWtd = 17 New refCnts for V12: refCnt = 5, refCntWtd = 352 STMT00023 (IL 0x067... ???) [000088] -A---+------ * ASG float [000087] D----+-N---- +--* LCL_VAR float V09 loc3 [000086] -----+------ \--* ADD float [000084] -----+------ +--* LCL_VAR float V09 loc3 [000085] -----+------ \--* LCL_VAR float V05 arg5 New refCnts for V09: refCnt = 4, refCntWtd = 36 New refCnts for V09: refCnt = 5, refCntWtd = 52 New refCnts for V05: refCnt = 1, refCntWtd = 16 STMT00024 (IL 0x06C...0x06F) [000093] -A---+------ * ASG int [000092] D----+-N---- +--* LCL_VAR int V08 loc2 [000091] -----+------ \--* ADD int [000089] -----+------ +--* LCL_VAR int V08 loc2 [000090] -----+------ \--* CNS_INT int 1 New refCnts for V08: refCnt = 3, refCntWtd = 34 New refCnts for V08: refCnt = 4, refCntWtd = 50 STMT00008 (IL 0x070...0x072) [000026] -----+------ * JTRUE void ( 7, 9) [000025] J------N---- \--* LT int ( 3, 4) [000023] ------------ +--* LCL_VAR float V09 loc3 ( 3, 4) [000024] ------------ \--* LCL_VAR float V02 arg2 New refCnts for V09: refCnt = 6, refCntWtd = 68 New refCnts for V02: refCnt = 2, refCntWtd = 18 *** marking local variables in block BB07 (weight=2 ) STMT00026 (IL 0x074...0x078) [000102] -A---+------ * ASG float [000101] D----+-N---- +--* LCL_VAR float V07 loc1 [000100] -----+------ \--* ADD float [000098] -----+------ +--* LCL_VAR float V07 loc1 [000099] -----+------ \--* LCL_VAR float V05 arg5 New refCnts for V07: refCnt = 3, refCntWtd = 19 New refCnts for V07: refCnt = 4, refCntWtd = 21 New refCnts for V05: refCnt = 2, refCntWtd = 18 STMT00027 (IL 0x079...0x07C) [000107] -A---+------ * ASG int [000106] D----+-N---- +--* LCL_VAR int V06 loc0 [000105] -----+------ \--* ADD int [000103] -----+------ +--* LCL_VAR int V06 loc0 [000104] -----+------ \--* CNS_INT int 1 New refCnts for V06: refCnt = 3, refCntWtd = 19 New refCnts for V06: refCnt = 4, refCntWtd = 21 *** marking local variables in block BB08 (weight=8 ) STMT00002 (IL 0x07D...0x080) [000009] -----+------ * JTRUE void [000008] N----+-N-U-- \--* GE int [000006] -----+------ +--* LCL_VAR float V07 loc1 [000007] -----+------ \--* LCL_VAR float V04 arg4 New refCnts for V07: refCnt = 5, refCntWtd = 29 New refCnts for V04: refCnt = 1, refCntWtd = 8 *** marking local variables in block BB09 (weight=4 ) STMT00005 (IL ???... ???) [000016] --CXG+------ * JTRUE void [000015] J-CXG+-N---- \--* EQ int [000012] --CXG+------ +--* CALL int Algorithms.FractalRenderer.get_Abort [000011] -----+------ this in rcx | \--* LCL_VAR ref V00 this [000014] -----+------ \--* CNS_INT int 0 New refCnts for V00: refCnt = 2, refCntWtd = 20 *** marking local variables in block BB10 (weight=1 ) STMT00003 (IL 0x08D...0x08D) [000010] -----+------ * RETURN void *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 21 New refCnts for V00: refCnt = 4, refCntWtd = 22 New refCnts for V01: refCnt = 2, refCntWtd = 3 New refCnts for V01: refCnt = 3, refCntWtd = 4 New refCnts for V02: refCnt = 3, refCntWtd = 19 New refCnts for V02: refCnt = 4, refCntWtd = 20 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 *************** In optAddCopies() *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** In fgFindOperOrder() *************** In fgSetBlockOrder() fgMarkLoopHead: Checking loop head block BB02: this block will execute a call fgMarkLoopHead: Checking loop head block BB03: this block will execute a call fgMarkLoopHead: Checking loop head block BB04: no guaranteed callsite exits, marking method as fully interruptible The biggest BB has 12 tree nodes ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V09 loc3 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void N003 ( 1, 3) [000225] -A------R--- +--* ASG float N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 N006 ( 1, 3) [000228] -A------R--- \--* ASG float N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 ***** BB03 STMT00012 (IL 0x01C...0x021) N003 ( 1, 3) [000041] -A------R--- * ASG float N002 ( 1, 2) [000040] D------N---- +--* LCL_VAR float V13 loc7 N001 ( 1, 1) [000039] ------------ \--* CNS_DBL float 0.00000000000000000 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void N003 ( 1, 3) [000232] -A------R--- +--* ASG float N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 N006 ( 1, 3) [000235] -A------R--- \--* ASG float N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 N007 ( 19, 20) [000131] ------------ \--* SUB float N003 ( 7, 8) [000123] ------------ +--* MUL float N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 N006 ( 7, 8) [000130] ------------ \--* MUL float N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 N005 ( 15, 16) [000140] ------------ \--* MUL float N003 ( 9, 10) [000136] ------------ +--* MUL float N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 ***** BB04 STMT00038 (IL 0x02C... ???) N007 ( 2, 6) [000243] -A---------- * COMMA void N003 ( 1, 3) [000239] -A------R--- +--* ASG float N002 ( 1, 2) [000237] D------N---- | +--* LCL_VAR float V29 tmp15 N001 ( 1, 2) [000238] -------N---- | \--* LCL_VAR float V25 tmp11 N006 ( 1, 3) [000242] -A------R--- \--* ASG float N005 ( 1, 2) [000240] D------N---- +--* LCL_VAR float V30 tmp16 N004 ( 1, 2) [000241] -------N---- \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00039 (IL 0x02C... ???) N007 ( 2, 6) [000250] -A---------- * COMMA void N003 ( 1, 3) [000246] -A------R--- +--* ASG float N002 ( 1, 2) [000244] D------N---- | +--* LCL_VAR float V31 tmp17 N001 ( 1, 2) [000245] -------N---- | \--* LCL_VAR float V23 tmp9 N006 ( 1, 3) [000249] -A------R--- \--* ASG float N005 ( 1, 2) [000247] D------N---- +--* LCL_VAR float V32 tmp18 N004 ( 1, 2) [000248] -------N---- \--* LCL_VAR float V24 tmp10 ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void N003 ( 1, 3) [000253] -A------R--- +--* ASG float N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 N006 ( 1, 3) [000256] -A------R--- \--* ASG float N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 N003 ( 3, 3) [000064] ------------ \--* ADD int N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 N007 ( 19, 20) [000217] ------------ \--* ADD float N003 ( 7, 8) [000209] ------------ +--* MUL float N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 N006 ( 7, 8) [000216] ------------ \--* MUL float N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 N003 ( 7, 8) [000086] ------------ \--* ADD float N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 N003 ( 3, 3) [000091] ------------ \--* ADD int N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 N003 ( 7, 8) [000100] ------------ \--* ADD float N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 N003 ( 3, 3) [000105] ------------ \--* ADD int N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 11. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB08 BB02 : BB07 BB03 BB03 : BB04 BB04 : BB06 BB05 BB08 : BB10 BB09 BB09 : BB02 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V25 should not be enregistered because: field of a dependently promoted struct Local V26 should not be enregistered because: field of a dependently promoted struct Local V27 should not be enregistered because: field of a dependently promoted struct Local V28 should not be enregistered because: field of a dependently promoted struct Local V33 should not be enregistered because: field of a dependently promoted struct Local V34 should not be enregistered because: field of a dependently promoted struct Tracked variable (20 out of 35) table: V12 loc6 [ int]: refCnt = 5, refCntWtd = 352 V08 loc2 [ int]: refCnt = 4, refCntWtd = 50 V00 this [ ref]: refCnt = 4, refCntWtd = 22 V06 loc0 [ int]: refCnt = 4, refCntWtd = 21 V16 tmp2 [ float]: refCnt = 2, refCntWtd = 512 V17 tmp3 [ float]: refCnt = 2, refCntWtd = 512 V23 tmp9 [ float]: refCnt = 4, refCntWtd = 288 V24 tmp10 [ float]: refCnt = 4, refCntWtd = 288 V13 loc7 [ float]: refCnt = 3, refCntWtd = 272 V29 tmp15 [ float]: refCnt = 1, refCntWtd = 128 V30 tmp16 [ float]: refCnt = 1, refCntWtd = 128 V31 tmp17 [ float]: refCnt = 1, refCntWtd = 128 V32 tmp18 [ float]: refCnt = 1, refCntWtd = 128 V09 loc3 [ float]: refCnt = 6, refCntWtd = 68 V07 loc1 [ float]: refCnt = 5, refCntWtd = 29 V02 arg2 [ float]: refCnt = 4, refCntWtd = 20 V05 arg5 [ float]: refCnt = 2, refCntWtd = 18 V04 arg4 [ float]: refCnt = 1, refCntWtd = 8 V01 arg1 [ float]: refCnt = 3, refCntWtd = 4 V03 arg3 [ float]: refCnt = 3, refCntWtd = 3 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={ V03} DEF(2)={V06 V07 } BB02 USE(2)={ V02 V01} DEF(2)={V08 V09 } BB03 USE(2)={ V09 V07} DEF(4)={V12 V23 V24 V13 } BB04 USE(3)={V12 V23 V24 } DEF(8)={V12 V16 V17 V13 V29 V30 V31 V32} BB05 USE(1)={V12} DEF(0)={ } BB06 USE(7)={V12 V08 V00 V06 V09 V02 V05} + ByrefExposed + GcHeap DEF(2)={ V08 V09 } + ByrefExposed* + GcHeap* BB07 USE(3)={V06 V07 V05} DEF(2)={V06 V07 } BB08 USE(2)={V07 V04} DEF(0)={ } BB09 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB10 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (6)={V00 V02 V05 V04 V01 V03} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V04 V01 } + ByrefExposed + GcHeap BB02 IN (7)={ V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(9)={V08 V00 V06 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB03 IN (9)={ V08 V00 V06 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB04 IN (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB05 IN (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB06 IN (10)={V12 V08 V00 V06 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(9)={ V08 V00 V06 V09 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB07 IN (7)={V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB08 IN (7)={V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB09 IN (7)={V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V04 V01} + ByrefExposed + GcHeap BB10 IN (0)={} OUT(0)={} top level assign removing stmt with no side effects Removing statement STMT00012 (IL 0x01C...0x021) N003 ( 1, 3) [000041] -A------R--- * ASG float N002 ( 1, 2) [000040] D------N---- +--* LCL_VAR float V13 loc7 N001 ( 1, 1) [000039] ------------ \--* CNS_DBL float 0.00000000000000000 in BB03 as useless: Removing tree [000249] in BB04 as useless N006 ( 1, 3) [000249] -A------R--- * ASG float N005 ( 1, 2) [000247] D------N---- +--* LCL_VAR float V32 tmp18 N004 ( 1, 2) [000248] -------N---- \--* LCL_VAR float V24 tmp10 Removing tree [000246] in BB04 as useless N003 ( 1, 3) [000246] -A------R--- * ASG float N002 ( 1, 2) [000244] D------N---- +--* LCL_VAR float V31 tmp17 N001 ( 1, 2) [000245] -------N---- \--* LCL_VAR float V23 tmp9 fgComputeLife modified tree: N003 ( 0, 0) [000250] ------------ * COMMA void N001 ( 0, 0) [000246] ------------ +--* NOP void N002 ( 0, 0) [000249] ------------ \--* NOP void Removing tree [000242] in BB04 as useless N006 ( 1, 3) [000242] -A------R--- * ASG float N005 ( 1, 2) [000240] D------N---- +--* LCL_VAR float V30 tmp16 N004 ( 1, 2) [000241] -------N---- \--* LCL_VAR float V26 tmp12 Removing tree [000239] in BB04 as useless N003 ( 1, 3) [000239] -A------R--- * ASG float N002 ( 1, 2) [000237] D------N---- +--* LCL_VAR float V29 tmp15 N001 ( 1, 2) [000238] -------N---- \--* LCL_VAR float V25 tmp11 fgComputeLife modified tree: N003 ( 0, 0) [000243] ------------ * COMMA void N001 ( 0, 0) [000239] ------------ +--* NOP void N002 ( 0, 0) [000242] ------------ \--* NOP void *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Added PHI definition for V06 at start of BB08. Added PHI definition for V07 at start of BB08. Added PHI definition for V08 at start of BB03. Added PHI definition for V09 at start of BB03. Inserting phi definition for ByrefExposed at start of BB07. Inserting phi definition for ByrefExposed at start of BB03. Inserting phi definition for ByrefExposed at start of BB08. Added PHI definition for V12 at start of BB04. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V09 loc3 u:2 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00046 (IL ???... ???) N005 ( 0, 0) [000280] -A------R--- * ASG float N004 ( 0, 0) [000278] D------N---- +--* LCL_VAR float V09 loc3 d:3 N003 ( 0, 0) [000279] ------------ \--* PHI float N001 ( 0, 0) [000291] ------------ pred BB06 +--* PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ pred BB02 \--* PHI_ARG float V09 loc3 u:2 ***** BB03 STMT00045 (IL ???... ???) N005 ( 0, 0) [000277] -A------R--- * ASG int N004 ( 0, 0) [000275] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000276] ------------ \--* PHI int N001 ( 0, 0) [000292] ------------ pred BB06 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ pred BB02 \--* PHI_ARG int V08 loc2 u:2 ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void N003 ( 1, 3) [000225] -A------R--- +--* ASG float N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 N006 ( 1, 3) [000228] -A------R--- \--* ASG float N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00047 (IL ???... ???) N005 ( 0, 0) [000283] -A------R--- * ASG int N004 ( 0, 0) [000281] D------N---- +--* LCL_VAR int V12 loc6 d:3 N003 ( 0, 0) [000282] ------------ \--* PHI int N001 ( 0, 0) [000293] ------------ pred BB05 +--* PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ pred BB03 \--* PHI_ARG int V12 loc6 u:2 ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void N003 ( 1, 3) [000232] -A------R--- +--* ASG float N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 N006 ( 1, 3) [000235] -A------R--- \--* ASG float N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 N007 ( 19, 20) [000131] ------------ \--* SUB float N003 ( 7, 8) [000123] ------------ +--* MUL float N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 N006 ( 7, 8) [000130] ------------ \--* MUL float N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 N005 ( 15, 16) [000140] ------------ \--* MUL float N003 ( 9, 10) [000136] ------------ +--* MUL float N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 ***** BB04 STMT00038 (IL 0x02C... ???) N003 ( 0, 0) [000243] ------------ * COMMA void N001 ( 0, 0) [000239] ------------ +--* NOP void N002 ( 0, 0) [000242] ------------ \--* NOP void ***** BB04 STMT00039 (IL 0x02C... ???) N003 ( 0, 0) [000250] ------------ * COMMA void N001 ( 0, 0) [000246] ------------ +--* NOP void N002 ( 0, 0) [000249] ------------ \--* NOP void ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void N003 ( 1, 3) [000253] -A------R--- +--* ASG float N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 N006 ( 1, 3) [000256] -A------R--- \--* ASG float N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 N003 ( 3, 3) [000064] ------------ \--* ADD int N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 N007 ( 19, 20) [000217] ------------ \--* ADD float N003 ( 7, 8) [000209] ------------ +--* MUL float N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 N006 ( 7, 8) [000216] ------------ \--* MUL float N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 N003 ( 7, 8) [000086] ------------ \--* ADD float N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 N003 ( 3, 3) [000091] ------------ \--* ADD int N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 N003 ( 7, 8) [000100] ------------ \--* ADD float N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 N003 ( 3, 3) [000105] ------------ \--* ADD int N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00044 (IL ???... ???) N005 ( 0, 0) [000274] -A------R--- * ASG float N004 ( 0, 0) [000272] D------N---- +--* LCL_VAR float V07 loc1 d:3 N003 ( 0, 0) [000273] ------------ \--* PHI float N001 ( 0, 0) [000288] ------------ pred BB07 +--* PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ pred BB01 \--* PHI_ARG float V07 loc1 u:2 ***** BB08 STMT00043 (IL ???... ???) N005 ( 0, 0) [000271] -A------R--- * ASG int N004 ( 0, 0) [000269] D------N---- +--* LCL_VAR int V06 loc0 d:3 N003 ( 0, 0) [000270] ------------ \--* PHI int N001 ( 0, 0) [000289] ------------ pred BB07 +--* PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ pred BB01 \--* PHI_ARG int V06 loc0 u:2 ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void ------------------------------------------------------------------------------------------------------------------- *************** In optEarlyProp() *************** In fgValueNumber() Memory Initial Value in BB01 is: $81 The SSA definition for ByrefExposed (#1) at start of BB01 is $81 {InitVal($46)} The SSA definition for GcHeap (#1) at start of BB01 is $81 {InitVal($46)} ***** BB01, STMT00000(before) N003 ( 1, 3) [000002] -A------R--- * ASG int N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 N001 [000000] CNS_INT 0 => $40 {IntCns 0} N002 [000001] LCL_VAR V06 loc0 d:2 => $40 {IntCns 0} N003 [000002] ASG => $40 {IntCns 0} ***** BB01, STMT00000(after) N003 ( 1, 3) [000002] -A------R--- * ASG int $40 N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 $40 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 $40 --------- ***** BB01, STMT00001(before) N003 ( 1, 3) [000005] -A------R--- * ASG float N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) N001 [000003] LCL_VAR V03 arg3 u:1 (last use) => $c2 {InitVal($43)} N002 [000004] LCL_VAR V07 loc1 d:2 => $c2 {InitVal($43)} N003 [000005] ASG => $c2 {InitVal($43)} ***** BB01, STMT00001(after) N003 ( 1, 3) [000005] -A------R--- * ASG float $c2 N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 $c2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) $c2 finish(BB01). Succ(BB08). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 7/3 to $200 {PhiDef($7, $3, $1c0)} . SSA PHI definition: set VN of local 6/3 to $240 {PhiDef($6, $3, $1c0)} . Computing GcHeap state for block BB08, entry block for loops 0 to 0: Loop 0 has memory havoc effect; heap state is new unique $280. The SSA definition for GcHeap (#2) at start of BB08 is $280 {280} ***** BB08, STMT00002(before) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 N001 [000006] LCL_VAR V07 loc1 u:3 => $200 {PhiDef($7, $3, $1c0)} N002 [000007] LCL_VAR V04 arg4 u:1 => $c3 {InitVal($44)} N003 [000008] GE => $2c0 {GE_UN($200, $c3)} ***** BB08, STMT00002(after) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int $2c0 N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 $c3 finish(BB08). Succ(BB09). Not yet completed. All preds complete, adding to allDone. Succ(BB10). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB09 is $280 {280} The SSA definition for GcHeap (#2) at start of BB09 is $280 {280} ***** BB09, STMT00005(before) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 N001 [000264] ARGPLACE => $281 {281} N002 [000011] LCL_VAR V00 this u:1 => $80 {InitVal($40)} fgCurMemoryVN[GcHeap] assigned for CALL at [000012] to VN: $282. N003 [000012] CALL => $300 {300} N004 [000014] CNS_INT 0 => $40 {IntCns 0} N005 [000015] EQ => $2c1 {EQ($300, $40)} ***** BB09, STMT00005(after) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int $2c1 N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort $300 N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 $80 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 finish(BB09). Succ(BB10). Not yet completed. All preds complete, adding to allDone. Succ(BB02). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#3) at start of BB02 is $282 {282} The SSA definition for GcHeap (#3) at start of BB02 is $282 {282} ***** BB02, STMT00006(before) N003 ( 1, 3) [000019] -A------R--- * ASG int N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 N001 [000017] CNS_INT 0 => $40 {IntCns 0} N002 [000018] LCL_VAR V08 loc2 d:2 => $40 {IntCns 0} N003 [000019] ASG => $40 {IntCns 0} ***** BB02, STMT00006(after) N003 ( 1, 3) [000019] -A------R--- * ASG int $40 N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 $40 --------- ***** BB02, STMT00007(before) N003 ( 1, 3) [000022] -A------R--- * ASG float N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 N001 [000020] LCL_VAR V01 arg1 u:1 => $c0 {InitVal($41)} N002 [000021] LCL_VAR V09 loc3 d:2 => $c0 {InitVal($41)} N003 [000022] ASG => $c0 {InitVal($41)} ***** BB02, STMT00007(after) N003 ( 1, 3) [000022] -A------R--- * ASG float $c0 N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 $c0 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 $c0 --------- ***** BB02, STMT00042(before) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V09 loc3 u:2 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 N001 [000266] LCL_VAR V09 loc3 u:2 => $c0 {InitVal($41)} N002 [000267] LCL_VAR V02 arg2 u:1 => $c1 {InitVal($42)} N003 [000265] GE => $2c2 {GE_UN($c0, $c1)} ***** BB02, STMT00042(after) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int $2c2 N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V09 loc3 u:2 $c0 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 finish(BB02). Succ(BB03). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB07). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#2) at start of BB10 is $280 {280} The SSA definition for GcHeap (#2) at start of BB10 is $280 {280} ***** BB10, STMT00003(before) N001 ( 0, 0) [000010] ------------ * RETURN void N001 [000010] RETURN => $380 {380} ***** BB10, STMT00003(after) N001 ( 0, 0) [000010] ------------ * RETURN void $380 finish(BB10). SSA PHI definition: set VN of local 9/3 to $201 {PhiDef($9, $3, $1c0)} . SSA PHI definition: set VN of local 8/3 to $241 {PhiDef($8, $3, $1c0)} . Computing GcHeap state for block BB03, entry block for loops 1 to 1: Loop 1 has memory havoc effect; heap state is new unique $3c0. The SSA definition for GcHeap (#5) at start of BB03 is $3c0 {3c0} ***** BB03, STMT00028(before) N003 ( 1, 3) [000111] -A------R--- * ASG float N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 N001 [000029] LCL_VAR V09 loc3 u:3 => $201 {PhiDef($9, $3, $1c0)} N002 [000110] LCL_VAR V23 tmp9 d:2 => $201 {PhiDef($9, $3, $1c0)} N003 [000111] ASG => $201 {PhiDef($9, $3, $1c0)} ***** BB03, STMT00028(after) N003 ( 1, 3) [000111] -A------R--- * ASG float $201 N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 $201 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 $201 --------- ***** BB03, STMT00029(before) N003 ( 1, 3) [000115] -A------R--- * ASG float N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 N001 [000030] LCL_VAR V07 loc1 u:3 => $200 {PhiDef($7, $3, $1c0)} N002 [000114] LCL_VAR V24 tmp10 d:2 => $200 {PhiDef($7, $3, $1c0)} N003 [000115] ASG => $200 {PhiDef($7, $3, $1c0)} ***** BB03, STMT00029(after) N003 ( 1, 3) [000115] -A------R--- * ASG float $200 N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 $200 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 $200 --------- ***** BB03, STMT00010(before) N007 ( 2, 6) [000229] -A---------- * COMMA void N003 ( 1, 3) [000225] -A------R--- +--* ASG float N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 N006 ( 1, 3) [000228] -A------R--- \--* ASG float N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 N001 [000224] LCL_VAR V23 tmp9 u:2 => $201 {PhiDef($9, $3, $1c0)} Tree [000225] assigns to non-address-taken local var V25; excluded from SSA, so value not tracked. N003 [000225] ASG => $201 {PhiDef($9, $3, $1c0)} N004 [000227] LCL_VAR V24 tmp10 u:2 => $200 {PhiDef($7, $3, $1c0)} Tree [000228] assigns to non-address-taken local var V26; excluded from SSA, so value not tracked. N006 [000228] ASG => $200 {PhiDef($7, $3, $1c0)} N007 [000229] COMMA => $200 {PhiDef($7, $3, $1c0)} ***** BB03, STMT00010(after) N007 ( 2, 6) [000229] -A---------- * COMMA void $200 N003 ( 1, 3) [000225] -A------R--- +--* ASG float $201 N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 $201 N006 ( 1, 3) [000228] -A------R--- \--* ASG float $200 N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 --------- ***** BB03, STMT00011(before) N003 ( 1, 3) [000038] -A------R--- * ASG int N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 N001 [000036] CNS_INT 0 => $40 {IntCns 0} N002 [000037] LCL_VAR V12 loc6 d:2 => $40 {IntCns 0} N003 [000038] ASG => $40 {IntCns 0} ***** BB03, STMT00011(after) N003 ( 1, 3) [000038] -A------R--- * ASG int $40 N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 $40 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 $40 finish(BB03). Succ(BB04). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 12/3 to $242 {PhiDef($c, $3, $1c0)} . The SSA definition for ByrefExposed (#5) at start of BB04 is $3c0 {3c0} The SSA definition for GcHeap (#5) at start of BB04 is $3c0 {3c0} ***** BB04, STMT00030(before) N007 ( 2, 6) [000236] -A---------- * COMMA void N003 ( 1, 3) [000232] -A------R--- +--* ASG float N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 N006 ( 1, 3) [000235] -A------R--- \--* ASG float N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 N001 [000231] CNS_DBL 0.00000000000000000 => $100 {FltCns[0.000000]} Tree [000232] assigns to non-address-taken local var V27; excluded from SSA, so value not tracked. N003 [000232] ASG => $100 {FltCns[0.000000]} N004 [000234] CNS_DBL 0.00000000000000000 => $100 {FltCns[0.000000]} Tree [000235] assigns to non-address-taken local var V28; excluded from SSA, so value not tracked. N006 [000235] ASG => $100 {FltCns[0.000000]} N007 [000236] COMMA => $100 {FltCns[0.000000]} ***** BB04, STMT00030(after) N007 ( 2, 6) [000236] -A---------- * COMMA void $100 N003 ( 1, 3) [000232] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000235] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 $100 --------- ***** BB04, STMT00034(before) N009 ( 19, 20) [000160] -A------R--- * ASG float N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 N007 ( 19, 20) [000131] ------------ \--* SUB float N003 ( 7, 8) [000123] ------------ +--* MUL float N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 N006 ( 7, 8) [000130] ------------ \--* MUL float N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 N001 [000119] LCL_VAR V25 tmp11 => $480 {480} N002 [000122] LCL_VAR V25 tmp11 => $481 {481} N003 [000123] MUL => $1c1 {MUL($480, $481)} N004 [000126] LCL_VAR V26 tmp12 => $482 {482} N005 [000129] LCL_VAR V26 tmp12 => $483 {483} N006 [000130] MUL => $1c2 {MUL($482, $483)} N007 [000131] SUB => $1c3 {SUB($1c1, $1c2)} N008 [000159] LCL_VAR V16 tmp2 d:2 => $1c3 {SUB($1c1, $1c2)} N009 [000160] ASG => $1c3 {SUB($1c1, $1c2)} ***** BB04, STMT00034(after) N009 ( 19, 20) [000160] -A------R--- * ASG float $1c3 N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 $1c3 N007 ( 19, 20) [000131] ------------ \--* SUB float $1c3 N003 ( 7, 8) [000123] ------------ +--* MUL float $1c1 N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 $481 N006 ( 7, 8) [000130] ------------ \--* MUL float $1c2 N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 $483 --------- ***** BB04, STMT00035(before) N007 ( 15, 16) [000162] -A------R--- * ASG float N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 N005 ( 15, 16) [000140] ------------ \--* MUL float N003 ( 9, 10) [000136] ------------ +--* MUL float N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 N001 [000135] LCL_VAR V25 tmp11 => $485 {485} N002 [000132] CNS_DBL 2.0000000000000000 => $101 {FltCns[2.000000]} N003 [000136] MUL => $1c4 {MUL($101, $485)} N004 [000139] LCL_VAR V26 tmp12 => $486 {486} N005 [000140] MUL => $1c5 {MUL($1c4, $486)} N006 [000161] LCL_VAR V17 tmp3 d:2 => $1c5 {MUL($1c4, $486)} N007 [000162] ASG => $1c5 {MUL($1c4, $486)} ***** BB04, STMT00035(after) N007 ( 15, 16) [000162] -A------R--- * ASG float $1c5 N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 $1c5 N005 ( 15, 16) [000140] ------------ \--* MUL float $1c5 N003 ( 9, 10) [000136] ------------ +--* MUL float $1c4 N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 $101 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 $486 --------- ***** BB04, STMT00032(before) N003 ( 1, 3) [000153] -A------R--- * ASG float N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) N001 [000151] LCL_VAR V16 tmp2 u:2 (last use) => $1c3 {SUB($1c1, $1c2)} Tree [000153] assigns to non-address-taken local var V27; excluded from SSA, so value not tracked. N003 [000153] ASG => $1c3 {SUB($1c1, $1c2)} ***** BB04, STMT00032(after) N003 ( 1, 3) [000153] -A------R--- * ASG float $1c3 N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) $1c3 --------- ***** BB04, STMT00033(before) N003 ( 1, 3) [000158] -A------R--- * ASG float N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) N001 [000156] LCL_VAR V17 tmp3 u:2 (last use) => $1c5 {MUL($1c4, $486)} Tree [000158] assigns to non-address-taken local var V28; excluded from SSA, so value not tracked. N003 [000158] ASG => $1c5 {MUL($1c4, $486)} ***** BB04, STMT00033(after) N003 ( 1, 3) [000158] -A------R--- * ASG float $1c5 N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) $1c5 --------- ***** BB04, STMT00014(before) N003 ( 7, 9) [000049] -A------R--- * ASG long N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 N001 [000147] LCL_FLD V15 tmp1 [+0] float V15.Real (offs=0x00) -> V27 tmp13 float V15.Imaginary (offs=0x04) -> V28 tmp14 => $4c0 {4c0} N003 [000049] ASG => $4c0 {4c0} ***** BB04, STMT00014(after) N003 ( 7, 9) [000049] -A------R--- * ASG long $4c0 N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 --------- ***** BB04, STMT00038(before) N003 ( 0, 0) [000243] ------------ * COMMA void N001 ( 0, 0) [000239] ------------ +--* NOP void N002 ( 0, 0) [000242] ------------ \--* NOP void N001 [000239] NOP => $500 {500} N002 [000242] NOP => $501 {501} N003 [000243] COMMA => $501 {501} ***** BB04, STMT00038(after) N003 ( 0, 0) [000243] ------------ * COMMA void $501 N001 ( 0, 0) [000239] ------------ +--* NOP void $500 N002 ( 0, 0) [000242] ------------ \--* NOP void $501 --------- ***** BB04, STMT00039(before) N003 ( 0, 0) [000250] ------------ * COMMA void N001 ( 0, 0) [000246] ------------ +--* NOP void N002 ( 0, 0) [000249] ------------ \--* NOP void N001 [000246] NOP => $502 {502} N002 [000249] NOP => $503 {503} N003 [000250] COMMA => $503 {503} ***** BB04, STMT00039(after) N003 ( 0, 0) [000250] ------------ * COMMA void $503 N001 ( 0, 0) [000246] ------------ +--* NOP void $502 N002 ( 0, 0) [000249] ------------ \--* NOP void $503 --------- ***** BB04, STMT00036(before) N007 ( 2, 6) [000257] -A---------- * COMMA void N003 ( 1, 3) [000253] -A------R--- +--* ASG float N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 N006 ( 1, 3) [000256] -A------R--- \--* ASG float N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 N001 [000252] CNS_DBL 0.00000000000000000 => $100 {FltCns[0.000000]} Tree [000253] assigns to non-address-taken local var V33; excluded from SSA, so value not tracked. N003 [000253] ASG => $100 {FltCns[0.000000]} N004 [000255] CNS_DBL 0.00000000000000000 => $100 {FltCns[0.000000]} Tree [000256] assigns to non-address-taken local var V34; excluded from SSA, so value not tracked. N006 [000256] ASG => $100 {FltCns[0.000000]} N007 [000257] COMMA => $100 {FltCns[0.000000]} ***** BB04, STMT00036(after) N007 ( 2, 6) [000257] -A---------- * COMMA void $100 N003 ( 1, 3) [000253] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000256] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 $100 --------- ***** BB04, STMT00040(before) N005 ( 7, 8) [000196] -A------R--- * ASG float N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 N001 [000166] LCL_VAR V25 tmp11 => $488 {488} N002 [000169] LCL_VAR V23 tmp9 u:2 => $201 {PhiDef($9, $3, $1c0)} N003 [000170] ADD => $1c6 {ADD($201, $488)} Tree [000196] assigns to non-address-taken local var V33; excluded from SSA, so value not tracked. N005 [000196] ASG => $1c6 {ADD($201, $488)} ***** BB04, STMT00040(after) N005 ( 7, 8) [000196] -A------R--- * ASG float $1c6 N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float $1c6 N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 $201 --------- ***** BB04, STMT00041(before) N005 ( 7, 8) [000201] -A------R--- * ASG float N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 N001 [000173] LCL_VAR V26 tmp12 => $489 {489} N002 [000176] LCL_VAR V24 tmp10 u:2 => $200 {PhiDef($7, $3, $1c0)} N003 [000177] ADD => $1c7 {ADD($200, $489)} Tree [000201] assigns to non-address-taken local var V34; excluded from SSA, so value not tracked. N005 [000201] ASG => $1c7 {ADD($200, $489)} ***** BB04, STMT00041(after) N005 ( 7, 8) [000201] -A------R--- * ASG float $1c7 N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float $1c7 N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 --------- ***** BB04, STMT00016(before) N003 ( 7, 9) [000061] -A------R--- * ASG long N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 N001 [000184] LCL_FLD V20 tmp6 [+0] float V20.Real (offs=0x00) -> V33 tmp19 float V20.Imaginary (offs=0x04) -> V34 tmp20 => $4c1 {4c1} N003 [000061] ASG => $4c1 {4c1} ***** BB04, STMT00016(after) N003 ( 7, 9) [000061] -A------R--- * ASG long $4c1 N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 --------- ***** BB04, STMT00017(before) N005 ( 3, 3) [000066] -A------R--- * ASG int N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 N003 ( 3, 3) [000064] ------------ \--* ADD int N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 N001 [000062] LCL_VAR V12 loc6 u:3 (last use) => $242 {PhiDef($c, $3, $1c0)} N002 [000063] CNS_INT 1 => $41 {IntCns 1} N003 [000064] ADD => $2c3 {ADD($41, $242)} N004 [000065] LCL_VAR V12 loc6 d:4 => $2c3 {ADD($41, $242)} N005 [000066] ASG => $2c3 {ADD($41, $242)} ***** BB04, STMT00017(after) N005 ( 3, 3) [000066] -A------R--- * ASG int $2c3 N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 $2c3 N003 ( 3, 3) [000064] ------------ \--* ADD int $2c3 N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 $41 --------- ***** BB04, STMT00019(before) N009 ( 19, 20) [000072] -A------R--- * ASG float N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 N007 ( 19, 20) [000217] ------------ \--* ADD float N003 ( 7, 8) [000209] ------------ +--* MUL float N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 N006 ( 7, 8) [000216] ------------ \--* MUL float N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 N001 [000205] LCL_VAR V25 tmp11 => $48a {48a} N002 [000208] LCL_VAR V25 tmp11 => $48b {48b} N003 [000209] MUL => $1c8 {MUL($48a, $48b)} N004 [000212] LCL_VAR V26 tmp12 => $48c {48c} N005 [000215] LCL_VAR V26 tmp12 => $48d {48d} N006 [000216] MUL => $1c9 {MUL($48c, $48d)} N007 [000217] ADD => $1ca {ADD($1c8, $1c9)} N008 [000071] LCL_VAR V13 loc7 d:2 => $1ca {ADD($1c8, $1c9)} N009 [000072] ASG => $1ca {ADD($1c8, $1c9)} ***** BB04, STMT00019(after) N009 ( 19, 20) [000072] -A------R--- * ASG float $1ca N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 $1ca N007 ( 19, 20) [000217] ------------ \--* ADD float $1ca N003 ( 7, 8) [000209] ------------ +--* MUL float $1c8 N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 $48b N006 ( 7, 8) [000216] ------------ \--* MUL float $1c9 N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 $48d --------- ***** BB04, STMT00020(before) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 N001 [000073] LCL_VAR V13 loc7 u:2 (last use) => $1ca {ADD($1c8, $1c9)} N002 [000074] CNS_DBL 4.0000000000000000 => $102 {FltCns[4.000000]} N003 [000075] GE => $2c4 {GE_UN($1ca, $102)} ***** BB04, STMT00020(after) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int $2c4 N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 $102 finish(BB04). Succ(BB05). Not yet completed. All preds complete, adding to allDone. Succ(BB06). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB05 is $3c0 {3c0} The SSA definition for GcHeap (#5) at start of BB05 is $3c0 {3c0} ***** BB05, STMT00025(before) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 N001 [000094] LCL_VAR V12 loc6 u:4 => $2c3 {ADD($41, $242)} N002 [000095] CNS_INT 0x3E8 => $47 {IntCns 0x3E8} N003 [000096] LT => $2c5 {LT($2c3, $47)} ***** BB05, STMT00025(after) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int $2c5 N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 $47 finish(BB05). Succ(BB06). Not yet completed. All preds complete, adding to allDone. Succ(BB04). The SSA definition for ByrefExposed (#5) at start of BB06 is $3c0 {3c0} The SSA definition for GcHeap (#5) at start of BB06 is $3c0 {3c0} ***** BB06, STMT00022(before) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) N001 [000260] ARGPLACE => $3c1 {3c1} N002 [000261] ARGPLACE => $441 {441} N003 [000262] ARGPLACE => $442 {442} N004 [000263] ARGPLACE => $443 {443} N005 [000077] LCL_VAR V00 this u:1 => $80 {InitVal($40)} N006 [000258] CNS_INT 16 field offset Fseq[_drawPixel] => $580 {LngCns: 16} N007 [000259] ADD => $5c0 {ADD($80, $580)} VNApplySelectors: VNForHandle(_drawPixel) is $600, fieldType is ref VNForMapSelect($3c0, $600):ref returns $640 {$3c0[$600]} VNForMapSelect($640, $80):ref returns $641 {$640[$80]} N008 [000219] IND => N009 [000080] LCL_VAR V08 loc2 u:3 => $241 {PhiDef($8, $3, $1c0)} N010 [000081] LCL_VAR V06 loc0 u:3 => $240 {PhiDef($6, $3, $1c0)} N011 [000082] LCL_VAR V12 loc6 u:4 (last use) => $2c3 {ADD($41, $242)} VN of ARGPLACE tree [000261] updated to VN of ARGPLACE tree [000262] updated to $241 {PhiDef($8, $3, $1c0)} VN of ARGPLACE tree [000263] updated to $240 {PhiDef($6, $3, $1c0)} fgCurMemoryVN[GcHeap] assigned for CALL at [000083] to VN: $3c3. N012 [000083] CALL => $VN.Void ***** BB06, STMT00022(after) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref $5c0 N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] $580 N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) $2c3 --------- ***** BB06, STMT00023(before) N005 ( 7, 8) [000088] -A------R--- * ASG float N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 N003 ( 7, 8) [000086] ------------ \--* ADD float N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 N001 [000084] LCL_VAR V09 loc3 u:3 (last use) => $201 {PhiDef($9, $3, $1c0)} N002 [000085] LCL_VAR V05 arg5 u:1 => $c4 {InitVal($45)} N003 [000086] ADD => $1cb {ADD($c4, $201)} N004 [000087] LCL_VAR V09 loc3 d:4 => $1cb {ADD($c4, $201)} N005 [000088] ASG => $1cb {ADD($c4, $201)} ***** BB06, STMT00023(after) N005 ( 7, 8) [000088] -A------R--- * ASG float $1cb N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 $1cb N003 ( 7, 8) [000086] ------------ \--* ADD float $1cb N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 --------- ***** BB06, STMT00024(before) N005 ( 3, 3) [000093] -A------R--- * ASG int N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 N003 ( 3, 3) [000091] ------------ \--* ADD int N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 N001 [000089] LCL_VAR V08 loc2 u:3 (last use) => $241 {PhiDef($8, $3, $1c0)} N002 [000090] CNS_INT 1 => $41 {IntCns 1} N003 [000091] ADD => $2c6 {ADD($41, $241)} N004 [000092] LCL_VAR V08 loc2 d:4 => $2c6 {ADD($41, $241)} N005 [000093] ASG => $2c6 {ADD($41, $241)} ***** BB06, STMT00024(after) N005 ( 3, 3) [000093] -A------R--- * ASG int $2c6 N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 $2c6 N003 ( 3, 3) [000091] ------------ \--* ADD int $2c6 N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 $41 --------- ***** BB06, STMT00008(before) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 N001 [000023] LCL_VAR V09 loc3 u:4 => $1cb {ADD($c4, $201)} N002 [000024] LCL_VAR V02 arg2 u:1 => $c1 {InitVal($42)} N003 [000025] LT => $2c7 {LT($1cb, $c1)} ***** BB06, STMT00008(after) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int $2c7 N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 finish(BB06). Succ(BB07). Not yet completed. All preds complete, adding to allDone. Succ(BB03). Building phi application: $48 = SSA# 6. Building phi application: $43 = SSA# 3. Building phi application: $645 = phi($43, $48). The SSA definition for GcHeap (#4) at start of BB07 is $646 {PhiMemoryDef($601, $645)} ***** BB07, STMT00026(before) N005 ( 7, 8) [000102] -A------R--- * ASG float N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 N003 ( 7, 8) [000100] ------------ \--* ADD float N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 N001 [000098] LCL_VAR V07 loc1 u:3 (last use) => $200 {PhiDef($7, $3, $1c0)} N002 [000099] LCL_VAR V05 arg5 u:1 => $c4 {InitVal($45)} N003 [000100] ADD => $1cc {ADD($c4, $200)} N004 [000101] LCL_VAR V07 loc1 d:4 => $1cc {ADD($c4, $200)} N005 [000102] ASG => $1cc {ADD($c4, $200)} ***** BB07, STMT00026(after) N005 ( 7, 8) [000102] -A------R--- * ASG float $1cc N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 $1cc N003 ( 7, 8) [000100] ------------ \--* ADD float $1cc N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 --------- ***** BB07, STMT00027(before) N005 ( 3, 3) [000107] -A------R--- * ASG int N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 N003 ( 3, 3) [000105] ------------ \--* ADD int N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 N001 [000103] LCL_VAR V06 loc0 u:3 (last use) => $240 {PhiDef($6, $3, $1c0)} N002 [000104] CNS_INT 1 => $41 {IntCns 1} N003 [000105] ADD => $2c8 {ADD($41, $240)} N004 [000106] LCL_VAR V06 loc0 d:4 => $2c8 {ADD($41, $240)} N005 [000107] ASG => $2c8 {ADD($41, $240)} ***** BB07, STMT00027(after) N005 ( 3, 3) [000107] -A------R--- * ASG int $2c8 N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 $2c8 N003 ( 3, 3) [000105] ------------ \--* ADD int $2c8 N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 $41 finish(BB07). Succ(BB08). *************** In optHoistLoopCode() Blocks/Trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int $40 N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 $40 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float $c2 N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 $c2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) $c2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int $40 N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 $40 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float $c0 N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 $c0 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 $c0 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int $2c2 N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V09 loc3 u:2 $c0 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00046 (IL ???... ???) N005 ( 0, 0) [000280] -A------R--- * ASG float N004 ( 0, 0) [000278] D------N---- +--* LCL_VAR float V09 loc3 d:3 N003 ( 0, 0) [000279] ------------ \--* PHI float N001 ( 0, 0) [000291] ------------ pred BB06 +--* PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ pred BB02 \--* PHI_ARG float V09 loc3 u:2 $c0 ***** BB03 STMT00045 (IL ???... ???) N005 ( 0, 0) [000277] -A------R--- * ASG int N004 ( 0, 0) [000275] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000276] ------------ \--* PHI int N001 ( 0, 0) [000292] ------------ pred BB06 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ pred BB02 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float $201 N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 $201 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 $201 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float $200 N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 $200 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 $200 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void $200 N003 ( 1, 3) [000225] -A------R--- +--* ASG float $201 N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 $201 N006 ( 1, 3) [000228] -A------R--- \--* ASG float $200 N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int $40 N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 $40 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00047 (IL ???... ???) N005 ( 0, 0) [000283] -A------R--- * ASG int N004 ( 0, 0) [000281] D------N---- +--* LCL_VAR int V12 loc6 d:3 N003 ( 0, 0) [000282] ------------ \--* PHI int N001 ( 0, 0) [000293] ------------ pred BB05 +--* PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ pred BB03 \--* PHI_ARG int V12 loc6 u:2 $40 ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void $100 N003 ( 1, 3) [000232] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000235] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float $1c3 N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 $1c3 N007 ( 19, 20) [000131] ------------ \--* SUB float $1c3 N003 ( 7, 8) [000123] ------------ +--* MUL float $1c1 N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 $481 N006 ( 7, 8) [000130] ------------ \--* MUL float $1c2 N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 $483 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float $1c5 N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 $1c5 N005 ( 15, 16) [000140] ------------ \--* MUL float $1c5 N003 ( 9, 10) [000136] ------------ +--* MUL float $1c4 N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 $101 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 $486 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float $1c3 N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) $1c3 ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float $1c5 N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) $1c5 ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long $4c0 N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 ***** BB04 STMT00038 (IL 0x02C... ???) N003 ( 0, 0) [000243] ------------ * COMMA void $501 N001 ( 0, 0) [000239] ------------ +--* NOP void $500 N002 ( 0, 0) [000242] ------------ \--* NOP void $501 ***** BB04 STMT00039 (IL 0x02C... ???) N003 ( 0, 0) [000250] ------------ * COMMA void $503 N001 ( 0, 0) [000246] ------------ +--* NOP void $502 N002 ( 0, 0) [000249] ------------ \--* NOP void $503 ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void $100 N003 ( 1, 3) [000253] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000256] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float $1c6 N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float $1c6 N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 $201 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float $1c7 N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float $1c7 N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long $4c1 N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int $2c3 N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 $2c3 N003 ( 3, 3) [000064] ------------ \--* ADD int $2c3 N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float $1ca N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 $1ca N007 ( 19, 20) [000217] ------------ \--* ADD float $1ca N003 ( 7, 8) [000209] ------------ +--* MUL float $1c8 N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 $48b N006 ( 7, 8) [000216] ------------ \--* MUL float $1c9 N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 $48d ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int $2c4 N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 $102 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int $2c5 N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 $47 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref $5c0 N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] $580 N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) $2c3 ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float $1cb N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 $1cb N003 ( 7, 8) [000086] ------------ \--* ADD float $1cb N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int $2c6 N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 $2c6 N003 ( 3, 3) [000091] ------------ \--* ADD int $2c6 N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 $41 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int $2c7 N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float $1cc N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 $1cc N003 ( 7, 8) [000100] ------------ \--* ADD float $1cc N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int $2c8 N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 $2c8 N003 ( 3, 3) [000105] ------------ \--* ADD int $2c8 N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 $41 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00044 (IL ???... ???) N005 ( 0, 0) [000274] -A------R--- * ASG float N004 ( 0, 0) [000272] D------N---- +--* LCL_VAR float V07 loc1 d:3 N003 ( 0, 0) [000273] ------------ \--* PHI float N001 ( 0, 0) [000288] ------------ pred BB07 +--* PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ pred BB01 \--* PHI_ARG float V07 loc1 u:2 $c2 ***** BB08 STMT00043 (IL ???... ???) N005 ( 0, 0) [000271] -A------R--- * ASG int N004 ( 0, 0) [000269] D------N---- +--* LCL_VAR int V06 loc0 d:3 N003 ( 0, 0) [000270] ------------ \--* PHI int N001 ( 0, 0) [000289] ------------ pred BB07 +--* PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ pred BB01 \--* PHI_ARG int V06 loc0 u:2 $40 ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int $2c0 N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 $c3 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int $2c1 N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort $300 N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 $80 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void $380 ------------------------------------------------------------------------------------------------------------------- optHoistLoopCode for loop L01 : Loop body contains a call USEDEF (17)={V12 V08 V00 V06 V16 V17 V23 V24 V13 V29 V30 V31 V32 V09 V07 V02 V05} INOUT (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} LOOPVARS(10)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05} INOUT-FP(8)={V23 V24 V09 V07 V02 V05 V04 V01} LOOPV-FP(6)={V23 V24 V09 V07 V02 V05} optHoistLoopBlocks BB03 (weight= 16 ) of loop L01 , firstBlock is true optHoistLoopBlocks BB04 (weight=128 ) of loop L01 , firstBlock is false optHoistLoopBlocks BB06 (weight= 16 ) of loop L01 , firstBlock is false optHoistLoopCode for loop L02 : Loop body does not contain a call USEDEF (10)={V12 V16 V17 V23 V24 V13 V29 V30 V31 V32} INOUT (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V04 V01} LOOPVARS(3)={V12 V23 V24} INOUT-FP(8)={V23 V24 V09 V07 V02 V05 V04 V01} LOOPV-FP(2)={V23 V24} optHoistLoopBlocks BB04 (weight=128 ) of loop L02 , firstBlock is true *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V06} Live vars: {V00 V01 V02 V03 V04 V05 V06} => {V00 V01 V02 V04 V05 V06} Live vars: {V00 V01 V02 V04 V05 V06} => {V00 V01 V02 V04 V05 V06 V07} Copy Assertion for BB08 curSsaName stack: { 3-[000003]:V03 6-[000001]:V06 7-[000004]:V07 } Copy Assertion for BB10 curSsaName stack: { 3-[000003]:V03 4-[000007]:V04 6-[000269]:V06 7-[000272]:V07 } Copy Assertion for BB09 curSsaName stack: { 3-[000003]:V03 4-[000007]:V04 6-[000269]:V06 7-[000272]:V07 } Copy Assertion for BB02 curSsaName stack: { 0-[000011]:V00 3-[000003]:V03 4-[000007]:V04 6-[000269]:V06 7-[000272]:V07 } Live vars: {V00 V01 V02 V04 V05 V06 V07} => {V00 V01 V02 V04 V05 V06 V07 V08} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} VN based copy assertion for [000266] V09 @000000C0 by [000020] V01 @000000C0. N001 ( 1, 2) [000266] ------------ * LCL_VAR float V09 loc3 u:2 $c0 copy propagated to: N001 ( 1, 2) [000266] ------------ * LCL_VAR float V01 arg1 u:1 $c0 Copy Assertion for BB07 curSsaName stack: { 0-[000011]:V00 1-[000020]:V01 2-[000267]:V02 3-[000003]:V03 4-[000007]:V04 6-[000269]:V06 7-[000272]:V07 8-[000018]:V08 9-[000021]:V09 } Live vars: {V00 V01 V02 V04 V05 V06 V07} => {V00 V01 V02 V04 V05 V06} Live vars: {V00 V01 V02 V04 V05 V06} => {V00 V01 V02 V04 V05 V06 V07} Live vars: {V00 V01 V02 V04 V05 V06 V07} => {V00 V01 V02 V04 V05 V07} Live vars: {V00 V01 V02 V04 V05 V07} => {V00 V01 V02 V04 V05 V06 V07} Copy Assertion for BB03 curSsaName stack: { 0-[000011]:V00 1-[000020]:V01 2-[000267]:V02 3-[000003]:V03 4-[000007]:V04 5-[000099]:V05 6-[000269]:V06 7-[000272]:V07 8-[000018]:V08 9-[000021]:V09 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Copy Assertion for BB04 curSsaName stack: { 23-[000110]:V23 0-[000011]:V00 24-[000114]:V24 1-[000020]:V01 2-[000267]:V02 3-[000003]:V03 4-[000007]:V04 5-[000099]:V05 6-[000269]:V06 7-[000272]:V07 8-[000275]:V08 9-[000278]:V09 12-[000037]:V12 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V17 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V17 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V17 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V17 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V13 V23 V24} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V13 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Copy Assertion for BB06 curSsaName stack: { 23-[000110]:V23 0-[000011]:V00 24-[000114]:V24 1-[000020]:V01 2-[000267]:V02 3-[000003]:V03 4-[000007]:V04 5-[000099]:V05 6-[000269]:V06 7-[000272]:V07 8-[000275]:V08 9-[000278]:V09 12-[000065]:V12 13-[000071]:V13 16-[000159]:V16 17-[000161]:V17 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V04 V05 V06 V07 V08} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V04 V05 V06 V07 V09} Live vars: {V00 V01 V02 V04 V05 V06 V07 V09} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} Copy Assertion for BB05 curSsaName stack: { 23-[000110]:V23 0-[000011]:V00 24-[000114]:V24 1-[000020]:V01 2-[000267]:V02 3-[000003]:V03 4-[000007]:V04 5-[000099]:V05 6-[000269]:V06 7-[000272]:V07 8-[000275]:V08 9-[000278]:V09 12-[000065]:V12 13-[000071]:V13 16-[000159]:V16 17-[000161]:V17 } *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int $40 N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 $40 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float $c2 N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 $c2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) $c2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int $40 N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 $40 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float $c0 N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 $c0 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 $c0 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int $2c2 N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00046 (IL ???... ???) N005 ( 0, 0) [000280] -A------R--- * ASG float N004 ( 0, 0) [000278] D------N---- +--* LCL_VAR float V09 loc3 d:3 N003 ( 0, 0) [000279] ------------ \--* PHI float N001 ( 0, 0) [000291] ------------ pred BB06 +--* PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ pred BB02 \--* PHI_ARG float V09 loc3 u:2 $c0 ***** BB03 STMT00045 (IL ???... ???) N005 ( 0, 0) [000277] -A------R--- * ASG int N004 ( 0, 0) [000275] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000276] ------------ \--* PHI int N001 ( 0, 0) [000292] ------------ pred BB06 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ pred BB02 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float $201 N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 $201 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 $201 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float $200 N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 $200 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 $200 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void $200 N003 ( 1, 3) [000225] -A------R--- +--* ASG float $201 N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 $201 N006 ( 1, 3) [000228] -A------R--- \--* ASG float $200 N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int $40 N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 $40 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00047 (IL ???... ???) N005 ( 0, 0) [000283] -A------R--- * ASG int N004 ( 0, 0) [000281] D------N---- +--* LCL_VAR int V12 loc6 d:3 N003 ( 0, 0) [000282] ------------ \--* PHI int N001 ( 0, 0) [000293] ------------ pred BB05 +--* PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ pred BB03 \--* PHI_ARG int V12 loc6 u:2 $40 ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void $100 N003 ( 1, 3) [000232] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000235] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float $1c3 N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 $1c3 N007 ( 19, 20) [000131] ------------ \--* SUB float $1c3 N003 ( 7, 8) [000123] ------------ +--* MUL float $1c1 N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 $481 N006 ( 7, 8) [000130] ------------ \--* MUL float $1c2 N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 $483 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float $1c5 N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 $1c5 N005 ( 15, 16) [000140] ------------ \--* MUL float $1c5 N003 ( 9, 10) [000136] ------------ +--* MUL float $1c4 N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 $101 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 $486 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float $1c3 N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) $1c3 ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float $1c5 N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) $1c5 ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long $4c0 N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 ***** BB04 STMT00038 (IL 0x02C... ???) N003 ( 0, 0) [000243] ------------ * COMMA void $501 N001 ( 0, 0) [000239] ------------ +--* NOP void $500 N002 ( 0, 0) [000242] ------------ \--* NOP void $501 ***** BB04 STMT00039 (IL 0x02C... ???) N003 ( 0, 0) [000250] ------------ * COMMA void $503 N001 ( 0, 0) [000246] ------------ +--* NOP void $502 N002 ( 0, 0) [000249] ------------ \--* NOP void $503 ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void $100 N003 ( 1, 3) [000253] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000256] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float $1c6 N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float $1c6 N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 $201 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float $1c7 N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float $1c7 N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long $4c1 N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int $2c3 N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 $2c3 N003 ( 3, 3) [000064] ------------ \--* ADD int $2c3 N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float $1ca N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 $1ca N007 ( 19, 20) [000217] ------------ \--* ADD float $1ca N003 ( 7, 8) [000209] ------------ +--* MUL float $1c8 N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 $48b N006 ( 7, 8) [000216] ------------ \--* MUL float $1c9 N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 $48d ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int $2c4 N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 $102 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int $2c5 N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 $47 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref $5c0 N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] $580 N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) $2c3 ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float $1cb N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 $1cb N003 ( 7, 8) [000086] ------------ \--* ADD float $1cb N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int $2c6 N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 $2c6 N003 ( 3, 3) [000091] ------------ \--* ADD int $2c6 N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 $41 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int $2c7 N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float $1cc N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 $1cc N003 ( 7, 8) [000100] ------------ \--* ADD float $1cc N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int $2c8 N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 $2c8 N003 ( 3, 3) [000105] ------------ \--* ADD int $2c8 N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 $41 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00044 (IL ???... ???) N005 ( 0, 0) [000274] -A------R--- * ASG float N004 ( 0, 0) [000272] D------N---- +--* LCL_VAR float V07 loc1 d:3 N003 ( 0, 0) [000273] ------------ \--* PHI float N001 ( 0, 0) [000288] ------------ pred BB07 +--* PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ pred BB01 \--* PHI_ARG float V07 loc1 u:2 $c2 ***** BB08 STMT00043 (IL ???... ???) N005 ( 0, 0) [000271] -A------R--- * ASG int N004 ( 0, 0) [000269] D------N---- +--* LCL_VAR int V06 loc0 d:3 N003 ( 0, 0) [000270] ------------ \--* PHI int N001 ( 0, 0) [000289] ------------ pred BB07 +--* PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ pred BB01 \--* PHI_ARG int V06 loc0 u:2 $40 ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int $2c0 N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 $c3 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int $2c1 N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort $300 N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 $80 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int $40 N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 $40 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float $c2 N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 $c2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) $c2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int $40 N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 $40 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float $c0 N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 $c0 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 $c0 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int $2c2 N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00046 (IL ???... ???) N005 ( 0, 0) [000280] -A------R--- * ASG float N004 ( 0, 0) [000278] D------N---- +--* LCL_VAR float V09 loc3 d:3 N003 ( 0, 0) [000279] ------------ \--* PHI float N001 ( 0, 0) [000291] ------------ pred BB06 +--* PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ pred BB02 \--* PHI_ARG float V09 loc3 u:2 $c0 ***** BB03 STMT00045 (IL ???... ???) N005 ( 0, 0) [000277] -A------R--- * ASG int N004 ( 0, 0) [000275] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000276] ------------ \--* PHI int N001 ( 0, 0) [000292] ------------ pred BB06 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ pred BB02 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float $201 N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 $201 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 $201 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float $200 N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 $200 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 $200 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void $200 N003 ( 1, 3) [000225] -A------R--- +--* ASG float $201 N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 $201 N006 ( 1, 3) [000228] -A------R--- \--* ASG float $200 N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int $40 N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 $40 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00047 (IL ???... ???) N005 ( 0, 0) [000283] -A------R--- * ASG int N004 ( 0, 0) [000281] D------N---- +--* LCL_VAR int V12 loc6 d:3 N003 ( 0, 0) [000282] ------------ \--* PHI int N001 ( 0, 0) [000293] ------------ pred BB05 +--* PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ pred BB03 \--* PHI_ARG int V12 loc6 u:2 $40 ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void $100 N003 ( 1, 3) [000232] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000235] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float $1c3 N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 $1c3 N007 ( 19, 20) [000131] ------------ \--* SUB float $1c3 N003 ( 7, 8) [000123] ------------ +--* MUL float $1c1 N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 $481 N006 ( 7, 8) [000130] ------------ \--* MUL float $1c2 N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 $483 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float $1c5 N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 $1c5 N005 ( 15, 16) [000140] ------------ \--* MUL float $1c5 N003 ( 9, 10) [000136] ------------ +--* MUL float $1c4 N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 $101 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 $486 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float $1c3 N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) $1c3 ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float $1c5 N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) $1c5 ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long $4c0 N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 ***** BB04 STMT00038 (IL 0x02C... ???) N003 ( 0, 0) [000243] ------------ * COMMA void $501 N001 ( 0, 0) [000239] ------------ +--* NOP void $500 N002 ( 0, 0) [000242] ------------ \--* NOP void $501 ***** BB04 STMT00039 (IL 0x02C... ???) N003 ( 0, 0) [000250] ------------ * COMMA void $503 N001 ( 0, 0) [000246] ------------ +--* NOP void $502 N002 ( 0, 0) [000249] ------------ \--* NOP void $503 ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void $100 N003 ( 1, 3) [000253] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000256] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float $1c6 N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float $1c6 N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 $201 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float $1c7 N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float $1c7 N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long $4c1 N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int $2c3 N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 $2c3 N003 ( 3, 3) [000064] ------------ \--* ADD int $2c3 N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float $1ca N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 $1ca N007 ( 19, 20) [000217] ------------ \--* ADD float $1ca N003 ( 7, 8) [000209] ------------ +--* MUL float $1c8 N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 $48b N006 ( 7, 8) [000216] ------------ \--* MUL float $1c9 N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 $48d ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int $2c4 N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 $102 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int $2c5 N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 $47 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref $5c0 N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] $580 N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) $2c3 ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float $1cb N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 $1cb N003 ( 7, 8) [000086] ------------ \--* ADD float $1cb N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int $2c6 N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 $2c6 N003 ( 3, 3) [000091] ------------ \--* ADD int $2c6 N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 $41 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int $2c7 N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float $1cc N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 $1cc N003 ( 7, 8) [000100] ------------ \--* ADD float $1cc N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int $2c8 N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 $2c8 N003 ( 3, 3) [000105] ------------ \--* ADD int $2c8 N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 $41 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00044 (IL ???... ???) N005 ( 0, 0) [000274] -A------R--- * ASG float N004 ( 0, 0) [000272] D------N---- +--* LCL_VAR float V07 loc1 d:3 N003 ( 0, 0) [000273] ------------ \--* PHI float N001 ( 0, 0) [000288] ------------ pred BB07 +--* PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ pred BB01 \--* PHI_ARG float V07 loc1 u:2 $c2 ***** BB08 STMT00043 (IL ???... ???) N005 ( 0, 0) [000271] -A------R--- * ASG int N004 ( 0, 0) [000269] D------N---- +--* LCL_VAR int V06 loc0 d:3 N003 ( 0, 0) [000270] ------------ \--* PHI int N001 ( 0, 0) [000289] ------------ pred BB07 +--* PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ pred BB01 \--* PHI_ARG int V06 loc0 u:2 $40 ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int $2c0 N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 $c3 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int $2c1 N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort $300 N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 $80 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void $380 ------------------------------------------------------------------------------------------------------------------- GenTreeNode creates assertion: N004 ( 5, 8) [000097] ------------ * JTRUE void In BB05 New Global Constant Assertion: (709, 64) ($2c5,$40) Const_Loop_Bnd {LT($2c3, $47)} is not {IntCns 0} index=#01, mask=0000000000000001 GenTreeNode creates assertion: N004 ( 5, 8) [000097] ------------ * JTRUE void In BB05 New Global Constant Assertion: (709, 64) ($2c5,$40) Const_Loop_Bnd {LT($2c3, $47)} is {IntCns 0} index=#02, mask=0000000000000002 GenTreeNode creates assertion: N008 ( 4, 4) [000219] ---XG------- * IND ref In BB06 New Global Constant Assertion: (128, 0) ($80,$0) V00.01 != null index=#03, mask=0000000000000004 BB01 valueGen = 0000000000000000 BB02 valueGen = 0000000000000000 => BB07 valueGen = 0000000000000000, BB03 valueGen = 0000000000000000 BB04 valueGen = 0000000000000000 => BB06 valueGen = 0000000000000000, BB05 valueGen = 0000000000000002 => BB04 valueGen = 0000000000000001, BB06 valueGen = 0000000000000004 => BB03 valueGen = 0000000000000004, BB07 valueGen = 0000000000000000 BB08 valueGen = 0000000000000000 => BB10 valueGen = 0000000000000000, BB09 valueGen = 0000000000000000 => BB02 valueGen = 0000000000000000, BB10 valueGen = 0000000000000000 AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 AssertionPropCallback::Changed : BB01 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB08 in -> 0000000000000007 AssertionPropCallback::Merge : BB08 in -> 0000000000000007, predBlock BB01 out -> 0000000000000000 AssertionPropCallback::Merge : BB08 in -> 0000000000000000, predBlock BB07 out -> 0000000000000007 AssertionPropCallback::EndMerge : BB08 in -> 0000000000000000 AssertionPropCallback::Changed : BB08 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB09 in -> 0000000000000007 AssertionPropCallback::Merge : BB09 in -> 0000000000000007, predBlock BB08 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB09 in -> 0000000000000000 AssertionPropCallback::Changed : BB09 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB10 in -> 0000000000000007 AssertionPropCallback::Merge : BB10 in -> 0000000000000007, predBlock BB08 out -> 0000000000000000 AssertionPropCallback::Merge : BB10 in -> 0000000000000000, predBlock BB09 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB10 in -> 0000000000000000 AssertionPropCallback::Changed : BB10 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB10 in -> 0000000000000000 AssertionPropCallback::Merge : BB10 in -> 0000000000000000, predBlock BB08 out -> 0000000000000000 AssertionPropCallback::Merge : BB10 in -> 0000000000000000, predBlock BB09 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB10 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB10 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB02 in -> 0000000000000007 AssertionPropCallback::Merge : BB02 in -> 0000000000000007, predBlock BB09 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB02 in -> 0000000000000000 AssertionPropCallback::Changed : BB02 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB03 in -> 0000000000000007 AssertionPropCallback::Merge : BB03 in -> 0000000000000007, predBlock BB02 out -> 0000000000000000 AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000 AssertionPropCallback::Changed : BB03 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB07 in -> 0000000000000007 AssertionPropCallback::Merge : BB07 in -> 0000000000000007, predBlock BB02 out -> 0000000000000000 AssertionPropCallback::Merge : BB07 in -> 0000000000000000, predBlock BB06 out -> 0000000000000007 AssertionPropCallback::EndMerge : BB07 in -> 0000000000000000 AssertionPropCallback::Changed : BB07 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB04 in -> 0000000000000007 AssertionPropCallback::Merge : BB04 in -> 0000000000000007, predBlock BB03 out -> 0000000000000000 AssertionPropCallback::Merge : BB04 in -> 0000000000000000, predBlock BB05 out -> 0000000000000007 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000000 AssertionPropCallback::Changed : BB04 before out -> 0000000000000007; after out -> 0000000000000000; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB08 in -> 0000000000000000 AssertionPropCallback::Merge : BB08 in -> 0000000000000000, predBlock BB01 out -> 0000000000000000 AssertionPropCallback::Merge : BB08 in -> 0000000000000000, predBlock BB07 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB08 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB08 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB05 in -> 0000000000000007 AssertionPropCallback::Merge : BB05 in -> 0000000000000007, predBlock BB04 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB05 in -> 0000000000000000 AssertionPropCallback::Changed : BB05 before out -> 0000000000000007; after out -> 0000000000000002; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000001; AssertionPropCallback::StartMerge: BB06 in -> 0000000000000007 AssertionPropCallback::Merge : BB06 in -> 0000000000000007, predBlock BB04 out -> 0000000000000000 AssertionPropCallback::Merge : BB06 in -> 0000000000000000, predBlock BB05 out -> 0000000000000002 AssertionPropCallback::EndMerge : BB06 in -> 0000000000000000 AssertionPropCallback::Changed : BB06 before out -> 0000000000000007; after out -> 0000000000000004; jumpDest before out -> 0000000000000007; jumpDest after out -> 0000000000000004; AssertionPropCallback::StartMerge: BB06 in -> 0000000000000000 AssertionPropCallback::Merge : BB06 in -> 0000000000000000, predBlock BB04 out -> 0000000000000000 AssertionPropCallback::Merge : BB06 in -> 0000000000000000, predBlock BB05 out -> 0000000000000002 AssertionPropCallback::EndMerge : BB06 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB06 out -> 0000000000000004; jumpDest out -> 0000000000000004 AssertionPropCallback::StartMerge: BB04 in -> 0000000000000000 AssertionPropCallback::Merge : BB04 in -> 0000000000000000, predBlock BB03 out -> 0000000000000000 AssertionPropCallback::Merge : BB04 in -> 0000000000000000, predBlock BB05 out -> 0000000000000002 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB04 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB07 in -> 0000000000000000 AssertionPropCallback::Merge : BB07 in -> 0000000000000000, predBlock BB02 out -> 0000000000000000 AssertionPropCallback::Merge : BB07 in -> 0000000000000000, predBlock BB06 out -> 0000000000000004 AssertionPropCallback::EndMerge : BB07 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB07 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB03 in -> 0000000000000000 AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB02 out -> 0000000000000000 AssertionPropCallback::Merge : BB03 in -> 0000000000000000, predBlock BB06 out -> 0000000000000004 AssertionPropCallback::EndMerge : BB03 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB03 out -> 0000000000000000; jumpDest out -> 0000000000000000 BB01 valueIn = 0000000000000000 valueOut = 0000000000000000 BB02 valueIn = 0000000000000000 valueOut = 0000000000000000 => BB07 valueOut= 0000000000000000 BB03 valueIn = 0000000000000000 valueOut = 0000000000000000 BB04 valueIn = 0000000000000000 valueOut = 0000000000000000 => BB06 valueOut= 0000000000000000 BB05 valueIn = 0000000000000000 valueOut = 0000000000000002 => BB04 valueOut= 0000000000000001 BB06 valueIn = 0000000000000000 valueOut = 0000000000000004 => BB03 valueOut= 0000000000000004 BB07 valueIn = 0000000000000000 valueOut = 0000000000000000 BB08 valueIn = 0000000000000000 valueOut = 0000000000000000 => BB10 valueOut= 0000000000000000 BB09 valueIn = 0000000000000000 valueOut = 0000000000000000 => BB02 valueOut= 0000000000000000 BB10 valueIn = 0000000000000000 valueOut = 0000000000000000 Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000000], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000001], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00000, tree [000002], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000003], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000004], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt STMT00001, tree [000005], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00006, tree [000017], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00006, tree [000018], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00006, tree [000019], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00007, tree [000020], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00007, tree [000021], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00007, tree [000022], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00042, tree [000266], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00042, tree [000267], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00042, tree [000265], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt STMT00042, tree [000268], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00028, tree [000029], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00028, tree [000110], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00028, tree [000111], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00029, tree [000030], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00029, tree [000114], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00029, tree [000115], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000224], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000223], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000225], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000227], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000226], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000228], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00010, tree [000229], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00011, tree [000036], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00011, tree [000037], tree -> 0 Propagating 0000000000000000 assertions for BB03, stmt STMT00011, tree [000038], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000231], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000230], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000232], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000234], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000233], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000235], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00030, tree [000236], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000119], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000122], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000123], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000126], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000129], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000130], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000131], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000159], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00034, tree [000160], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000135], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000132], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000136], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000139], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000140], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000161], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00035, tree [000162], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00032, tree [000151], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00032, tree [000152], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00032, tree [000153], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00033, tree [000156], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00033, tree [000157], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00033, tree [000158], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00014, tree [000147], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00014, tree [000046], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00014, tree [000049], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00038, tree [000239], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00038, tree [000242], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00038, tree [000243], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00039, tree [000246], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00039, tree [000249], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00039, tree [000250], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000252], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000251], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000253], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000255], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000254], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000256], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00036, tree [000257], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00040, tree [000166], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00040, tree [000169], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00040, tree [000170], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00040, tree [000195], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00040, tree [000196], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00041, tree [000173], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00041, tree [000176], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00041, tree [000177], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00041, tree [000200], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00041, tree [000201], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00016, tree [000184], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00016, tree [000058], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00016, tree [000061], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00017, tree [000062], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00017, tree [000063], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00017, tree [000064], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00017, tree [000065], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00017, tree [000066], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000205], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000208], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000209], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000212], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000215], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000216], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000217], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000071], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00019, tree [000072], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00020, tree [000073], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00020, tree [000074], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00020, tree [000075], tree -> 0 Propagating 0000000000000000 assertions for BB04, stmt STMT00020, tree [000076], tree -> 0 Propagating 0000000000000000 assertions for BB05, stmt STMT00025, tree [000094], tree -> 0 Propagating 0000000000000000 assertions for BB05, stmt STMT00025, tree [000095], tree -> 0 Propagating 0000000000000000 assertions for BB05, stmt STMT00025, tree [000096], tree -> 0 Propagating 0000000000000000 assertions for BB05, stmt STMT00025, tree [000097], tree -> 1 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000260], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000261], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000262], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000263], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000077], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000258], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000259], tree -> 0 Propagating 0000000000000000 assertions for BB06, stmt STMT00022, tree [000219], tree -> 3 Propagating 0000000000000004 assertions for BB06, stmt STMT00022, tree [000080], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00022, tree [000081], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00022, tree [000082], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00022, tree [000083], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00023, tree [000084], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00023, tree [000085], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00023, tree [000086], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00023, tree [000087], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00023, tree [000088], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00024, tree [000089], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00024, tree [000090], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00024, tree [000091], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00024, tree [000092], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00024, tree [000093], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00008, tree [000023], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00008, tree [000024], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00008, tree [000025], tree -> 0 Propagating 0000000000000004 assertions for BB06, stmt STMT00008, tree [000026], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00026, tree [000098], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00026, tree [000099], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00026, tree [000100], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00026, tree [000101], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00026, tree [000102], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00027, tree [000103], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00027, tree [000104], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00027, tree [000105], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00027, tree [000106], tree -> 0 Propagating 0000000000000000 assertions for BB07, stmt STMT00027, tree [000107], tree -> 0 Propagating 0000000000000000 assertions for BB08, stmt STMT00002, tree [000006], tree -> 0 Propagating 0000000000000000 assertions for BB08, stmt STMT00002, tree [000007], tree -> 0 Propagating 0000000000000000 assertions for BB08, stmt STMT00002, tree [000008], tree -> 0 Propagating 0000000000000000 assertions for BB08, stmt STMT00002, tree [000009], tree -> 0 Propagating 0000000000000000 assertions for BB09, stmt STMT00005, tree [000264], tree -> 0 Propagating 0000000000000000 assertions for BB09, stmt STMT00005, tree [000011], tree -> 0 Propagating 0000000000000000 assertions for BB09, stmt STMT00005, tree [000012], tree -> 0 Propagating 0000000000000000 assertions for BB09, stmt STMT00005, tree [000014], tree -> 0 Propagating 0000000000000000 assertions for BB09, stmt STMT00005, tree [000015], tree -> 0 Propagating 0000000000000000 assertions for BB09, stmt STMT00005, tree [000016], tree -> 0 Propagating 0000000000000000 assertions for BB10, stmt STMT00003, tree [000010], tree -> 0 *************** In fgDebugCheckBBlist *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int $40 N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 $40 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float $c2 N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 $c2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) $c2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int $40 N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 $40 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float $c0 N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 $c0 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 $c0 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int $2c2 N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00046 (IL ???... ???) N005 ( 0, 0) [000280] -A------R--- * ASG float N004 ( 0, 0) [000278] D------N---- +--* LCL_VAR float V09 loc3 d:3 N003 ( 0, 0) [000279] ------------ \--* PHI float N001 ( 0, 0) [000291] ------------ pred BB06 +--* PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ pred BB02 \--* PHI_ARG float V09 loc3 u:2 $c0 ***** BB03 STMT00045 (IL ???... ???) N005 ( 0, 0) [000277] -A------R--- * ASG int N004 ( 0, 0) [000275] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000276] ------------ \--* PHI int N001 ( 0, 0) [000292] ------------ pred BB06 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ pred BB02 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float $201 N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 $201 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 $201 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float $200 N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 $200 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 $200 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void $200 N003 ( 1, 3) [000225] -A------R--- +--* ASG float $201 N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 $201 N006 ( 1, 3) [000228] -A------R--- \--* ASG float $200 N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int $40 N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 $40 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00047 (IL ???... ???) N005 ( 0, 0) [000283] -A------R--- * ASG int N004 ( 0, 0) [000281] D------N---- +--* LCL_VAR int V12 loc6 d:3 N003 ( 0, 0) [000282] ------------ \--* PHI int N001 ( 0, 0) [000293] ------------ pred BB05 +--* PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ pred BB03 \--* PHI_ARG int V12 loc6 u:2 $40 ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void $100 N003 ( 1, 3) [000232] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000235] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float $1c3 N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 $1c3 N007 ( 19, 20) [000131] ------------ \--* SUB float $1c3 N003 ( 7, 8) [000123] ------------ +--* MUL float $1c1 N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 $481 N006 ( 7, 8) [000130] ------------ \--* MUL float $1c2 N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 $483 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float $1c5 N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 $1c5 N005 ( 15, 16) [000140] ------------ \--* MUL float $1c5 N003 ( 9, 10) [000136] ------------ +--* MUL float $1c4 N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 $101 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 $486 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float $1c3 N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) $1c3 ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float $1c5 N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) $1c5 ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long $4c0 N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 ***** BB04 STMT00038 (IL 0x02C... ???) N003 ( 0, 0) [000243] ------------ * COMMA void $501 N001 ( 0, 0) [000239] ------------ +--* NOP void $500 N002 ( 0, 0) [000242] ------------ \--* NOP void $501 ***** BB04 STMT00039 (IL 0x02C... ???) N003 ( 0, 0) [000250] ------------ * COMMA void $503 N001 ( 0, 0) [000246] ------------ +--* NOP void $502 N002 ( 0, 0) [000249] ------------ \--* NOP void $503 ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void $100 N003 ( 1, 3) [000253] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000256] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float $1c6 N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float $1c6 N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 $201 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float $1c7 N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float $1c7 N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long $4c1 N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int $2c3 N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 $2c3 N003 ( 3, 3) [000064] ------------ \--* ADD int $2c3 N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float $1ca N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 $1ca N007 ( 19, 20) [000217] ------------ \--* ADD float $1ca N003 ( 7, 8) [000209] ------------ +--* MUL float $1c8 N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 $48b N006 ( 7, 8) [000216] ------------ \--* MUL float $1c9 N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 $48d ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int $2c4 N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 $102 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int $2c5 N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 $47 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref $5c0 N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] $580 N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) $2c3 ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float $1cb N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 $1cb N003 ( 7, 8) [000086] ------------ \--* ADD float $1cb N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int $2c6 N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 $2c6 N003 ( 3, 3) [000091] ------------ \--* ADD int $2c6 N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 $41 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int $2c7 N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float $1cc N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 $1cc N003 ( 7, 8) [000100] ------------ \--* ADD float $1cc N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int $2c8 N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 $2c8 N003 ( 3, 3) [000105] ------------ \--* ADD int $2c8 N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 $41 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00044 (IL ???... ???) N005 ( 0, 0) [000274] -A------R--- * ASG float N004 ( 0, 0) [000272] D------N---- +--* LCL_VAR float V07 loc1 d:3 N003 ( 0, 0) [000273] ------------ \--* PHI float N001 ( 0, 0) [000288] ------------ pred BB07 +--* PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ pred BB01 \--* PHI_ARG float V07 loc1 u:2 $c2 ***** BB08 STMT00043 (IL ???... ???) N005 ( 0, 0) [000271] -A------R--- * ASG int N004 ( 0, 0) [000269] D------N---- +--* LCL_VAR int V06 loc0 d:3 N003 ( 0, 0) [000270] ------------ \--* PHI int N001 ( 0, 0) [000289] ------------ pred BB07 +--* PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ pred BB01 \--* PHI_ARG int V06 loc0 u:2 $40 ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int $2c0 N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 $c3 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int $2c1 N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort $300 N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 $80 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** In IR Rationalize Trees before IR Rationalize ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ***** BB01 STMT00000 (IL 0x000...0x001) N003 ( 1, 3) [000002] -A------R--- * ASG int $40 N002 ( 1, 1) [000001] D------N---- +--* LCL_VAR int V06 loc0 d:2 $40 N001 ( 1, 1) [000000] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00001 (IL 0x002...0x003) N003 ( 1, 3) [000005] -A------R--- * ASG float $c2 N002 ( 1, 2) [000004] D------N---- +--* LCL_VAR float V07 loc1 d:2 $c2 N001 ( 1, 2) [000003] ------------ \--* LCL_VAR float V03 arg3 u:1 (last use) $c2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ***** BB02 STMT00006 (IL 0x006...0x007) N003 ( 1, 3) [000019] -A------R--- * ASG int $40 N002 ( 1, 1) [000018] D------N---- +--* LCL_VAR int V08 loc2 d:2 $40 N001 ( 1, 1) [000017] ------------ \--* CNS_INT int 0 $40 ***** BB02 STMT00007 (IL 0x008...0x009) N003 ( 1, 3) [000022] -A------R--- * ASG float $c0 N002 ( 1, 2) [000021] D------N---- +--* LCL_VAR float V09 loc3 d:2 $c0 N001 ( 1, 2) [000020] ------------ \--* LCL_VAR float V01 arg1 u:1 $c0 ***** BB02 STMT00042 (IL 0x070... ???) N004 ( 5, 7) [000268] ------------ * JTRUE void N003 ( 3, 5) [000265] N------N---- \--* GE int $2c2 N001 ( 1, 2) [000266] ------------ +--* LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} ***** BB03 STMT00046 (IL ???... ???) N005 ( 0, 0) [000280] -A------R--- * ASG float N004 ( 0, 0) [000278] D------N---- +--* LCL_VAR float V09 loc3 d:3 N003 ( 0, 0) [000279] ------------ \--* PHI float N001 ( 0, 0) [000291] ------------ pred BB06 +--* PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ pred BB02 \--* PHI_ARG float V09 loc3 u:2 $c0 ***** BB03 STMT00045 (IL ???... ???) N005 ( 0, 0) [000277] -A------R--- * ASG int N004 ( 0, 0) [000275] D------N---- +--* LCL_VAR int V08 loc2 d:3 N003 ( 0, 0) [000276] ------------ \--* PHI int N001 ( 0, 0) [000292] ------------ pred BB06 +--* PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ pred BB02 \--* PHI_ARG int V08 loc2 u:2 $40 ***** BB03 STMT00028 (IL 0x00C... ???) N003 ( 1, 3) [000111] -A------R--- * ASG float $201 N002 ( 1, 2) [000110] D------N---- +--* LCL_VAR float V23 tmp9 d:2 $201 N001 ( 1, 2) [000029] ------------ \--* LCL_VAR float V09 loc3 u:3 $201 ***** BB03 STMT00029 (IL 0x00C... ???) N003 ( 1, 3) [000115] -A------R--- * ASG float $200 N002 ( 1, 2) [000114] D------N---- +--* LCL_VAR float V24 tmp10 d:2 $200 N001 ( 1, 2) [000030] ------------ \--* LCL_VAR float V07 loc1 u:3 $200 ***** BB03 STMT00010 (IL 0x015... ???) N007 ( 2, 6) [000229] -A---------- * COMMA void $200 N003 ( 1, 3) [000225] -A------R--- +--* ASG float $201 N002 ( 1, 2) [000223] D------N---- | +--* LCL_VAR float V25 tmp11 N001 ( 1, 2) [000224] ------------ | \--* LCL_VAR float V23 tmp9 u:2 $201 N006 ( 1, 3) [000228] -A------R--- \--* ASG float $200 N005 ( 1, 2) [000226] D------N---- +--* LCL_VAR float V26 tmp12 N004 ( 1, 2) [000227] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB03 STMT00011 (IL 0x019...0x01A) N003 ( 1, 3) [000038] -A------R--- * ASG int $40 N002 ( 1, 1) [000037] D------N---- +--* LCL_VAR int V12 loc6 d:2 $40 N001 ( 1, 1) [000036] ------------ \--* CNS_INT int 0 $40 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ***** BB04 STMT00047 (IL ???... ???) N005 ( 0, 0) [000283] -A------R--- * ASG int N004 ( 0, 0) [000281] D------N---- +--* LCL_VAR int V12 loc6 d:3 N003 ( 0, 0) [000282] ------------ \--* PHI int N001 ( 0, 0) [000293] ------------ pred BB05 +--* PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ pred BB03 \--* PHI_ARG int V12 loc6 u:2 $40 ***** BB04 STMT00030 (IL 0x023... ???) N007 ( 2, 6) [000236] -A---------- * COMMA void $100 N003 ( 1, 3) [000232] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000230] D------N---- | +--* LCL_VAR float V27 tmp13 N001 ( 1, 1) [000231] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000235] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000233] D------N---- +--* LCL_VAR float V28 tmp14 N004 ( 1, 1) [000234] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00034 (IL 0x023... ???) N009 ( 19, 20) [000160] -A------R--- * ASG float $1c3 N008 ( 1, 2) [000159] D------N---- +--* LCL_VAR float V16 tmp2 d:2 $1c3 N007 ( 19, 20) [000131] ------------ \--* SUB float $1c3 N003 ( 7, 8) [000123] ------------ +--* MUL float $1c1 N001 ( 1, 2) [000119] ------------ | +--* LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ | \--* LCL_VAR float V25 tmp11 $481 N006 ( 7, 8) [000130] ------------ \--* MUL float $1c2 N004 ( 1, 2) [000126] ------------ +--* LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ \--* LCL_VAR float V26 tmp12 $483 ***** BB04 STMT00035 (IL 0x023... ???) N007 ( 15, 16) [000162] -A------R--- * ASG float $1c5 N006 ( 1, 2) [000161] D------N---- +--* LCL_VAR float V17 tmp3 d:2 $1c5 N005 ( 15, 16) [000140] ------------ \--* MUL float $1c5 N003 ( 9, 10) [000136] ------------ +--* MUL float $1c4 N001 ( 1, 2) [000135] ------------ | +--* LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ | \--* CNS_DBL float 2.0000000000000000 $101 N004 ( 1, 2) [000139] ------------ \--* LCL_VAR float V26 tmp12 $486 ***** BB04 STMT00032 (IL 0x023... ???) N003 ( 1, 3) [000153] -A------R--- * ASG float $1c3 N002 ( 1, 2) [000152] D------N---- +--* LCL_VAR float V27 tmp13 N001 ( 1, 2) [000151] ------------ \--* LCL_VAR float V16 tmp2 u:2 (last use) $1c3 ***** BB04 STMT00033 (IL 0x023... ???) N003 ( 1, 3) [000158] -A------R--- * ASG float $1c5 N002 ( 1, 2) [000157] D------N---- +--* LCL_VAR float V28 tmp14 N001 ( 1, 2) [000156] ------------ \--* LCL_VAR float V17 tmp3 u:2 (last use) $1c5 ***** BB04 STMT00014 (IL ???... ???) N003 ( 7, 9) [000049] -A------R--- * ASG long $4c0 N002 ( 3, 4) [000046] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000147] ------------ \--* LCL_FLD long V15 tmp1 [+0] \--* float V15.Real (offs=0x00) -> V27 tmp13 \--* float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 ***** BB04 STMT00038 (IL 0x02C... ???) N003 ( 0, 0) [000243] ------------ * COMMA void $501 N001 ( 0, 0) [000239] ------------ +--* NOP void $500 N002 ( 0, 0) [000242] ------------ \--* NOP void $501 ***** BB04 STMT00039 (IL 0x02C... ???) N003 ( 0, 0) [000250] ------------ * COMMA void $503 N001 ( 0, 0) [000246] ------------ +--* NOP void $502 N002 ( 0, 0) [000249] ------------ \--* NOP void $503 ***** BB04 STMT00036 (IL 0x02C... ???) N007 ( 2, 6) [000257] -A---------- * COMMA void $100 N003 ( 1, 3) [000253] -A------R--- +--* ASG float $100 N002 ( 1, 2) [000251] D------N---- | +--* LCL_VAR float V33 tmp19 N001 ( 1, 1) [000252] ------------ | \--* CNS_DBL float 0.00000000000000000 $100 N006 ( 1, 3) [000256] -A------R--- \--* ASG float $100 N005 ( 1, 2) [000254] D------N---- +--* LCL_VAR float V34 tmp20 N004 ( 1, 1) [000255] ------------ \--* CNS_DBL float 0.00000000000000000 $100 ***** BB04 STMT00040 (IL 0x02C... ???) N005 ( 7, 8) [000196] -A------R--- * ASG float $1c6 N004 ( 1, 2) [000195] D------N---- +--* LCL_VAR float V33 tmp19 N003 ( 7, 8) [000170] ------------ \--* ADD float $1c6 N001 ( 1, 2) [000166] ------------ +--* LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ \--* LCL_VAR float V23 tmp9 u:2 $201 ***** BB04 STMT00041 (IL 0x02C... ???) N005 ( 7, 8) [000201] -A------R--- * ASG float $1c7 N004 ( 1, 2) [000200] D------N---- +--* LCL_VAR float V34 tmp20 N003 ( 7, 8) [000177] ------------ \--* ADD float $1c7 N001 ( 1, 2) [000173] ------------ +--* LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ \--* LCL_VAR float V24 tmp10 u:2 $200 ***** BB04 STMT00016 (IL ???... ???) N003 ( 7, 9) [000061] -A------R--- * ASG long $4c1 N002 ( 3, 4) [000058] D------N---- +--* LCL_FLD long V11 loc5 [+0] +--* float V11.Real (offs=0x00) -> V25 tmp11 +--* float V11.Imaginary (offs=0x04) -> V26 tmp12 N001 ( 3, 4) [000184] ------------ \--* LCL_FLD long V20 tmp6 [+0] \--* float V20.Real (offs=0x00) -> V33 tmp19 \--* float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 ***** BB04 STMT00017 (IL 0x037...0x03B) N005 ( 3, 3) [000066] -A------R--- * ASG int $2c3 N004 ( 1, 1) [000065] D------N---- +--* LCL_VAR int V12 loc6 d:4 $2c3 N003 ( 3, 3) [000064] ------------ \--* ADD int $2c3 N001 ( 1, 1) [000062] ------------ +--* LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ \--* CNS_INT int 1 $41 ***** BB04 STMT00019 (IL ???... ???) N009 ( 19, 20) [000072] -A------R--- * ASG float $1ca N008 ( 1, 2) [000071] D------N---- +--* LCL_VAR float V13 loc7 d:2 $1ca N007 ( 19, 20) [000217] ------------ \--* ADD float $1ca N003 ( 7, 8) [000209] ------------ +--* MUL float $1c8 N001 ( 1, 2) [000205] ------------ | +--* LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ | \--* LCL_VAR float V25 tmp11 $48b N006 ( 7, 8) [000216] ------------ \--* MUL float $1c9 N004 ( 1, 2) [000212] ------------ +--* LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ \--* LCL_VAR float V26 tmp12 $48d ***** BB04 STMT00020 (IL 0x046...0x04D) N004 ( 7, 9) [000076] ------------ * JTRUE void N003 ( 5, 7) [000075] N------N-U-- \--* GE int $2c4 N001 ( 1, 2) [000073] ------------ +--* LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ \--* CNS_DBL float 4.0000000000000000 $102 ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ***** BB05 STMT00025 (IL 0x04F...0x056) N004 ( 5, 8) [000097] ------------ * JTRUE void N003 ( 3, 6) [000096] J------N---- \--* LT int $2c5 N001 ( 1, 1) [000094] ------------ +--* LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ \--* CNS_INT int 0x3E8 $47 ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ***** BB06 STMT00022 (IL ???... ???) N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void N008 ( 4, 4) [000219] ---XG------- this in rcx +--* IND ref N007 ( 2, 2) [000259] -------N---- | \--* ADD byref $5c0 N005 ( 1, 1) [000077] ------------ | +--* LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ | \--* CNS_INT long 16 field offset Fseq[_drawPixel] $580 N009 ( 1, 1) [000080] ------------ arg1 in rdx +--* LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ arg2 in r8 +--* LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ arg3 in r9 \--* LCL_VAR int V12 loc6 u:4 (last use) $2c3 ***** BB06 STMT00023 (IL 0x067... ???) N005 ( 7, 8) [000088] -A------R--- * ASG float $1cb N004 ( 1, 2) [000087] D------N---- +--* LCL_VAR float V09 loc3 d:4 $1cb N003 ( 7, 8) [000086] ------------ \--* ADD float $1cb N001 ( 1, 2) [000084] ------------ +--* LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB06 STMT00024 (IL 0x06C...0x06F) N005 ( 3, 3) [000093] -A------R--- * ASG int $2c6 N004 ( 1, 1) [000092] D------N---- +--* LCL_VAR int V08 loc2 d:4 $2c6 N003 ( 3, 3) [000091] ------------ \--* ADD int $2c6 N001 ( 1, 1) [000089] ------------ +--* LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ \--* CNS_INT int 1 $41 ***** BB06 STMT00008 (IL 0x070...0x072) N004 ( 5, 7) [000026] ------------ * JTRUE void N003 ( 3, 5) [000025] J------N---- \--* LT int $2c7 N001 ( 1, 2) [000023] ------------ +--* LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ \--* LCL_VAR float V02 arg2 u:1 $c1 ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} ***** BB07 STMT00026 (IL 0x074...0x078) N005 ( 7, 8) [000102] -A------R--- * ASG float $1cc N004 ( 1, 2) [000101] D------N---- +--* LCL_VAR float V07 loc1 d:4 $1cc N003 ( 7, 8) [000100] ------------ \--* ADD float $1cc N001 ( 1, 2) [000098] ------------ +--* LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ \--* LCL_VAR float V05 arg5 u:1 $c4 ***** BB07 STMT00027 (IL 0x079...0x07C) N005 ( 3, 3) [000107] -A------R--- * ASG int $2c8 N004 ( 1, 1) [000106] D------N---- +--* LCL_VAR int V06 loc0 d:4 $2c8 N003 ( 3, 3) [000105] ------------ \--* ADD int $2c8 N001 ( 1, 1) [000103] ------------ +--* LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ \--* CNS_INT int 1 $41 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ***** BB08 STMT00044 (IL ???... ???) N005 ( 0, 0) [000274] -A------R--- * ASG float N004 ( 0, 0) [000272] D------N---- +--* LCL_VAR float V07 loc1 d:3 N003 ( 0, 0) [000273] ------------ \--* PHI float N001 ( 0, 0) [000288] ------------ pred BB07 +--* PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ pred BB01 \--* PHI_ARG float V07 loc1 u:2 $c2 ***** BB08 STMT00043 (IL ???... ???) N005 ( 0, 0) [000271] -A------R--- * ASG int N004 ( 0, 0) [000269] D------N---- +--* LCL_VAR int V06 loc0 d:3 N003 ( 0, 0) [000270] ------------ \--* PHI int N001 ( 0, 0) [000289] ------------ pred BB07 +--* PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ pred BB01 \--* PHI_ARG int V06 loc0 u:2 $40 ***** BB08 STMT00002 (IL 0x07D...0x080) N004 ( 5, 7) [000009] ------------ * JTRUE void N003 ( 3, 5) [000008] N------N-U-- \--* GE int $2c0 N001 ( 1, 2) [000006] ------------ +--* LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ \--* LCL_VAR float V04 arg4 u:1 $c3 ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ***** BB09 STMT00005 (IL ???... ???) N006 ( 19, 12) [000016] --CXG------- * JTRUE void N005 ( 17, 10) [000015] J-CXG--N---- \--* EQ int $2c1 N003 ( 15, 8) [000012] --CXG------- +--* CALL int Algorithms.FractalRenderer.get_Abort $300 N002 ( 1, 1) [000011] ------------ this in rcx | \--* LCL_VAR ref V00 this u:1 $80 N004 ( 1, 1) [000014] ------------ \--* CNS_INT int 0 $40 ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ***** BB10 STMT00003 (IL 0x08D...0x08D) N001 ( 0, 0) [000010] ------------ * RETURN void $380 ------------------------------------------------------------------------------------------------------------------- rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X) N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 rewriting asg(LCL_FLD, X) to STORE_LCL_FLD(X) N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 *************** Exiting IR Rationalize Trees after IR Rationalize ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- t265 = * GE int $2c2 /--* t265 int N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] ------------ t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] ------------ t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] ------------ t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- t75 = * GE int $2c4 /--* t75 int N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- t96 = * LT int $2c5 /--* t96 int N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ t258 = CNS_INT long 16 field offset Fseq[_drawPixel] $580 /--* t77 ref +--* t258 long N007 ( 2, 2) [000259] -------N---- t259 = * ADD byref $5c0 /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t219 ref this in rcx +--* t80 int arg1 in rdx +--* t81 int arg2 in r8 +--* t82 int arg3 in r9 N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- t25 = * LT int $2c7 /--* t25 int N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- t8 = * GE int $2c0 /--* t8 int N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] ------------ t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- t15 = * EQ int $2c1 /--* t15 int N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Bumping outgoingArgSpaceSize to 32 for call [000083] outgoingArgSpaceSize 32 sufficient for call [000012], which needs 32 *************** In fgDebugCheckBBlist *************** In Lowering Trees before Lowering ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- t265 = * GE int $2c2 /--* t265 int N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] ------------ t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] ------------ t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] ------------ t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] ------------ t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] ------------ t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] ------------ t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] ------------ t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] ------------ t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] ------------ t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- t75 = * GE int $2c4 /--* t75 int N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] ------------ t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- t96 = * LT int $2c5 /--* t96 int N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 N006 ( 1, 1) [000258] ------------ t258 = CNS_INT long 16 field offset Fseq[_drawPixel] $580 /--* t77 ref +--* t258 long N007 ( 2, 2) [000259] -------N---- t259 = * ADD byref $5c0 /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t219 ref this in rcx +--* t80 int arg1 in rdx +--* t81 int arg2 in r8 +--* t82 int arg3 in r9 N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] ------------ t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- t25 = * LT int $2c7 /--* t25 int N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] ------------ t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- t8 = * GE int $2c0 /--* t8 int N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] ------------ t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- t15 = * EQ int $2c1 /--* t15 int N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- Addressing mode: Base N005 ( 1, 1) [000077] ------------ * LCL_VAR ref V00 this u:1 $80 + 16 Removing unused node: N006 ( 1, 1) [000258] -c---------- * CNS_INT long 16 field offset Fseq[_drawPixel] $580 New addressing mode node: N007 ( 2, 2) [000259] ------------ * LEA(b+16) byref lowering call (before): N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 /--* t77 ref N007 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t219 ref this in rcx +--* t80 int arg1 in rdx +--* t81 int arg2 in r8 +--* t82 int arg3 in r9 N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000260] ----------L- * ARGPLACE ref $3c1 args: ====== lowering arg : N002 ( 0, 0) [000261] ----------L- * ARGPLACE int lowering arg : N003 ( 0, 0) [000262] ----------L- * ARGPLACE int $241 lowering arg : N004 ( 0, 0) [000263] ----------L- * ARGPLACE int $240 late: ====== lowering arg : N008 ( 4, 4) [000219] ---XG------- * IND ref new node is : [000323] ---XG------- * PUTARG_REG ref REG rcx lowering arg : N009 ( 1, 1) [000080] ------------ * LCL_VAR int V08 loc2 u:3 $241 new node is : [000324] ------------ * PUTARG_REG int REG rdx lowering arg : N010 ( 1, 1) [000081] ------------ * LCL_VAR int V06 loc0 u:3 $240 new node is : [000325] ------------ * PUTARG_REG int REG r8 lowering arg : N011 ( 1, 1) [000082] ------------ * LCL_VAR int V12 loc6 u:4 (last use) $2c3 new node is : [000326] ------------ * PUTARG_REG int REG r9 lvaGrabTemp returning 35 (V35 rat0) called for delegate invoke call. rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 ReplaceWithLclVar created store : [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 results of lowering call: N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 /--* t332 ref N002 ( 4, 3) [000333] ------------ t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] ------------ t334 = * IND long lowering call (after): [000329] ------------ t329 = LCL_VAR ref V35 rat0 /--* t329 ref [000330] -c---------- t330 = * LEA(b+8) byref /--* t330 byref [000331] ------------ t331 = * IND ref /--* t331 ref [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 /--* t80 int [000324] ------------ t324 = * PUTARG_REG int REG rdx N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 /--* t81 int [000325] ------------ t325 = * PUTARG_REG int REG r8 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t82 int [000326] ------------ t326 = * PUTARG_REG int REG r9 N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 /--* t332 ref N002 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void lowering call (before): N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 objp: ====== lowering arg : N001 ( 0, 0) [000264] ----------L- * ARGPLACE ref $281 args: ====== late: ====== lowering arg : N002 ( 1, 1) [000011] ------------ * LCL_VAR ref V00 this u:1 $80 new node is : [000335] ------------ * PUTARG_REG ref REG rcx lowering call (after): N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 lowering GT_RETURN N001 ( 0, 0) [000010] ------------ * RETURN void $380 ============Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- * GE void $2c2 N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- * GE void $2c4 N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- * LT void $2c5 N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 /--* t77 ref N007 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref /--* t219 ref [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 [000329] ------------ t329 = LCL_VAR ref V35 rat0 /--* t329 ref [000330] -c---------- t330 = * LEA(b+8) byref /--* t330 byref [000331] ------------ t331 = * IND ref /--* t331 ref [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 /--* t80 int [000324] ------------ t324 = * PUTARG_REG int REG rdx N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 /--* t81 int [000325] ------------ t325 = * PUTARG_REG int REG r8 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t82 int [000326] ------------ t326 = * PUTARG_REG int REG r9 N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 /--* t332 ref N002 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- * LT void $2c7 N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- * GE void $2c0 N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- * EQ void $2c1 N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V08: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 2, refCntWtd = 18 New refCnts for V23: refCnt = 1, refCntWtd = 16 New refCnts for V07: refCnt = 2, refCntWtd = 17 New refCnts for V24: refCnt = 1, refCntWtd = 16 New refCnts for V23: refCnt = 2, refCntWtd = 32 New refCnts for V11: refCnt = 1, refCntWtd = 16 New refCnts for V25: refCnt = 1, refCntWtd = 16 New refCnts for V24: refCnt = 2, refCntWtd = 32 New refCnts for V11: refCnt = 2, refCntWtd = 32 New refCnts for V26: refCnt = 1, refCntWtd = 16 New refCnts for V12: refCnt = 1, refCntWtd = 16 New refCnts for V15: refCnt = 1, refCntWtd = 256 New refCnts for V27: refCnt = 1, refCntWtd = 128 New refCnts for V15: refCnt = 2, refCntWtd = 512 New refCnts for V28: refCnt = 1, refCntWtd = 128 New refCnts for V11: refCnt = 3, refCntWtd = 160 New refCnts for V25: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 4, refCntWtd = 288 New refCnts for V25: refCnt = 3, refCntWtd = 272 New refCnts for V11: refCnt = 5, refCntWtd = 416 New refCnts for V26: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 6, refCntWtd = 544 New refCnts for V26: refCnt = 3, refCntWtd = 272 New refCnts for V16: refCnt = 1, refCntWtd = 256 New refCnts for V11: refCnt = 7, refCntWtd = 672 New refCnts for V25: refCnt = 4, refCntWtd = 400 New refCnts for V11: refCnt = 8, refCntWtd = 800 New refCnts for V26: refCnt = 4, refCntWtd = 400 New refCnts for V17: refCnt = 1, refCntWtd = 256 New refCnts for V16: refCnt = 2, refCntWtd = 512 New refCnts for V15: refCnt = 3, refCntWtd = 768 New refCnts for V27: refCnt = 2, refCntWtd = 256 New refCnts for V17: refCnt = 2, refCntWtd = 512 New refCnts for V15: refCnt = 4, refCntWtd = 1024 New refCnts for V28: refCnt = 2, refCntWtd = 256 New refCnts for V27: refCnt = 3, refCntWtd = 512 New refCnts for V28: refCnt = 3, refCntWtd = 512 New refCnts for V15: refCnt = 5, refCntWtd = 1280 New refCnts for V25: refCnt = 5, refCntWtd = 528 New refCnts for V26: refCnt = 5, refCntWtd = 528 New refCnts for V11: refCnt = 9, refCntWtd = 928 New refCnts for V20: refCnt = 1, refCntWtd = 256 New refCnts for V33: refCnt = 1, refCntWtd = 128 New refCnts for V20: refCnt = 2, refCntWtd = 512 New refCnts for V34: refCnt = 1, refCntWtd = 128 New refCnts for V11: refCnt = 10, refCntWtd = 1056 New refCnts for V25: refCnt = 6, refCntWtd = 656 New refCnts for V23: refCnt = 3, refCntWtd = 160 New refCnts for V20: refCnt = 3, refCntWtd = 768 New refCnts for V33: refCnt = 2, refCntWtd = 256 New refCnts for V11: refCnt = 11, refCntWtd = 1184 New refCnts for V26: refCnt = 6, refCntWtd = 656 New refCnts for V24: refCnt = 3, refCntWtd = 160 New refCnts for V20: refCnt = 4, refCntWtd = 1024 New refCnts for V34: refCnt = 2, refCntWtd = 256 New refCnts for V33: refCnt = 3, refCntWtd = 512 New refCnts for V34: refCnt = 3, refCntWtd = 512 New refCnts for V20: refCnt = 5, refCntWtd = 1280 New refCnts for V25: refCnt = 7, refCntWtd = 784 New refCnts for V26: refCnt = 7, refCntWtd = 784 New refCnts for V11: refCnt = 12, refCntWtd = 1312 New refCnts for V12: refCnt = 2, refCntWtd = 144 New refCnts for V12: refCnt = 3, refCntWtd = 272 New refCnts for V11: refCnt = 13, refCntWtd = 1440 New refCnts for V25: refCnt = 8, refCntWtd = 912 New refCnts for V11: refCnt = 14, refCntWtd = 1568 New refCnts for V25: refCnt = 9, refCntWtd = 1040 New refCnts for V11: refCnt = 15, refCntWtd = 1696 New refCnts for V26: refCnt = 8, refCntWtd = 912 New refCnts for V11: refCnt = 16, refCntWtd = 1824 New refCnts for V26: refCnt = 9, refCntWtd = 1040 New refCnts for V13: refCnt = 1, refCntWtd = 128 New refCnts for V13: refCnt = 2, refCntWtd = 256 New refCnts for V12: refCnt = 4, refCntWtd = 336 New refCnts for V00: refCnt = 1, refCntWtd = 16 New refCnts for V35: refCnt = 1, refCntWtd = 32 New refCnts for V35: refCnt = 2, refCntWtd = 64 New refCnts for V08: refCnt = 2, refCntWtd = 18 New refCnts for V06: refCnt = 2, refCntWtd = 17 New refCnts for V12: refCnt = 5, refCntWtd = 352 New refCnts for V35: refCnt = 3, refCntWtd = 96 New refCnts for V09: refCnt = 3, refCntWtd = 34 New refCnts for V05: refCnt = 1, refCntWtd = 16 New refCnts for V09: refCnt = 4, refCntWtd = 50 New refCnts for V08: refCnt = 3, refCntWtd = 34 New refCnts for V08: refCnt = 4, refCntWtd = 50 New refCnts for V09: refCnt = 5, refCntWtd = 66 New refCnts for V02: refCnt = 2, refCntWtd = 18 New refCnts for V07: refCnt = 3, refCntWtd = 19 New refCnts for V05: refCnt = 2, refCntWtd = 18 New refCnts for V07: refCnt = 4, refCntWtd = 21 New refCnts for V06: refCnt = 3, refCntWtd = 19 New refCnts for V06: refCnt = 4, refCntWtd = 21 New refCnts for V07: refCnt = 5, refCntWtd = 29 New refCnts for V04: refCnt = 1, refCntWtd = 8 New refCnts for V00: refCnt = 2, refCntWtd = 20 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 21 New refCnts for V00: refCnt = 4, refCntWtd = 22 New refCnts for V01: refCnt = 3, refCntWtd = 5 New refCnts for V01: refCnt = 4, refCntWtd = 6 New refCnts for V02: refCnt = 3, refCntWtd = 19 New refCnts for V02: refCnt = 4, refCntWtd = 20 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 float ; V02 arg2 float ; V03 arg3 float ; V04 arg4 float ; V05 arg5 float ; V06 loc0 int ; V07 loc1 float ; V08 loc2 int ; V09 loc3 float ; V10 loc4 struct ( 8) ld-addr-op ; V11 loc5 struct ( 8) do-not-enreg[SF] ld-addr-op ; V12 loc6 int ; V13 loc7 float ; V14 OutArgs lclBlk (32) "OutgoingArgSpace" ; V15 tmp1 struct ( 8) do-not-enreg[SF] "NewObj constructor temp" ; V16 tmp2 float "Inlining Arg" ; V17 tmp3 float "Inlining Arg" ; V18 tmp4 struct ( 8) "Inlining Arg" ; V19 tmp5 struct ( 8) "Inlining Arg" ; V20 tmp6 struct ( 8) do-not-enreg[SF] "NewObj constructor temp" ; V21 tmp7 float "Inlining Arg" ; V22 tmp8 float "Inlining Arg" ; V23 tmp9 float V10.Real(offs=0x00) P-INDEP "field V10.Real (fldOffset=0x0)" ; V24 tmp10 float V10.Imaginary(offs=0x04) P-INDEP "field V10.Imaginary (fldOffset=0x4)" ; V25 tmp11 float do-not-enreg[] V11.Real(offs=0x00) P-DEP "field V11.Real (fldOffset=0x0)" ; V26 tmp12 float do-not-enreg[] V11.Imaginary(offs=0x04) P-DEP "field V11.Imaginary (fldOffset=0x4)" ; V27 tmp13 float do-not-enreg[] V15.Real(offs=0x00) P-DEP "field V15.Real (fldOffset=0x0)" ; V28 tmp14 float do-not-enreg[] V15.Imaginary(offs=0x04) P-DEP "field V15.Imaginary (fldOffset=0x4)" ; V29 tmp15 float V18.Real(offs=0x00) P-INDEP "field V18.Real (fldOffset=0x0)" ; V30 tmp16 float V18.Imaginary(offs=0x04) P-INDEP "field V18.Imaginary (fldOffset=0x4)" ; V31 tmp17 float V19.Real(offs=0x00) P-INDEP "field V19.Real (fldOffset=0x0)" ; V32 tmp18 float V19.Imaginary(offs=0x04) P-INDEP "field V19.Imaginary (fldOffset=0x4)" ; V33 tmp19 float do-not-enreg[] V20.Real(offs=0x00) P-DEP "field V20.Real (fldOffset=0x0)" ; V34 tmp20 float do-not-enreg[] V20.Imaginary(offs=0x04) P-DEP "field V20.Imaginary (fldOffset=0x4)" ; V35 rat0 ref "delegate invoke call" In fgLocalVarLivenessInit Local V25 should not be enregistered because: field of a dependently promoted struct Local V26 should not be enregistered because: field of a dependently promoted struct Local V27 should not be enregistered because: field of a dependently promoted struct Local V28 should not be enregistered because: field of a dependently promoted struct Local V33 should not be enregistered because: field of a dependently promoted struct Local V34 should not be enregistered because: field of a dependently promoted struct Tracked variable (17 out of 36) table: V12 loc6 [ int]: refCnt = 5, refCntWtd = 352 V35 rat0 [ ref]: refCnt = 3, refCntWtd = 96 V08 loc2 [ int]: refCnt = 4, refCntWtd = 50 V00 this [ ref]: refCnt = 4, refCntWtd = 22 V06 loc0 [ int]: refCnt = 4, refCntWtd = 21 V16 tmp2 [ float]: refCnt = 2, refCntWtd = 512 V17 tmp3 [ float]: refCnt = 2, refCntWtd = 512 V13 loc7 [ float]: refCnt = 2, refCntWtd = 256 V23 tmp9 [ float]: refCnt = 3, refCntWtd = 160 V24 tmp10 [ float]: refCnt = 3, refCntWtd = 160 V09 loc3 [ float]: refCnt = 5, refCntWtd = 66 V07 loc1 [ float]: refCnt = 5, refCntWtd = 29 V02 arg2 [ float]: refCnt = 4, refCntWtd = 20 V05 arg5 [ float]: refCnt = 2, refCntWtd = 18 V01 arg1 [ float]: refCnt = 4, refCntWtd = 6 V04 arg4 [ float]: refCnt = 1, refCntWtd = 8 V03 arg3 [ float]: refCnt = 3, refCntWtd = 3 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={ V03} DEF(2)={V06 V07 } BB02 USE(2)={ V02 V01} DEF(2)={V08 V09 } BB03 USE(2)={ V09 V07} DEF(3)={V12 V23 V24 } BB04 USE(3)={V12 V23 V24} DEF(4)={V12 V16 V17 V13 } BB05 USE(1)={V12} DEF(0)={ } BB06 USE(7)={V12 V08 V00 V06 V09 V02 V05} + ByrefExposed + GcHeap DEF(3)={ V35 V08 V09 } + ByrefExposed* + GcHeap* BB07 USE(3)={V06 V07 V05} DEF(2)={V06 V07 } BB08 USE(2)={V07 V04} DEF(0)={ } BB09 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB10 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (6)={V00 V02 V05 V01 V04 V03} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04 } + ByrefExposed + GcHeap BB02 IN (7)={ V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(9)={V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB03 IN (9)={ V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB04 IN (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB05 IN (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB06 IN (10)={V12 V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(9)={ V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB07 IN (7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB08 IN (7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB09 IN (7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap BB10 IN (0)={} OUT(0)={} *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V08: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 2, refCntWtd = 18 New refCnts for V23: refCnt = 1, refCntWtd = 16 New refCnts for V07: refCnt = 2, refCntWtd = 17 New refCnts for V24: refCnt = 1, refCntWtd = 16 New refCnts for V23: refCnt = 2, refCntWtd = 32 New refCnts for V11: refCnt = 1, refCntWtd = 16 New refCnts for V25: refCnt = 1, refCntWtd = 16 New refCnts for V24: refCnt = 2, refCntWtd = 32 New refCnts for V11: refCnt = 2, refCntWtd = 32 New refCnts for V26: refCnt = 1, refCntWtd = 16 New refCnts for V12: refCnt = 1, refCntWtd = 16 New refCnts for V15: refCnt = 1, refCntWtd = 256 New refCnts for V27: refCnt = 1, refCntWtd = 128 New refCnts for V15: refCnt = 2, refCntWtd = 512 New refCnts for V28: refCnt = 1, refCntWtd = 128 New refCnts for V11: refCnt = 3, refCntWtd = 160 New refCnts for V25: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 4, refCntWtd = 288 New refCnts for V25: refCnt = 3, refCntWtd = 272 New refCnts for V11: refCnt = 5, refCntWtd = 416 New refCnts for V26: refCnt = 2, refCntWtd = 144 New refCnts for V11: refCnt = 6, refCntWtd = 544 New refCnts for V26: refCnt = 3, refCntWtd = 272 New refCnts for V16: refCnt = 1, refCntWtd = 256 New refCnts for V11: refCnt = 7, refCntWtd = 672 New refCnts for V25: refCnt = 4, refCntWtd = 400 New refCnts for V11: refCnt = 8, refCntWtd = 800 New refCnts for V26: refCnt = 4, refCntWtd = 400 New refCnts for V17: refCnt = 1, refCntWtd = 256 New refCnts for V16: refCnt = 2, refCntWtd = 512 New refCnts for V15: refCnt = 3, refCntWtd = 768 New refCnts for V27: refCnt = 2, refCntWtd = 256 New refCnts for V17: refCnt = 2, refCntWtd = 512 New refCnts for V15: refCnt = 4, refCntWtd = 1024 New refCnts for V28: refCnt = 2, refCntWtd = 256 New refCnts for V27: refCnt = 3, refCntWtd = 512 New refCnts for V28: refCnt = 3, refCntWtd = 512 New refCnts for V15: refCnt = 5, refCntWtd = 1280 New refCnts for V25: refCnt = 5, refCntWtd = 528 New refCnts for V26: refCnt = 5, refCntWtd = 528 New refCnts for V11: refCnt = 9, refCntWtd = 928 New refCnts for V20: refCnt = 1, refCntWtd = 256 New refCnts for V33: refCnt = 1, refCntWtd = 128 New refCnts for V20: refCnt = 2, refCntWtd = 512 New refCnts for V34: refCnt = 1, refCntWtd = 128 New refCnts for V11: refCnt = 10, refCntWtd = 1056 New refCnts for V25: refCnt = 6, refCntWtd = 656 New refCnts for V23: refCnt = 3, refCntWtd = 160 New refCnts for V20: refCnt = 3, refCntWtd = 768 New refCnts for V33: refCnt = 2, refCntWtd = 256 New refCnts for V11: refCnt = 11, refCntWtd = 1184 New refCnts for V26: refCnt = 6, refCntWtd = 656 New refCnts for V24: refCnt = 3, refCntWtd = 160 New refCnts for V20: refCnt = 4, refCntWtd = 1024 New refCnts for V34: refCnt = 2, refCntWtd = 256 New refCnts for V33: refCnt = 3, refCntWtd = 512 New refCnts for V34: refCnt = 3, refCntWtd = 512 New refCnts for V20: refCnt = 5, refCntWtd = 1280 New refCnts for V25: refCnt = 7, refCntWtd = 784 New refCnts for V26: refCnt = 7, refCntWtd = 784 New refCnts for V11: refCnt = 12, refCntWtd = 1312 New refCnts for V12: refCnt = 2, refCntWtd = 144 New refCnts for V12: refCnt = 3, refCntWtd = 272 New refCnts for V11: refCnt = 13, refCntWtd = 1440 New refCnts for V25: refCnt = 8, refCntWtd = 912 New refCnts for V11: refCnt = 14, refCntWtd = 1568 New refCnts for V25: refCnt = 9, refCntWtd = 1040 New refCnts for V11: refCnt = 15, refCntWtd = 1696 New refCnts for V26: refCnt = 8, refCntWtd = 912 New refCnts for V11: refCnt = 16, refCntWtd = 1824 New refCnts for V26: refCnt = 9, refCntWtd = 1040 New refCnts for V13: refCnt = 1, refCntWtd = 128 New refCnts for V13: refCnt = 2, refCntWtd = 256 New refCnts for V12: refCnt = 4, refCntWtd = 336 New refCnts for V00: refCnt = 1, refCntWtd = 16 New refCnts for V35: refCnt = 1, refCntWtd = 32 New refCnts for V35: refCnt = 2, refCntWtd = 64 New refCnts for V08: refCnt = 2, refCntWtd = 18 New refCnts for V06: refCnt = 2, refCntWtd = 17 New refCnts for V12: refCnt = 5, refCntWtd = 352 New refCnts for V35: refCnt = 3, refCntWtd = 96 New refCnts for V09: refCnt = 3, refCntWtd = 34 New refCnts for V05: refCnt = 1, refCntWtd = 16 New refCnts for V09: refCnt = 4, refCntWtd = 50 New refCnts for V08: refCnt = 3, refCntWtd = 34 New refCnts for V08: refCnt = 4, refCntWtd = 50 New refCnts for V09: refCnt = 5, refCntWtd = 66 New refCnts for V02: refCnt = 2, refCntWtd = 18 New refCnts for V07: refCnt = 3, refCntWtd = 19 New refCnts for V05: refCnt = 2, refCntWtd = 18 New refCnts for V07: refCnt = 4, refCntWtd = 21 New refCnts for V06: refCnt = 3, refCntWtd = 19 New refCnts for V06: refCnt = 4, refCntWtd = 21 New refCnts for V07: refCnt = 5, refCntWtd = 29 New refCnts for V04: refCnt = 1, refCntWtd = 8 New refCnts for V00: refCnt = 2, refCntWtd = 20 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 21 New refCnts for V00: refCnt = 4, refCntWtd = 22 New refCnts for V01: refCnt = 3, refCntWtd = 5 New refCnts for V01: refCnt = 4, refCntWtd = 6 New refCnts for V02: refCnt = 3, refCntWtd = 19 New refCnts for V02: refCnt = 4, refCntWtd = 20 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 Liveness pass finished after lowering, IR: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- * GE void $2c2 N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- * GE void $2c4 N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- * LT void $2c5 N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 /--* t77 ref N007 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref /--* t219 ref [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 [000329] ------------ t329 = LCL_VAR ref V35 rat0 /--* t329 ref [000330] -c---------- t330 = * LEA(b+8) byref /--* t330 byref [000331] ------------ t331 = * IND ref /--* t331 ref [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 /--* t80 int [000324] ------------ t324 = * PUTARG_REG int REG rdx N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 /--* t81 int [000325] ------------ t325 = * PUTARG_REG int REG r8 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t82 int [000326] ------------ t326 = * PUTARG_REG int REG r9 N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 (last use) /--* t332 ref N002 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- * LT void $2c7 N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- * GE void $2c0 N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- * EQ void $2c1 N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** Exiting Lowering Trees after Lowering ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- * GE void $2c2 N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- * GE void $2c4 N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- * LT void $2c5 N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 /--* t77 ref N007 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref /--* t219 ref [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 [000329] ------------ t329 = LCL_VAR ref V35 rat0 /--* t329 ref [000330] -c---------- t330 = * LEA(b+8) byref /--* t330 byref [000331] ------------ t331 = * IND ref /--* t331 ref [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 /--* t80 int [000324] ------------ t324 = * PUTARG_REG int REG rdx N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 /--* t81 int [000325] ------------ t325 = * PUTARG_REG int REG r8 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t82 int [000326] ------------ t326 = * PUTARG_REG int REG r9 N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 (last use) /--* t332 ref N002 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- * LT void $2c7 N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- * GE void $2c0 N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- * EQ void $2c1 N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In StackLevelSetter Trees before StackLevelSetter ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- * GE void $2c2 N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- * GE void $2c4 N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- * LT void $2c5 N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 /--* t77 ref N007 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref /--* t219 ref [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 [000329] ------------ t329 = LCL_VAR ref V35 rat0 /--* t329 ref [000330] -c---------- t330 = * LEA(b+8) byref /--* t330 byref [000331] ------------ t331 = * IND ref /--* t331 ref [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 /--* t80 int [000324] ------------ t324 = * PUTARG_REG int REG rdx N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 /--* t81 int [000325] ------------ t325 = * PUTARG_REG int REG r8 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t82 int [000326] ------------ t326 = * PUTARG_REG int REG r9 N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 (last use) /--* t332 ref N002 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- * LT void $2c7 N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- * GE void $2c0 N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- * EQ void $2c1 N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** Exiting StackLevelSetter Trees after StackLevelSetter ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} [000294] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 $40 /--* t0 int N003 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 [000295] ------------ IL_OFFSET void IL offset: 0x2 N001 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 (last use) $c2 /--* t3 float N003 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} [000296] ------------ IL_OFFSET void IL offset: 0x6 N001 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 $40 /--* t17 int N003 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 [000297] ------------ IL_OFFSET void IL offset: 0x8 N001 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 $c0 /--* t20 float N003 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 [000298] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 $c0 N002 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 $c1 /--* t266 float +--* t267 float N003 ( 3, 5) [000265] N------N---- * GE void $2c2 N004 ( 5, 7) [000268] ------------ * JTRUE void ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 [000299] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 $201 /--* t29 float N003 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 [000300] ------------ IL_OFFSET void IL offset: 0xc N001 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 $200 /--* t30 float N003 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 [000301] ------------ IL_OFFSET void IL offset: 0x15 N001 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 $201 /--* t224 float N003 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 N004 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 $200 /--* t227 float N006 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 [000302] ------------ IL_OFFSET void IL offset: 0x19 N001 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 $40 /--* t36 int N003 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 [000303] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 $100 /--* t231 float N003 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 N004 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 $100 /--* t234 float N006 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 [000304] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 $480 N002 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 $481 /--* t119 float +--* t122 float N003 ( 7, 8) [000123] ------------ t123 = * MUL float $1c1 N004 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 $482 N005 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 $483 /--* t126 float +--* t129 float N006 ( 7, 8) [000130] ------------ t130 = * MUL float $1c2 /--* t123 float +--* t130 float N007 ( 19, 20) [000131] ------------ t131 = * SUB float $1c3 /--* t131 float N009 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 [000305] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 $485 N002 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 $101 /--* t135 float +--* t132 float N003 ( 9, 10) [000136] ------------ t136 = * MUL float $1c4 N004 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 $486 /--* t136 float +--* t139 float N005 ( 15, 16) [000140] ------------ t140 = * MUL float $1c5 /--* t140 float N007 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 [000306] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 (last use) $1c3 /--* t151 float N003 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 [000307] ------------ IL_OFFSET void IL offset: 0x23 N001 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 (last use) $1c5 /--* t156 float N003 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 N001 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 $4c0 /--* t147 long N003 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000308] ------------ IL_OFFSET void IL offset: 0x2c [000309] ------------ IL_OFFSET void IL offset: 0x2c [000310] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 $100 /--* t252 float N003 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 N004 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 $100 /--* t255 float N006 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 [000311] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 $488 N002 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 $201 /--* t166 float +--* t169 float N003 ( 7, 8) [000170] ------------ t170 = * ADD float $1c6 /--* t170 float N005 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 [000312] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 $489 N002 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 $200 /--* t173 float +--* t176 float N003 ( 7, 8) [000177] ------------ t177 = * ADD float $1c7 /--* t177 float N005 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 N001 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 $4c1 /--* t184 long N003 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 [000313] ------------ IL_OFFSET void IL offset: 0x37 N001 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 (last use) $242 N002 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 $41 /--* t62 int +--* t63 int N003 ( 3, 3) [000064] ------------ t64 = * ADD int $2c3 /--* t64 int N005 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 N001 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 $48a N002 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 $48b /--* t205 float +--* t208 float N003 ( 7, 8) [000209] ------------ t209 = * MUL float $1c8 N004 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 $48c N005 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 $48d /--* t212 float +--* t215 float N006 ( 7, 8) [000216] ------------ t216 = * MUL float $1c9 /--* t209 float +--* t216 float N007 ( 19, 20) [000217] ------------ t217 = * ADD float $1ca /--* t217 float N009 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 [000314] ------------ IL_OFFSET void IL offset: 0x46 N001 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 (last use) $1ca N002 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 $102 /--* t73 float +--* t74 float N003 ( 5, 7) [000075] N------N-U-- * GE void $2c4 N004 ( 7, 9) [000076] ------------ * JTRUE void ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} [000315] ------------ IL_OFFSET void IL offset: 0x4f N001 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 $2c3 N002 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 $47 /--* t94 int +--* t95 int N003 ( 3, 6) [000096] J------N---- * LT void $2c5 N004 ( 5, 8) [000097] ------------ * JTRUE void ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N005 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 $80 /--* t77 ref N007 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref /--* t259 byref N008 ( 4, 4) [000219] ---XG------- t219 = * IND ref /--* t219 ref [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 [000329] ------------ t329 = LCL_VAR ref V35 rat0 /--* t329 ref [000330] -c---------- t330 = * LEA(b+8) byref /--* t330 byref [000331] ------------ t331 = * IND ref /--* t331 ref [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 $241 /--* t80 int [000324] ------------ t324 = * PUTARG_REG int REG rdx N010 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 $240 /--* t81 int [000325] ------------ t325 = * PUTARG_REG int REG r8 N011 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 (last use) $2c3 /--* t82 int [000326] ------------ t326 = * PUTARG_REG int REG r9 N001 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 (last use) /--* t332 ref N002 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref /--* t333 ref N003 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N012 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke $VN.Void [000316] ------------ IL_OFFSET void IL offset: 0x67 N001 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 (last use) $201 N002 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 $c4 /--* t84 float +--* t85 float N003 ( 7, 8) [000086] ------------ t86 = * ADD float $1cb /--* t86 float N005 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 [000317] ------------ IL_OFFSET void IL offset: 0x6c N001 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 (last use) $241 N002 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 $41 /--* t89 int +--* t90 int N003 ( 3, 3) [000091] ------------ t91 = * ADD int $2c6 /--* t91 int N005 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 [000318] ------------ IL_OFFSET void IL offset: 0x70 N001 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 $1cb N002 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 $c1 /--* t23 float +--* t24 float N003 ( 3, 5) [000025] J------N---- * LT void $2c7 N004 ( 5, 7) [000026] ------------ * JTRUE void ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} [000319] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 (last use) $200 N002 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 $c4 /--* t98 float +--* t99 float N003 ( 7, 8) [000100] ------------ t100 = * ADD float $1cc /--* t100 float N005 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 [000320] ------------ IL_OFFSET void IL offset: 0x79 N001 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 (last use) $240 N002 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 $41 /--* t103 int +--* t104 int N003 ( 3, 3) [000105] ------------ t105 = * ADD int $2c8 /--* t105 int N005 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 [000321] ------------ IL_OFFSET void IL offset: 0x7d N001 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 $200 N002 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 $c3 /--* t6 float +--* t7 float N003 ( 3, 5) [000008] N------N-U-- * GE void $2c0 N004 ( 5, 7) [000009] ------------ * JTRUE void ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N002 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 $80 /--* t11 ref [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N003 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort $300 N004 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 $40 /--* t12 int +--* t14 int N005 ( 17, 10) [000015] J--XG--N---- * EQ void $2c1 N006 ( 19, 12) [000016] ---XG------- * JTRUE void ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} [000322] ------------ IL_OFFSET void IL offset: 0x8d N001 ( 0, 0) [000010] ------------ RETURN void $380 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V03} {V06 V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V04 V05 V06 V07} BB02 use def in out {V01 V02} {V08 V09} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07 V08 V09} BB03 use def in out {V07 V09} {V12 V23 V24} {V00 V01 V02 V04 V05 V06 V07 V08 V09} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} BB04 use def in out {V12 V23 V24} {V12 V13 V16 V17} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} BB05 use def in out {V12} {} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} BB06 use def in out {V00 V02 V05 V06 V08 V09 V12} {V08 V09 V35} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12} {V00 V01 V02 V04 V05 V06 V07 V08 V09} BB07 use def in out {V05 V06 V07} {V06 V07} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07} BB08 use def in out {V04 V07} {} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07} BB09 use def in out {V00} {} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07} BB10 use def in out {} {} {} {} Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 2: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 3: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 4: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 5: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 6: int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 8: int RefPositions {} physReg:NA Preferences=[allInt] Interval 9: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 10: int RefPositions {} physReg:NA Preferences=[allInt] Interval 11: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 12: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 13: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 14: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 15: float RefPositions {} physReg:NA Preferences=[allFloat] Interval 16: ref RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: {V01 V02 V04 V05 V07 V09 V13 V16 V17 V23 V24} floatVarCount = 12; hasLoops = 1, singleExit = 1 Adding additional fp callee save candidates: {V03} TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB08( 8 ) BB09( 4 ) BB02( 2 ) BB03( 16 ) BB04(128 ) BB05( 64 ) BB06( 16 ) BB07( 2 ) BB10( 1 ) BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ===== N000. IL_OFFSET IL offset: 0x0 N001. t0 = CNS_INT 0 N003. V06(t2); t0 N000. IL_OFFSET IL offset: 0x2 N001. V03(t3*) N003. V07(t5); t3* BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ===== N000. IL_OFFSET IL offset: 0x7d N001. V07(t6) N002. V04(t7) N003. GE ; t6,t7 N004. JTRUE BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ===== N002. V00(t11) N000. t335 = PUTARG_REG; t11 N003. t12 = CALL ; t335 N004. CNS_INT 0 N005. EQ ; t12 N006. JTRUE BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ===== N000. IL_OFFSET IL offset: 0x6 N001. t17 = CNS_INT 0 N003. V08(t19); t17 N000. IL_OFFSET IL offset: 0x8 N001. V01(t20) N003. V09(t22); t20 N000. IL_OFFSET IL offset: 0x70 N001. V01(t266) N002. V02(t267) N003. GE ; t266,t267 N004. JTRUE BB03 [00C..023), preds={BB02,BB06} succs={BB04} ===== N000. IL_OFFSET IL offset: 0xc N001. V09(t29) N003. V23(t111); t29 N000. IL_OFFSET IL offset: 0xc N001. V07(t30) N003. V24(t115); t30 N000. IL_OFFSET IL offset: 0x15 N001. V23(t224) N003. V25 MEM; t224 N004. V24(t227) N006. V26 MEM; t227 N000. IL_OFFSET IL offset: 0x19 N001. t36 = CNS_INT 0 N003. V12(t38); t36 BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ===== N000. IL_OFFSET IL offset: 0x23 N001. t231 = CNS_DBL 0.00000000000000000 N003. V27 MEM; t231 N004. t234 = CNS_DBL 0.00000000000000000 N006. V28 MEM; t234 N000. IL_OFFSET IL offset: 0x23 N001. t119 = V25 MEM N002. V25 MEM N003. t123 = MUL ; t119 N004. t126 = V26 MEM N005. V26 MEM N006. t130 = MUL ; t126 N007. t131 = SUB ; t123,t130 N009. V16(t160); t131 N000. IL_OFFSET IL offset: 0x23 N001. t135 = V25 MEM N002. CNS_DBL 2.0000000000000000 N003. t136 = MUL ; t135 N004. V26 MEM N005. t140 = MUL ; t136 N007. V17(t162); t140 N000. IL_OFFSET IL offset: 0x23 N001. V16(t151*) N003. V27 MEM; t151* N000. IL_OFFSET IL offset: 0x23 N001. V17(t156*) N003. V28 MEM; t156* N001. t147 = V15 MEM N003. V11 MEM; t147 N000. IL_OFFSET IL offset: 0x2c N000. IL_OFFSET IL offset: 0x2c N000. IL_OFFSET IL offset: 0x2c N001. t252 = CNS_DBL 0.00000000000000000 N003. V33 MEM; t252 N004. t255 = CNS_DBL 0.00000000000000000 N006. V34 MEM; t255 N000. IL_OFFSET IL offset: 0x2c N001. V25 MEM N002. V23(t169) N003. t170 = ADD ; t169 N005. V33 MEM; t170 N000. IL_OFFSET IL offset: 0x2c N001. V26 MEM N002. V24(t176) N003. t177 = ADD ; t176 N005. V34 MEM; t177 N001. t184 = V20 MEM N003. V11 MEM; t184 N000. IL_OFFSET IL offset: 0x37 N001. V12(t62*) N002. CNS_INT 1 N003. t64 = ADD ; t62* N005. V12(t66); t64 N001. t205 = V25 MEM N002. V25 MEM N003. t209 = MUL ; t205 N004. t212 = V26 MEM N005. V26 MEM N006. t216 = MUL ; t212 N007. t217 = ADD ; t209,t216 N009. V13(t72); t217 N000. IL_OFFSET IL offset: 0x46 N001. V13(t73*) N002. t74 = CNS_DBL 4.0000000000000000 N003. GE ; t73*,t74 N004. JTRUE BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ===== N000. IL_OFFSET IL offset: 0x4f N001. V12(t94) N002. CNS_INT 0x3E8 N003. LT ; t94 N004. JTRUE BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ===== N005. V00(t77) N007. t259 = LEA(b+16); t77 N008. t219 = IND ; t259 N000. V35(t328); t219 N000. V35(t329) N000. t330 = LEA(b+8) ; t329 N000. t331 = IND ; t330 N000. t323 = PUTARG_REG; t331 N009. V08(t80) N000. t324 = PUTARG_REG; t80 N010. V06(t81) N000. t325 = PUTARG_REG; t81 N011. V12(t82*) N000. t326 = PUTARG_REG; t82* N001. V35(t332*) N002. t333 = LEA(b+24); t332* N003. t334 = IND ; t333 N012. CALL ; t323,t324,t325,t326,t334 N000. IL_OFFSET IL offset: 0x67 N001. V09(t84*) N002. V05(t85) N003. t86 = ADD ; t84*,t85 N005. V09(t88); t86 N000. IL_OFFSET IL offset: 0x6c N001. V08(t89*) N002. CNS_INT 1 N003. t91 = ADD ; t89* N005. V08(t93); t91 N000. IL_OFFSET IL offset: 0x70 N001. V09(t23) N002. V02(t24) N003. LT ; t23,t24 N004. JTRUE BB07 [074..07D), preds={BB02,BB06} succs={BB08} ===== N000. IL_OFFSET IL offset: 0x74 N001. V07(t98*) N002. V05(t99) N003. t100 = ADD ; t98*,t99 N005. V07(t102); t100 N000. IL_OFFSET IL offset: 0x79 N001. V06(t103*) N002. CNS_INT 1 N003. t105 = ADD ; t103* N005. V06(t107); t105 BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ===== N000. IL_OFFSET IL offset: 0x8d N001. RETURN buildIntervals second part ======== Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> Float arg V02 in reg mm2 BB00 regmask=[mm2] minReg=1 fixed> BB00 regmask=[allFloat] minReg=1> Float arg V01 in reg mm1 BB00 regmask=[mm1] minReg=1 fixed> BB00 regmask=[allFloat] minReg=1> Float arg V03 in reg mm3 BB00 regmask=[mm3] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 (???,???) [000294] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N005 ( 1, 1) [000000] ------------ * CNS_INT int 0 REG NA $40 Interval 17: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N005.t0. CNS_INT } N007 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N009 (???,???) [000295] ------------ * IL_OFFSET void IL offset: 0x2 REG NA DefList: { } N011 ( 1, 2) [000003] ------------ * LCL_VAR float V03 arg3 u:1 NA (last use) REG NA $c2 DefList: { } N013 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 NA REG NA LCL_VAR BB01 regmask=[allFloat] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1 last> CHECKING LAST USES for BB01, liveout={V00 V01 V02 V04 V05 V06 V07} ============================== use: {V03} def: {V06 V07} NEW BLOCK BB08 Setting BB01 as the predecessor for determining incoming variable registers of BB08 DefList: { } N017 (???,???) [000321] ------------ * IL_OFFSET void IL offset: 0x7d REG NA DefList: { } N019 ( 1, 2) [000006] ------------ * LCL_VAR float V07 loc1 u:3 NA REG NA $200 DefList: { } N021 ( 1, 2) [000007] ------------ * LCL_VAR float V04 arg4 u:1 NA REG NA $c3 DefList: { } N023 ( 3, 5) [000008] N------N-U-- * GE void REG NA $2c0 LCL_VAR BB08 regmask=[allFloat] minReg=1 last> LCL_VAR BB08 regmask=[allFloat] minReg=1 last> DefList: { } N025 ( 5, 7) [000009] ------------ * JTRUE void REG NA CHECKING LAST USES for BB08, liveout={V00 V01 V02 V04 V05 V06 V07} ============================== use: {V04 V07} def: {} NEW BLOCK BB09 Setting BB08 as the predecessor for determining incoming variable registers of BB09 DefList: { } N029 ( 1, 1) [000011] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $80 DefList: { } N031 (???,???) [000335] ------------ * PUTARG_REG ref REG rcx BB09 regmask=[rcx] minReg=1> LCL_VAR BB09 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 18: ref RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rcx] minReg=1> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N031.t335. PUTARG_REG } N033 ( 15, 8) [000012] --CXG------- * CALL int Algorithms.FractalRenderer.get_Abort REG NA $300 BB09 regmask=[rcx] minReg=1> BB09 regmask=[rcx] minReg=1 last fixed> BB09 regmask=[rax] minReg=1> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rdx] minReg=1> BB09 regmask=[r8] minReg=1> BB09 regmask=[r9] minReg=1> BB09 regmask=[r10] minReg=1> BB09 regmask=[r11] minReg=1> BB09 regmask=[mm0] minReg=1> BB09 regmask=[mm1] minReg=1> BB09 regmask=[mm2] minReg=1> BB09 regmask=[mm3] minReg=1> BB09 regmask=[mm4] minReg=1> BB09 regmask=[mm5] minReg=1> Interval 19: int RefPositions {} physReg:NA Preferences=[allInt] BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> DefList: { N033.t12. CALL } N035 ( 1, 1) [000014] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { N033.t12. CALL } N037 ( 17, 10) [000015] J--XG--N---- * EQ void REG NA $2c1 BB09 regmask=[allInt] minReg=1 last> DefList: { } N039 ( 19, 12) [000016] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB09, liveout={V00 V01 V02 V04 V05 V06 V07} ============================== use: {V00} def: {} NEW BLOCK BB02 Setting BB09 as the predecessor for determining incoming variable registers of BB02 DefList: { } N043 (???,???) [000296] ------------ * IL_OFFSET void IL offset: 0x6 REG NA DefList: { } N045 ( 1, 1) [000017] ------------ * CNS_INT int 0 REG NA $40 Interval 20: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB02 regmask=[allInt] minReg=1> DefList: { N045.t17. CNS_INT } N047 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 NA REG NA BB02 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N049 (???,???) [000297] ------------ * IL_OFFSET void IL offset: 0x8 REG NA DefList: { } N051 ( 1, 2) [000020] ------------ * LCL_VAR float V01 arg1 u:1 NA REG NA $c0 DefList: { } N053 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 NA REG NA LCL_VAR BB02 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1 last> DefList: { } N055 (???,???) [000298] ------------ * IL_OFFSET void IL offset: 0x70 REG NA DefList: { } N057 ( 1, 2) [000266] ------------ * LCL_VAR float V01 arg1 u:1 NA REG NA $c0 DefList: { } N059 ( 1, 2) [000267] ------------ * LCL_VAR float V02 arg2 u:1 NA REG NA $c1 DefList: { } N061 ( 3, 5) [000265] N------N---- * GE void REG NA $2c2 LCL_VAR BB02 regmask=[allFloat] minReg=1 last> LCL_VAR BB02 regmask=[allFloat] minReg=1 last> DefList: { } N063 ( 5, 7) [000268] ------------ * JTRUE void REG NA CHECKING LAST USES for BB02, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V09} ============================== use: {V01 V02} def: {V08 V09} NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N067 (???,???) [000299] ------------ * IL_OFFSET void IL offset: 0xc REG NA DefList: { } N069 ( 1, 2) [000029] ------------ * LCL_VAR float V09 loc3 u:3 NA REG NA $201 DefList: { } N071 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 NA REG NA LCL_VAR BB03 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1 last> DefList: { } N073 (???,???) [000300] ------------ * IL_OFFSET void IL offset: 0xc REG NA DefList: { } N075 ( 1, 2) [000030] ------------ * LCL_VAR float V07 loc1 u:3 NA REG NA $200 DefList: { } N077 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 NA REG NA LCL_VAR BB03 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1 last> DefList: { } N079 (???,???) [000301] ------------ * IL_OFFSET void IL offset: 0x15 REG NA DefList: { } N081 ( 1, 2) [000224] ------------ * LCL_VAR float V23 tmp9 u:2 NA REG NA $201 DefList: { } N083 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 NA REG NA LCL_VAR BB03 regmask=[allFloat] minReg=1 last> DefList: { } N085 ( 1, 2) [000227] ------------ * LCL_VAR float V24 tmp10 u:2 NA REG NA $200 DefList: { } N087 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 NA REG NA LCL_VAR BB03 regmask=[allFloat] minReg=1 last> DefList: { } N089 (???,???) [000302] ------------ * IL_OFFSET void IL offset: 0x19 REG NA DefList: { } N091 ( 1, 1) [000036] ------------ * CNS_INT int 0 REG NA $40 Interval 21: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB03 regmask=[allInt] minReg=1> DefList: { N091.t36. CNS_INT } N093 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 NA REG NA BB03 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB03 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB03, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} ============================== use: {V07 V09} def: {V12 V23 V24} NEW BLOCK BB04 Setting BB03 as the predecessor for determining incoming variable registers of BB04 DefList: { } N097 (???,???) [000303] ------------ * IL_OFFSET void IL offset: 0x23 REG NA DefList: { } N099 ( 1, 1) [000231] ------------ * CNS_DBL float 0.00000000000000000 REG NA $100 Interval 22: float RefPositions {} physReg:NA Preferences=[allFloat] CNS_DBL BB04 regmask=[allFloat] minReg=1> DefList: { N099.t231. CNS_DBL } N101 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 NA REG NA BB04 regmask=[allFloat] minReg=1 last> DefList: { } N103 ( 1, 1) [000234] ------------ * CNS_DBL float 0.00000000000000000 REG NA $100 Interval 23: float RefPositions {} physReg:NA Preferences=[allFloat] CNS_DBL BB04 regmask=[allFloat] minReg=1> DefList: { N103.t234. CNS_DBL } N105 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 NA REG NA BB04 regmask=[allFloat] minReg=1 last> DefList: { } N107 (???,???) [000304] ------------ * IL_OFFSET void IL offset: 0x23 REG NA DefList: { } N109 ( 1, 2) [000119] ------------ * LCL_VAR float V25 tmp11 NA REG NA $480 Interval 24: float RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB04 regmask=[allFloat] minReg=1> DefList: { N109.t119. LCL_VAR } N111 ( 1, 2) [000122] -c---------- * LCL_VAR float V25 tmp11 NA REG NA $481 Contained DefList: { N109.t119. LCL_VAR } N113 ( 7, 8) [000123] ------------ * MUL float REG NA $1c1 BB04 regmask=[allFloat] minReg=1 last> Interval 25: float RefPositions {} physReg:NA Preferences=[allFloat] MUL BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N113.t123. MUL } N115 ( 1, 2) [000126] ------------ * LCL_VAR float V26 tmp12 NA REG NA $482 Interval 26: float RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB04 regmask=[allFloat] minReg=1> DefList: { N113.t123. MUL; N115.t126. LCL_VAR } N117 ( 1, 2) [000129] -c---------- * LCL_VAR float V26 tmp12 NA REG NA $483 Contained DefList: { N113.t123. MUL; N115.t126. LCL_VAR } N119 ( 7, 8) [000130] ------------ * MUL float REG NA $1c2 BB04 regmask=[allFloat] minReg=1 last> Interval 27: float RefPositions {} physReg:NA Preferences=[allFloat] MUL BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N113.t123. MUL; N119.t130. MUL } N121 ( 19, 20) [000131] ------------ * SUB float REG NA $1c3 BB04 regmask=[allFloat] minReg=1 last> BB04 regmask=[allFloat] minReg=1 last> Interval 28: float RefPositions {} physReg:NA Preferences=[allFloat] SUB BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N121.t131. SUB } N123 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 NA REG NA BB04 regmask=[allFloat] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1 last> DefList: { } N125 (???,???) [000305] ------------ * IL_OFFSET void IL offset: 0x23 REG NA DefList: { } N127 ( 1, 2) [000135] ------------ * LCL_VAR float V25 tmp11 NA REG NA $485 Interval 29: float RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB04 regmask=[allFloat] minReg=1> DefList: { N127.t135. LCL_VAR } N129 ( 3, 4) [000132] -c---------- * CNS_DBL float 2.0000000000000000 REG NA $101 Contained DefList: { N127.t135. LCL_VAR } N131 ( 9, 10) [000136] ------------ * MUL float REG NA $1c4 BB04 regmask=[allFloat] minReg=1 last> Interval 30: float RefPositions {} physReg:NA Preferences=[allFloat] MUL BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N131.t136. MUL } N133 ( 1, 2) [000139] -c---------- * LCL_VAR float V26 tmp12 NA REG NA $486 Contained DefList: { N131.t136. MUL } N135 ( 15, 16) [000140] ------------ * MUL float REG NA $1c5 BB04 regmask=[allFloat] minReg=1 last> Interval 31: float RefPositions {} physReg:NA Preferences=[allFloat] MUL BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N135.t140. MUL } N137 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 NA REG NA BB04 regmask=[allFloat] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1 last> DefList: { } N139 (???,???) [000306] ------------ * IL_OFFSET void IL offset: 0x23 REG NA DefList: { } N141 ( 1, 2) [000151] ------------ * LCL_VAR float V16 tmp2 u:2 NA (last use) REG NA $1c3 DefList: { } N143 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 NA REG NA LCL_VAR BB04 regmask=[allFloat] minReg=1 last> DefList: { } N145 (???,???) [000307] ------------ * IL_OFFSET void IL offset: 0x23 REG NA DefList: { } N147 ( 1, 2) [000156] ------------ * LCL_VAR float V17 tmp3 u:2 NA (last use) REG NA $1c5 DefList: { } N149 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 NA REG NA LCL_VAR BB04 regmask=[allFloat] minReg=1 last> DefList: { } N151 ( 3, 4) [000147] ------------ * LCL_FLD long V15 tmp1 [+0] NA * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 REG NA $4c0 Interval 32: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB04 regmask=[allInt] minReg=1> DefList: { N151.t147. LCL_FLD } N153 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] NA * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 REG NA BB04 regmask=[allInt] minReg=1 last> DefList: { } N155 (???,???) [000308] ------------ * IL_OFFSET void IL offset: 0x2c REG NA DefList: { } N157 (???,???) [000309] ------------ * IL_OFFSET void IL offset: 0x2c REG NA DefList: { } N159 (???,???) [000310] ------------ * IL_OFFSET void IL offset: 0x2c REG NA DefList: { } N161 ( 1, 1) [000252] ------------ * CNS_DBL float 0.00000000000000000 REG NA $100 Interval 33: float RefPositions {} physReg:NA Preferences=[allFloat] CNS_DBL BB04 regmask=[allFloat] minReg=1> DefList: { N161.t252. CNS_DBL } N163 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 NA REG NA BB04 regmask=[allFloat] minReg=1 last> DefList: { } N165 ( 1, 1) [000255] ------------ * CNS_DBL float 0.00000000000000000 REG NA $100 Interval 34: float RefPositions {} physReg:NA Preferences=[allFloat] CNS_DBL BB04 regmask=[allFloat] minReg=1> DefList: { N165.t255. CNS_DBL } N167 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 NA REG NA BB04 regmask=[allFloat] minReg=1 last> DefList: { } N169 (???,???) [000311] ------------ * IL_OFFSET void IL offset: 0x2c REG NA DefList: { } N171 ( 1, 2) [000166] -c---------- * LCL_VAR float V25 tmp11 NA REG NA $488 Contained DefList: { } N173 ( 1, 2) [000169] ------------ * LCL_VAR float V23 tmp9 u:2 NA REG NA $201 DefList: { } N175 ( 7, 8) [000170] ------------ * ADD float REG NA $1c6 LCL_VAR BB04 regmask=[allFloat] minReg=1 last> Interval 35: float RefPositions {} physReg:NA Preferences=[allFloat] ADD BB04 regmask=[allFloat] minReg=1> DefList: { N175.t170. ADD } N177 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 NA REG NA BB04 regmask=[allFloat] minReg=1 last> DefList: { } N179 (???,???) [000312] ------------ * IL_OFFSET void IL offset: 0x2c REG NA DefList: { } N181 ( 1, 2) [000173] -c---------- * LCL_VAR float V26 tmp12 NA REG NA $489 Contained DefList: { } N183 ( 1, 2) [000176] ------------ * LCL_VAR float V24 tmp10 u:2 NA REG NA $200 DefList: { } N185 ( 7, 8) [000177] ------------ * ADD float REG NA $1c7 LCL_VAR BB04 regmask=[allFloat] minReg=1 last> Interval 36: float RefPositions {} physReg:NA Preferences=[allFloat] ADD BB04 regmask=[allFloat] minReg=1> DefList: { N185.t177. ADD } N187 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 NA REG NA BB04 regmask=[allFloat] minReg=1 last> DefList: { } N189 ( 3, 4) [000184] ------------ * LCL_FLD long V20 tmp6 [+0] NA * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 REG NA $4c1 Interval 37: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB04 regmask=[allInt] minReg=1> DefList: { N189.t184. LCL_FLD } N191 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] NA * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 REG NA BB04 regmask=[allInt] minReg=1 last> DefList: { } N193 (???,???) [000313] ------------ * IL_OFFSET void IL offset: 0x37 REG NA DefList: { } N195 ( 1, 1) [000062] ------------ * LCL_VAR int V12 loc6 u:3 NA (last use) REG NA $242 DefList: { } N197 ( 1, 1) [000063] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N199 ( 3, 3) [000064] ------------ * ADD int REG NA $2c3 LCL_VAR BB04 regmask=[allInt] minReg=1 last> Interval 38: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB04 regmask=[allInt] minReg=1> Assigning related to DefList: { N199.t64. ADD } N201 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 NA REG NA BB04 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N203 ( 1, 2) [000205] ------------ * LCL_VAR float V25 tmp11 NA REG NA $48a Interval 39: float RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB04 regmask=[allFloat] minReg=1> DefList: { N203.t205. LCL_VAR } N205 ( 1, 2) [000208] -c---------- * LCL_VAR float V25 tmp11 NA REG NA $48b Contained DefList: { N203.t205. LCL_VAR } N207 ( 7, 8) [000209] ------------ * MUL float REG NA $1c8 BB04 regmask=[allFloat] minReg=1 last> Interval 40: float RefPositions {} physReg:NA Preferences=[allFloat] MUL BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N207.t209. MUL } N209 ( 1, 2) [000212] ------------ * LCL_VAR float V26 tmp12 NA REG NA $48c Interval 41: float RefPositions {} physReg:NA Preferences=[allFloat] LCL_VAR BB04 regmask=[allFloat] minReg=1> DefList: { N207.t209. MUL; N209.t212. LCL_VAR } N211 ( 1, 2) [000215] -c---------- * LCL_VAR float V26 tmp12 NA REG NA $48d Contained DefList: { N207.t209. MUL; N209.t212. LCL_VAR } N213 ( 7, 8) [000216] ------------ * MUL float REG NA $1c9 BB04 regmask=[allFloat] minReg=1 last> Interval 42: float RefPositions {} physReg:NA Preferences=[allFloat] MUL BB04 regmask=[allFloat] minReg=1> Assigning related to DefList: { N207.t209. MUL; N213.t216. MUL } N215 ( 19, 20) [000217] ------------ * ADD float REG NA $1ca BB04 regmask=[allFloat] minReg=1 last> BB04 regmask=[allFloat] minReg=1 last> Interval 43: float RefPositions {} physReg:NA Preferences=[allFloat] ADD BB04 regmask=[allFloat] minReg=1> Assigning related to Assigning related to DefList: { N215.t217. ADD } N217 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 NA REG NA BB04 regmask=[allFloat] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1 last> DefList: { } N219 (???,???) [000314] ------------ * IL_OFFSET void IL offset: 0x46 REG NA DefList: { } N221 ( 1, 2) [000073] ------------ * LCL_VAR float V13 loc7 u:2 NA (last use) REG NA $1ca DefList: { } N223 ( 3, 4) [000074] ------------ * CNS_DBL float 4.0000000000000000 REG NA $102 Interval 44: float RefPositions {} physReg:NA Preferences=[allFloat] CNS_DBL BB04 regmask=[allFloat] minReg=1> DefList: { N223.t74. CNS_DBL } N225 ( 5, 7) [000075] N------N-U-- * GE void REG NA $2c4 LCL_VAR BB04 regmask=[allFloat] minReg=1 last> BB04 regmask=[allFloat] minReg=1 last> DefList: { } N227 ( 7, 9) [000076] ------------ * JTRUE void REG NA CHECKING LAST USES for BB04, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} ============================== use: {V12 V23 V24} def: {V12 V13 V16 V17} NEW BLOCK BB05 Setting BB04 as the predecessor for determining incoming variable registers of BB05 DefList: { } N231 (???,???) [000315] ------------ * IL_OFFSET void IL offset: 0x4f REG NA DefList: { } N233 ( 1, 1) [000094] ------------ * LCL_VAR int V12 loc6 u:4 NA REG NA $2c3 DefList: { } N235 ( 1, 4) [000095] -c---------- * CNS_INT int 0x3E8 REG NA $47 Contained DefList: { } N237 ( 3, 6) [000096] J------N---- * LT void REG NA $2c5 LCL_VAR BB05 regmask=[allInt] minReg=1 last> DefList: { } N239 ( 5, 8) [000097] ------------ * JTRUE void REG NA Exposed uses: BB05 regmask=[allFloat] minReg=1> V23 BB05 regmask=[allFloat] minReg=1> V24 CHECKING LAST USES for BB05, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} ============================== use: {V12} def: {} NEW BLOCK BB06 Setting BB04 as the predecessor for determining incoming variable registers of BB06 DefList: { } N243 ( 1, 1) [000077] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $80 DefList: { } N245 ( 2, 2) [000259] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N247 ( 4, 4) [000219] ---XG------- * IND ref REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 45: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N247.t219. IND } N249 (???,???) [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N251 (???,???) [000329] ------------ * LCL_VAR ref V35 rat0 NA REG NA DefList: { } N253 (???,???) [000330] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N255 (???,???) [000331] ------------ * IND ref REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 46: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N255.t331. IND } N257 (???,???) [000323] ---XG------- * PUTARG_REG ref REG rcx BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> Interval 47: ref RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rcx] minReg=1> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed> DefList: { N257.t323. PUTARG_REG } N259 ( 1, 1) [000080] ------------ * LCL_VAR int V08 loc2 u:3 NA REG NA $241 DefList: { N257.t323. PUTARG_REG } N261 (???,???) [000324] ------------ * PUTARG_REG int REG rdx BB06 regmask=[rdx] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 48: int RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[rdx] minReg=1> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG } N263 ( 1, 1) [000081] ------------ * LCL_VAR int V06 loc0 u:3 NA REG NA $240 DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG } N265 (???,???) [000325] ------------ * PUTARG_REG int REG r8 BB06 regmask=[r8] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 49: int RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[r8] minReg=1> PUTARG_REG BB06 regmask=[r8] minReg=1 fixed> Assigning related to DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG; N265.t325. PUTARG_REG } N267 ( 1, 1) [000082] ------------ * LCL_VAR int V12 loc6 u:4 NA (last use) REG NA $2c3 DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG; N265.t325. PUTARG_REG } N269 (???,???) [000326] ------------ * PUTARG_REG int REG r9 BB06 regmask=[r9] minReg=1> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> Interval 50: int RefPositions {} physReg:NA Preferences=[allInt] BB06 regmask=[r9] minReg=1> PUTARG_REG BB06 regmask=[r9] minReg=1 fixed> DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG; N265.t325. PUTARG_REG; N269.t326. PUTARG_REG } N271 ( 3, 2) [000332] ------------ * LCL_VAR ref V35 rat0 NA (last use) REG NA DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG; N265.t325. PUTARG_REG; N269.t326. PUTARG_REG } N273 ( 4, 3) [000333] -c---------- * LEA(b+24) ref REG NA Contained DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG; N265.t325. PUTARG_REG; N269.t326. PUTARG_REG } N275 ( 7, 5) [000334] -c---------- * IND long REG NA Contained DefList: { N257.t323. PUTARG_REG; N261.t324. PUTARG_REG; N265.t325. PUTARG_REG; N269.t326. PUTARG_REG } N277 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke REG NA $VN.Void BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rdx] minReg=1 last fixed> BB06 regmask=[r8] minReg=1> BB06 regmask=[r8] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> BB06 regmask=[r9] minReg=1 last fixed> LCL_VAR BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rdx] minReg=1> BB06 regmask=[r8] minReg=1> BB06 regmask=[r9] minReg=1> BB06 regmask=[r10] minReg=1> BB06 regmask=[r11] minReg=1> BB06 regmask=[mm0] minReg=1> BB06 regmask=[mm1] minReg=1> BB06 regmask=[mm2] minReg=1> BB06 regmask=[mm3] minReg=1> BB06 regmask=[mm4] minReg=1> BB06 regmask=[mm5] minReg=1> DefList: { } N279 (???,???) [000316] ------------ * IL_OFFSET void IL offset: 0x67 REG NA DefList: { } N281 ( 1, 2) [000084] ------------ * LCL_VAR float V09 loc3 u:3 NA (last use) REG NA $201 DefList: { } N283 ( 1, 2) [000085] ------------ * LCL_VAR float V05 arg5 u:1 NA REG NA $c4 DefList: { } N285 ( 7, 8) [000086] ------------ * ADD float REG NA $1cb LCL_VAR BB06 regmask=[allFloat] minReg=1 last> LCL_VAR BB06 regmask=[allFloat] minReg=1 last> Interval 51: float RefPositions {} physReg:NA Preferences=[allFloat] ADD BB06 regmask=[allFloat] minReg=1> Assigning related to DefList: { N285.t86. ADD } N287 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 NA REG NA BB06 regmask=[allFloat] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allFloat] minReg=1 last> DefList: { } N289 (???,???) [000317] ------------ * IL_OFFSET void IL offset: 0x6c REG NA DefList: { } N291 ( 1, 1) [000089] ------------ * LCL_VAR int V08 loc2 u:3 NA (last use) REG NA $241 DefList: { } N293 ( 1, 1) [000090] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N295 ( 3, 3) [000091] ------------ * ADD int REG NA $2c6 LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 52: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB06 regmask=[allInt] minReg=1> Assigning related to DefList: { N295.t91. ADD } N297 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N299 (???,???) [000318] ------------ * IL_OFFSET void IL offset: 0x70 REG NA DefList: { } N301 ( 1, 2) [000023] ------------ * LCL_VAR float V09 loc3 u:4 NA REG NA $1cb DefList: { } N303 ( 1, 2) [000024] ------------ * LCL_VAR float V02 arg2 u:1 NA REG NA $c1 DefList: { } N305 ( 3, 5) [000025] J------N---- * LT void REG NA $2c7 LCL_VAR BB06 regmask=[allFloat] minReg=1 last> LCL_VAR BB06 regmask=[allFloat] minReg=1 last> DefList: { } N307 ( 5, 7) [000026] ------------ * JTRUE void REG NA Exposed uses: BB06 regmask=[allInt] minReg=1> V08 BB06 regmask=[allFloat] minReg=1> V09 CHECKING LAST USES for BB06, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V09} ============================== use: {V00 V02 V05 V06 V08 V09 V12} def: {V08 V09 V35} NEW BLOCK BB07 Setting BB06 as the predecessor for determining incoming variable registers of BB07 DefList: { } N311 (???,???) [000319] ------------ * IL_OFFSET void IL offset: 0x74 REG NA DefList: { } N313 ( 1, 2) [000098] ------------ * LCL_VAR float V07 loc1 u:3 NA (last use) REG NA $200 DefList: { } N315 ( 1, 2) [000099] ------------ * LCL_VAR float V05 arg5 u:1 NA REG NA $c4 DefList: { } N317 ( 7, 8) [000100] ------------ * ADD float REG NA $1cc LCL_VAR BB07 regmask=[allFloat] minReg=1 last> LCL_VAR BB07 regmask=[allFloat] minReg=1 last> Interval 53: float RefPositions {} physReg:NA Preferences=[allFloat] ADD BB07 regmask=[allFloat] minReg=1> Assigning related to DefList: { N317.t100. ADD } N319 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 NA REG NA BB07 regmask=[allFloat] minReg=1 last> Assigning related to STORE_LCL_VAR BB07 regmask=[allFloat] minReg=1 last> DefList: { } N321 (???,???) [000320] ------------ * IL_OFFSET void IL offset: 0x79 REG NA DefList: { } N323 ( 1, 1) [000103] ------------ * LCL_VAR int V06 loc0 u:3 NA (last use) REG NA $240 DefList: { } N325 ( 1, 1) [000104] -c---------- * CNS_INT int 1 REG NA $41 Contained DefList: { } N327 ( 3, 3) [000105] ------------ * ADD int REG NA $2c8 LCL_VAR BB07 regmask=[allInt] minReg=1 last> Interval 54: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB07 regmask=[allInt] minReg=1> Assigning related to DefList: { N327.t105. ADD } N329 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 NA REG NA BB07 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB07 regmask=[allInt] minReg=1 last> Exposed uses: BB07 regmask=[allInt] minReg=1> V00 BB07 regmask=[allInt] minReg=1> V06 BB07 regmask=[allFloat] minReg=1> V07 BB07 regmask=[allFloat] minReg=1> V02 BB07 regmask=[allFloat] minReg=1> V05 BB07 regmask=[allFloat] minReg=1> V01 BB07 regmask=[allFloat] minReg=1> V04 CHECKING LAST USES for BB07, liveout={V00 V01 V02 V04 V05 V06 V07} ============================== use: {V05 V06 V07} def: {V06 V07} NEW BLOCK BB10 Setting BB08 as the predecessor for determining incoming variable registers of BB10 DefList: { } N333 (???,???) [000322] ------------ * IL_OFFSET void IL offset: 0x8d REG NA DefList: { } N335 ( 0, 0) [000010] ------------ * RETURN void REG NA $380 CHECKING LAST USES for BB10, liveout={} ============================== use: {} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) ref RefPositions {#0@0 #17@31 #118@247 #185@331} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) float RefPositions {#3@0 #42@53 #44@61 #190@331} physReg:mm1 Preferences=[mm6-mm15] Interval 2: (V02) float RefPositions {#1@0 #45@61 #172@305 #188@331} physReg:mm2 Preferences=[mm6-mm15] Interval 3: (V03) float RefPositions {#5@0 #10@13} physReg:mm3 Preferences=[mm3] RelatedInterval Interval 4: (V04) float RefPositions {#4@0 #14@23 #191@331} physReg:NA Preferences=[mm6-mm15] Interval 5: (V05) float RefPositions {#2@0 #163@285 #177@317 #189@331} physReg:NA Preferences=[mm6-mm15] Interval 6: (V06) int RefPositions {#9@8 #133@265 #181@327 #184@330 #186@331} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 7: (V07) float RefPositions {#11@14 #13@23 #49@77 #176@317 #180@320 #187@331} physReg:NA Preferences=[mm6-mm15] RelatedInterval Interval 8: (V08) int RefPositions {#41@48 #129@261 #167@295 #170@298 #173@309} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 9: (V09) float RefPositions {#43@54 #47@71 #162@285 #166@288 #171@305 #174@309} physReg:NA Preferences=[mm6-mm15] RelatedInterval Interval 10: (V12) int RefPositions {#55@94 #95@199 #98@202 #114@237 #137@269} physReg:NA Preferences=[r9] RelatedInterval Interval 11: (V13) float RefPositions {#109@218 #111@225} physReg:NA Preferences=[allFloat] Interval 12: (V16) float RefPositions {#71@124 #79@143} physReg:NA Preferences=[allFloat] Interval 13: (V17) float RefPositions {#78@138 #80@149} physReg:NA Preferences=[allFloat] Interval 14: (V23) float (struct) RefPositions {#48@72 #51@83 #87@175 #115@241} physReg:NA Preferences=[allFloat] Interval 15: (V24) float (struct) RefPositions {#50@78 #52@87 #90@185 #116@241} physReg:NA Preferences=[allFloat] Interval 16: (V35) ref RefPositions {#121@250 #122@255 #148@277} physReg:NA Preferences=[allInt] Interval 17: int (constant) RefPositions {#7@6 #8@7} physReg:NA Preferences=[allInt] RelatedInterval Interval 18: ref (specialPutArg) RefPositions {#19@32 #21@33} physReg:NA Preferences=[rcx] RelatedInterval Interval 19: int RefPositions {#36@34 #37@37} physReg:NA Preferences=[rax] Interval 20: int (constant) RefPositions {#39@46 #40@47} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: int (constant) RefPositions {#53@92 #54@93} physReg:NA Preferences=[allInt] RelatedInterval Interval 22: float (constant) RefPositions {#57@100 #58@101} physReg:NA Preferences=[allFloat] Interval 23: float (constant) RefPositions {#59@104 #60@105} physReg:NA Preferences=[allFloat] Interval 24: float RefPositions {#61@110 #62@113} physReg:NA Preferences=[allFloat] RelatedInterval Interval 25: float RefPositions {#63@114 #67@121} physReg:NA Preferences=[allFloat] RelatedInterval Interval 26: float RefPositions {#64@116 #65@119} physReg:NA Preferences=[allFloat] RelatedInterval Interval 27: float RefPositions {#66@120 #68@121} physReg:NA Preferences=[allFloat] Interval 28: float (interfering uses) RefPositions {#69@122 #70@123} physReg:NA Preferences=[allFloat] RelatedInterval Interval 29: float RefPositions {#72@128 #73@131} physReg:NA Preferences=[allFloat] RelatedInterval Interval 30: float RefPositions {#74@132 #75@135} physReg:NA Preferences=[allFloat] RelatedInterval Interval 31: float RefPositions {#76@136 #77@137} physReg:NA Preferences=[allFloat] RelatedInterval Interval 32: long RefPositions {#81@152 #82@153} physReg:NA Preferences=[allInt] Interval 33: float (constant) RefPositions {#83@162 #84@163} physReg:NA Preferences=[allFloat] Interval 34: float (constant) RefPositions {#85@166 #86@167} physReg:NA Preferences=[allFloat] Interval 35: float RefPositions {#88@176 #89@177} physReg:NA Preferences=[allFloat] Interval 36: float RefPositions {#91@186 #92@187} physReg:NA Preferences=[allFloat] Interval 37: long RefPositions {#93@190 #94@191} physReg:NA Preferences=[allInt] Interval 38: int RefPositions {#96@200 #97@201} physReg:NA Preferences=[allInt] RelatedInterval Interval 39: float RefPositions {#99@204 #100@207} physReg:NA Preferences=[allFloat] RelatedInterval Interval 40: float RefPositions {#101@208 #105@215} physReg:NA Preferences=[allFloat] RelatedInterval Interval 41: float RefPositions {#102@210 #103@213} physReg:NA Preferences=[allFloat] RelatedInterval Interval 42: float RefPositions {#104@214 #106@215} physReg:NA Preferences=[allFloat] RelatedInterval Interval 43: float RefPositions {#107@216 #108@217} physReg:NA Preferences=[allFloat] RelatedInterval Interval 44: float (constant) RefPositions {#110@224 #112@225} physReg:NA Preferences=[allFloat] Interval 45: ref RefPositions {#119@248 #120@249} physReg:NA Preferences=[allInt] RelatedInterval Interval 46: ref RefPositions {#123@256 #125@257} physReg:NA Preferences=[rcx] Interval 47: ref RefPositions {#127@258 #141@277} physReg:NA Preferences=[rcx] Interval 48: int (specialPutArg) RefPositions {#131@262 #143@277} physReg:NA Preferences=[rdx] RelatedInterval Interval 49: int (specialPutArg) RefPositions {#135@266 #145@277} physReg:NA Preferences=[r8] RelatedInterval Interval 50: int RefPositions {#139@270 #147@277} physReg:NA Preferences=[r9] Interval 51: float RefPositions {#164@286 #165@287} physReg:NA Preferences=[allFloat] RelatedInterval Interval 52: int RefPositions {#168@296 #169@297} physReg:NA Preferences=[allInt] RelatedInterval Interval 53: float RefPositions {#178@318 #179@319} physReg:NA Preferences=[allFloat] RelatedInterval Interval 54: int RefPositions {#182@328 #183@329} physReg:NA Preferences=[allInt] RelatedInterval ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[mm2] minReg=1 fixed regOptional> BB00 regmask=[allFloat] minReg=1 regOptional> BB00 regmask=[mm1] minReg=1 fixed regOptional> BB00 regmask=[allFloat] minReg=1 regOptional> BB00 regmask=[mm3] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> LCL_VAR BB08 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB08 regmask=[allFloat] minReg=1> BB09 regmask=[rcx] minReg=1> LCL_VAR BB09 regmask=[rcx] minReg=1 fixed> BB09 regmask=[rcx] minReg=1> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rcx] minReg=1 last fixed> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[mm0] minReg=1 last> BB09 regmask=[mm1] minReg=1 last> BB09 regmask=[mm2] minReg=1 last> BB09 regmask=[mm3] minReg=1 last> BB09 regmask=[mm4] minReg=1 last> BB09 regmask=[mm5] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> CNS_INT BB03 regmask=[allInt] minReg=1> BB03 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> BB04 regmask=[allFloat] minReg=1 last delay regOptional> SUB BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> LCL_FLD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1> ADD BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1> ADD BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_FLD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> LCL_VAR BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last regOptional> BB04 regmask=[allFloat] minReg=1 last> ADD BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> CNS_DBL BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last regOptional> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional> BB05 regmask=[allFloat] minReg=1 regOptional> BB05 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rcx] minReg=1> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[r8] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 fixed> BB06 regmask=[r8] minReg=1> PUTARG_REG BB06 regmask=[r8] minReg=1 fixed> BB06 regmask=[r9] minReg=1> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> PUTARG_REG BB06 regmask=[r9] minReg=1 fixed> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rdx] minReg=1 last fixed> BB06 regmask=[r8] minReg=1> BB06 regmask=[r8] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> BB06 regmask=[r9] minReg=1 last fixed> LCL_VAR BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[mm0] minReg=1 last> BB06 regmask=[mm1] minReg=1 last> BB06 regmask=[mm2] minReg=1 last> BB06 regmask=[mm3] minReg=1 last> BB06 regmask=[mm4] minReg=1 last> BB06 regmask=[mm5] minReg=1 last> LCL_VAR BB06 regmask=[allFloat] minReg=1 last> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> ADD BB06 regmask=[allFloat] minReg=1> BB06 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last> ADD BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[allFloat] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB07 regmask=[allFloat] minReg=1 last> LCL_VAR BB07 regmask=[allFloat] minReg=1 regOptional> ADD BB07 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allFloat] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> ADD BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB03 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 fixed> LCL_VAR BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB09 regmask=[rcx] minReg=1 fixed> LCL_VAR BB06 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 fixed> LCL_VAR BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> ----------------- STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> ----------------- STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> BB06 regmask=[allFloat] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> LCL_VAR BB08 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB07 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> ----------------- BB00 regmask=[mm2] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> ----------------- BB00 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> ----------------- BB00 regmask=[mm1] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> ----------------- BB00 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB08 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> ----------------- BB00 regmask=[mm3] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allFloat] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 V02 V05 V01 V04 V03 BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ===== N003. IL_OFFSET IL offset: 0x0 N005. CNS_INT 0 Def:(#7) Pref: N007. V06(L6) Use:(#8) * Def:(#9) Pref: N009. IL_OFFSET IL offset: 0x2 N011. V03(L3) N013. V07(L7) Use:(#10) * Def:(#11) Pref: BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ===== N017. IL_OFFSET IL offset: 0x7d N019. V07(L7) N021. V04(L4) N023. GE Use:(#13) Use:(#14) N025. JTRUE BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ===== N029. V00(L0) N031. PUTARG_REG Use:(#17) Fixed:rcx(#16) Def:(#19) rcx Pref: N033. CALL Use:(#21) Fixed:rcx(#20) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 Def:(#36) rax N035. CNS_INT 0 N037. EQ Use:(#37) * N039. JTRUE BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ===== N043. IL_OFFSET IL offset: 0x6 N045. CNS_INT 0 Def:(#39) Pref: N047. V08(L8) Use:(#40) * Def:(#41) Pref: N049. IL_OFFSET IL offset: 0x8 N051. V01(L1) N053. V09(L9) Use:(#42) Def:(#43) Pref: N055. IL_OFFSET IL offset: 0x70 N057. V01(L1) N059. V02(L2) N061. GE Use:(#44) Use:(#45) N063. JTRUE BB03 [00C..023), preds={BB02,BB06} succs={BB04} ===== N067. IL_OFFSET IL offset: 0xc N069. V09(L9) N071. V23(L14) Use:(#47) Def:(#48) N073. IL_OFFSET IL offset: 0xc N075. V07(L7) N077. V24(L15) Use:(#49) Def:(#50) N079. IL_OFFSET IL offset: 0x15 N081. V23(L14) N083. V25 MEM Use:(#51) N085. V24(L15) N087. V26 MEM Use:(#52) N089. IL_OFFSET IL offset: 0x19 N091. CNS_INT 0 Def:(#53) Pref: N093. V12(L10) Use:(#54) * Def:(#55) Pref: BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ===== N097. IL_OFFSET IL offset: 0x23 N099. CNS_DBL 0.00000000000000000 Def:(#57) N101. V27 MEM Use:(#58) * N103. CNS_DBL 0.00000000000000000 Def:(#59) N105. V28 MEM Use:(#60) * N107. IL_OFFSET IL offset: 0x23 N109. V25 MEM Def:(#61) Pref: N111. V25 MEM N113. MUL Use:(#62) * Def:(#63) Pref: N115. V26 MEM Def:(#64) Pref: N117. V26 MEM N119. MUL Use:(#65) * Def:(#66) N121. SUB Use:(#67) * Use:(#68) * Def:(#69) Pref: N123. V16(L12) Use:(#70) * Def:(#71) N125. IL_OFFSET IL offset: 0x23 N127. V25 MEM Def:(#72) Pref: N129. CNS_DBL 2.0000000000000000 N131. MUL Use:(#73) * Def:(#74) Pref: N133. V26 MEM N135. MUL Use:(#75) * Def:(#76) Pref: N137. V17(L13) Use:(#77) * Def:(#78) N139. IL_OFFSET IL offset: 0x23 N141. V16(L12) N143. V27 MEM Use:(#79) * N145. IL_OFFSET IL offset: 0x23 N147. V17(L13) N149. V28 MEM Use:(#80) * N151. V15 MEM Def:(#81) N153. V11 MEM Use:(#82) * N155. IL_OFFSET IL offset: 0x2c N157. IL_OFFSET IL offset: 0x2c N159. IL_OFFSET IL offset: 0x2c N161. CNS_DBL 0.00000000000000000 Def:(#83) N163. V33 MEM Use:(#84) * N165. CNS_DBL 0.00000000000000000 Def:(#85) N167. V34 MEM Use:(#86) * N169. IL_OFFSET IL offset: 0x2c N171. V25 MEM N173. V23(L14) N175. ADD Use:(#87) Def:(#88) N177. V33 MEM Use:(#89) * N179. IL_OFFSET IL offset: 0x2c N181. V26 MEM N183. V24(L15) N185. ADD Use:(#90) Def:(#91) N187. V34 MEM Use:(#92) * N189. V20 MEM Def:(#93) N191. V11 MEM Use:(#94) * N193. IL_OFFSET IL offset: 0x37 N195. V12(L10) N197. CNS_INT 1 N199. ADD Use:(#95) * Def:(#96) Pref: N201. V12(L10) Use:(#97) * Def:(#98) Pref: N203. V25 MEM Def:(#99) Pref: N205. V25 MEM N207. MUL Use:(#100) * Def:(#101) Pref: N209. V26 MEM Def:(#102) Pref: N211. V26 MEM N213. MUL Use:(#103) * Def:(#104) Pref: N215. ADD Use:(#105) * Use:(#106) * Def:(#107) Pref: N217. V13(L11) Use:(#108) * Def:(#109) N219. IL_OFFSET IL offset: 0x46 N221. V13(L11) N223. CNS_DBL 4.0000000000000000 Def:(#110) N225. GE Use:(#111) * Use:(#112) * N227. JTRUE BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ===== N231. IL_OFFSET IL offset: 0x4f N233. V12(L10) N235. CNS_INT 0x3E8 N237. LT Use:(#114) N239. JTRUE Exposed use of V23 at #115 Exposed use of V24 at #116 BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ===== N243. V00(L0) N245. LEA(b+16) N247. IND Use:(#118) Def:(#119) Pref: N249. V35(L16) Use:(#120) * Def:(#121) N251. V35(L16) N253. LEA(b+8) N255. IND Use:(#122) Def:(#123) N257. PUTARG_REG Use:(#125) Fixed:rcx(#124) * Def:(#127) rcx N259. V08(L8) N261. PUTARG_REG Use:(#129) Fixed:rdx(#128) Def:(#131) rdx Pref: N263. V06(L6) N265. PUTARG_REG Use:(#133) Fixed:r8(#132) Def:(#135) r8 Pref: N267. V12(L10) N269. PUTARG_REG Use:(#137) Fixed:r9(#136) * Def:(#139) r9 N271. V35(L16) N273. LEA(b+24) N275. IND N277. CALL Use:(#141) Fixed:rcx(#140) * Use:(#143) Fixed:rdx(#142) * Use:(#145) Fixed:r8(#144) * Use:(#147) Fixed:r9(#146) * Use:(#148) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N279. IL_OFFSET IL offset: 0x67 N281. V09(L9) N283. V05(L5) N285. ADD Use:(#162) * Use:(#163) Def:(#164) Pref: N287. V09(L9) Use:(#165) * Def:(#166) Pref: N289. IL_OFFSET IL offset: 0x6c N291. V08(L8) N293. CNS_INT 1 N295. ADD Use:(#167) * Def:(#168) Pref: N297. V08(L8) Use:(#169) * Def:(#170) Pref: N299. IL_OFFSET IL offset: 0x70 N301. V09(L9) N303. V02(L2) N305. LT Use:(#171) Use:(#172) N307. JTRUE Exposed use of V08 at #173 Exposed use of V09 at #174 BB07 [074..07D), preds={BB02,BB06} succs={BB08} ===== N311. IL_OFFSET IL offset: 0x74 N313. V07(L7) N315. V05(L5) N317. ADD Use:(#176) * Use:(#177) Def:(#178) Pref: N319. V07(L7) Use:(#179) * Def:(#180) Pref: N321. IL_OFFSET IL offset: 0x79 N323. V06(L6) N325. CNS_INT 1 N327. ADD Use:(#181) * Def:(#182) Pref: N329. V06(L6) Use:(#183) * Def:(#184) Pref: Exposed use of V00 at #185 Exposed use of V06 at #186 Exposed use of V07 at #187 Exposed use of V02 at #188 Exposed use of V05 at #189 Exposed use of V01 at #190 Exposed use of V04 at #191 BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ===== N333. IL_OFFSET IL offset: 0x8d N335. RETURN Linear scan intervals after buildIntervals: Interval 0: (V00) ref RefPositions {#0@0 #17@31 #118@247 #185@331} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) float RefPositions {#3@0 #42@53 #44@61 #190@331} physReg:mm1 Preferences=[mm6-mm15] Interval 2: (V02) float RefPositions {#1@0 #45@61 #172@305 #188@331} physReg:mm2 Preferences=[mm6-mm15] Interval 3: (V03) float RefPositions {#5@0 #10@13} physReg:mm3 Preferences=[mm3] RelatedInterval Interval 4: (V04) float RefPositions {#4@0 #14@23 #191@331} physReg:NA Preferences=[mm6-mm15] Interval 5: (V05) float RefPositions {#2@0 #163@285 #177@317 #189@331} physReg:NA Preferences=[mm6-mm15] Interval 6: (V06) int RefPositions {#9@8 #133@265 #181@327 #184@330 #186@331} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 7: (V07) float RefPositions {#11@14 #13@23 #49@77 #176@317 #180@320 #187@331} physReg:NA Preferences=[mm6-mm15] RelatedInterval Interval 8: (V08) int RefPositions {#41@48 #129@261 #167@295 #170@298 #173@309} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 9: (V09) float RefPositions {#43@54 #47@71 #162@285 #166@288 #171@305 #174@309} physReg:NA Preferences=[mm6-mm15] RelatedInterval Interval 10: (V12) int RefPositions {#55@94 #95@199 #98@202 #114@237 #137@269} physReg:NA Preferences=[r9] RelatedInterval Interval 11: (V13) float RefPositions {#109@218 #111@225} physReg:NA Preferences=[allFloat] Interval 12: (V16) float RefPositions {#71@124 #79@143} physReg:NA Preferences=[allFloat] Interval 13: (V17) float RefPositions {#78@138 #80@149} physReg:NA Preferences=[allFloat] Interval 14: (V23) float (struct) RefPositions {#48@72 #51@83 #87@175 #115@241} physReg:NA Preferences=[allFloat] Interval 15: (V24) float (struct) RefPositions {#50@78 #52@87 #90@185 #116@241} physReg:NA Preferences=[allFloat] Interval 16: (V35) ref RefPositions {#121@250 #122@255 #148@277} physReg:NA Preferences=[allInt] Interval 17: int (constant) RefPositions {#7@6 #8@7} physReg:NA Preferences=[allInt] RelatedInterval Interval 18: ref (specialPutArg) RefPositions {#19@32 #21@33} physReg:NA Preferences=[rcx] RelatedInterval Interval 19: int RefPositions {#36@34 #37@37} physReg:NA Preferences=[rax] Interval 20: int (constant) RefPositions {#39@46 #40@47} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: int (constant) RefPositions {#53@92 #54@93} physReg:NA Preferences=[allInt] RelatedInterval Interval 22: float (constant) RefPositions {#57@100 #58@101} physReg:NA Preferences=[allFloat] Interval 23: float (constant) RefPositions {#59@104 #60@105} physReg:NA Preferences=[allFloat] Interval 24: float RefPositions {#61@110 #62@113} physReg:NA Preferences=[allFloat] RelatedInterval Interval 25: float RefPositions {#63@114 #67@121} physReg:NA Preferences=[allFloat] RelatedInterval Interval 26: float RefPositions {#64@116 #65@119} physReg:NA Preferences=[allFloat] RelatedInterval Interval 27: float RefPositions {#66@120 #68@121} physReg:NA Preferences=[allFloat] Interval 28: float (interfering uses) RefPositions {#69@122 #70@123} physReg:NA Preferences=[allFloat] RelatedInterval Interval 29: float RefPositions {#72@128 #73@131} physReg:NA Preferences=[allFloat] RelatedInterval Interval 30: float RefPositions {#74@132 #75@135} physReg:NA Preferences=[allFloat] RelatedInterval Interval 31: float RefPositions {#76@136 #77@137} physReg:NA Preferences=[allFloat] RelatedInterval Interval 32: long RefPositions {#81@152 #82@153} physReg:NA Preferences=[allInt] Interval 33: float (constant) RefPositions {#83@162 #84@163} physReg:NA Preferences=[allFloat] Interval 34: float (constant) RefPositions {#85@166 #86@167} physReg:NA Preferences=[allFloat] Interval 35: float RefPositions {#88@176 #89@177} physReg:NA Preferences=[allFloat] Interval 36: float RefPositions {#91@186 #92@187} physReg:NA Preferences=[allFloat] Interval 37: long RefPositions {#93@190 #94@191} physReg:NA Preferences=[allInt] Interval 38: int RefPositions {#96@200 #97@201} physReg:NA Preferences=[allInt] RelatedInterval Interval 39: float RefPositions {#99@204 #100@207} physReg:NA Preferences=[allFloat] RelatedInterval Interval 40: float RefPositions {#101@208 #105@215} physReg:NA Preferences=[allFloat] RelatedInterval Interval 41: float RefPositions {#102@210 #103@213} physReg:NA Preferences=[allFloat] RelatedInterval Interval 42: float RefPositions {#104@214 #106@215} physReg:NA Preferences=[allFloat] RelatedInterval Interval 43: float RefPositions {#107@216 #108@217} physReg:NA Preferences=[allFloat] RelatedInterval Interval 44: float (constant) RefPositions {#110@224 #112@225} physReg:NA Preferences=[allFloat] Interval 45: ref RefPositions {#119@248 #120@249} physReg:NA Preferences=[allInt] RelatedInterval Interval 46: ref RefPositions {#123@256 #125@257} physReg:NA Preferences=[rcx] Interval 47: ref RefPositions {#127@258 #141@277} physReg:NA Preferences=[rcx] Interval 48: int (specialPutArg) RefPositions {#131@262 #143@277} physReg:NA Preferences=[rdx] RelatedInterval Interval 49: int (specialPutArg) RefPositions {#135@266 #145@277} physReg:NA Preferences=[r8] RelatedInterval Interval 50: int RefPositions {#139@270 #147@277} physReg:NA Preferences=[r9] Interval 51: float RefPositions {#164@286 #165@287} physReg:NA Preferences=[allFloat] RelatedInterval Interval 52: int RefPositions {#168@296 #169@297} physReg:NA Preferences=[allInt] RelatedInterval Interval 53: float RefPositions {#178@318 #179@319} physReg:NA Preferences=[allFloat] RelatedInterval Interval 54: int RefPositions {#182@328 #183@329} physReg:NA Preferences=[allInt] RelatedInterval *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) ref RefPositions {#0@0 #17@31 #118@247 #185@331} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) float RefPositions {#3@0 #42@53 #44@61 #190@331} physReg:mm1 Preferences=[mm6-mm15] Interval 2: (V02) float RefPositions {#1@0 #45@61 #172@305 #188@331} physReg:mm2 Preferences=[mm6-mm15] Interval 3: (V03) float RefPositions {#5@0 #10@13} physReg:mm3 Preferences=[mm3] RelatedInterval Interval 4: (V04) float RefPositions {#4@0 #14@23 #191@331} physReg:NA Preferences=[mm6-mm15] Interval 5: (V05) float RefPositions {#2@0 #163@285 #177@317 #189@331} physReg:NA Preferences=[mm6-mm15] Interval 6: (V06) int RefPositions {#9@8 #133@265 #181@327 #184@330 #186@331} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 7: (V07) float RefPositions {#11@14 #13@23 #49@77 #176@317 #180@320 #187@331} physReg:NA Preferences=[mm6-mm15] RelatedInterval Interval 8: (V08) int RefPositions {#41@48 #129@261 #167@295 #170@298 #173@309} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 9: (V09) float RefPositions {#43@54 #47@71 #162@285 #166@288 #171@305 #174@309} physReg:NA Preferences=[mm6-mm15] RelatedInterval Interval 10: (V12) int RefPositions {#55@94 #95@199 #98@202 #114@237 #137@269} physReg:NA Preferences=[r9] RelatedInterval Interval 11: (V13) float RefPositions {#109@218 #111@225} physReg:NA Preferences=[allFloat] Interval 12: (V16) float RefPositions {#71@124 #79@143} physReg:NA Preferences=[allFloat] Interval 13: (V17) float RefPositions {#78@138 #80@149} physReg:NA Preferences=[allFloat] Interval 14: (V23) float (struct) RefPositions {#48@72 #51@83 #87@175 #115@241} physReg:NA Preferences=[allFloat] Interval 15: (V24) float (struct) RefPositions {#50@78 #52@87 #90@185 #116@241} physReg:NA Preferences=[allFloat] Interval 16: (V35) ref RefPositions {#121@250 #122@255 #148@277} physReg:NA Preferences=[allInt] Interval 17: int (constant) RefPositions {#7@6 #8@7} physReg:NA Preferences=[allInt] RelatedInterval Interval 18: ref (specialPutArg) RefPositions {#19@32 #21@33} physReg:NA Preferences=[rcx] RelatedInterval Interval 19: int RefPositions {#36@34 #37@37} physReg:NA Preferences=[rax] Interval 20: int (constant) RefPositions {#39@46 #40@47} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: int (constant) RefPositions {#53@92 #54@93} physReg:NA Preferences=[allInt] RelatedInterval Interval 22: float (constant) RefPositions {#57@100 #58@101} physReg:NA Preferences=[allFloat] Interval 23: float (constant) RefPositions {#59@104 #60@105} physReg:NA Preferences=[allFloat] Interval 24: float RefPositions {#61@110 #62@113} physReg:NA Preferences=[allFloat] RelatedInterval Interval 25: float RefPositions {#63@114 #67@121} physReg:NA Preferences=[allFloat] RelatedInterval Interval 26: float RefPositions {#64@116 #65@119} physReg:NA Preferences=[allFloat] RelatedInterval Interval 27: float RefPositions {#66@120 #68@121} physReg:NA Preferences=[allFloat] Interval 28: float (interfering uses) RefPositions {#69@122 #70@123} physReg:NA Preferences=[allFloat] RelatedInterval Interval 29: float RefPositions {#72@128 #73@131} physReg:NA Preferences=[allFloat] RelatedInterval Interval 30: float RefPositions {#74@132 #75@135} physReg:NA Preferences=[allFloat] RelatedInterval Interval 31: float RefPositions {#76@136 #77@137} physReg:NA Preferences=[allFloat] RelatedInterval Interval 32: long RefPositions {#81@152 #82@153} physReg:NA Preferences=[allInt] Interval 33: float (constant) RefPositions {#83@162 #84@163} physReg:NA Preferences=[allFloat] Interval 34: float (constant) RefPositions {#85@166 #86@167} physReg:NA Preferences=[allFloat] Interval 35: float RefPositions {#88@176 #89@177} physReg:NA Preferences=[allFloat] Interval 36: float RefPositions {#91@186 #92@187} physReg:NA Preferences=[allFloat] Interval 37: long RefPositions {#93@190 #94@191} physReg:NA Preferences=[allInt] Interval 38: int RefPositions {#96@200 #97@201} physReg:NA Preferences=[allInt] RelatedInterval Interval 39: float RefPositions {#99@204 #100@207} physReg:NA Preferences=[allFloat] RelatedInterval Interval 40: float RefPositions {#101@208 #105@215} physReg:NA Preferences=[allFloat] RelatedInterval Interval 41: float RefPositions {#102@210 #103@213} physReg:NA Preferences=[allFloat] RelatedInterval Interval 42: float RefPositions {#104@214 #106@215} physReg:NA Preferences=[allFloat] RelatedInterval Interval 43: float RefPositions {#107@216 #108@217} physReg:NA Preferences=[allFloat] RelatedInterval Interval 44: float (constant) RefPositions {#110@224 #112@225} physReg:NA Preferences=[allFloat] Interval 45: ref RefPositions {#119@248 #120@249} physReg:NA Preferences=[allInt] RelatedInterval Interval 46: ref RefPositions {#123@256 #125@257} physReg:NA Preferences=[rcx] Interval 47: ref RefPositions {#127@258 #141@277} physReg:NA Preferences=[rcx] Interval 48: int (specialPutArg) RefPositions {#131@262 #143@277} physReg:NA Preferences=[rdx] RelatedInterval Interval 49: int (specialPutArg) RefPositions {#135@266 #145@277} physReg:NA Preferences=[r8] RelatedInterval Interval 50: int RefPositions {#139@270 #147@277} physReg:NA Preferences=[r9] Interval 51: float RefPositions {#164@286 #165@287} physReg:NA Preferences=[allFloat] RelatedInterval Interval 52: int RefPositions {#168@296 #169@297} physReg:NA Preferences=[allInt] RelatedInterval Interval 53: float RefPositions {#178@318 #179@319} physReg:NA Preferences=[allFloat] RelatedInterval Interval 54: int RefPositions {#182@328 #183@329} physReg:NA Preferences=[allInt] RelatedInterval ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[mm2] minReg=1 fixed regOptional> BB00 regmask=[allFloat] minReg=1 regOptional> BB00 regmask=[mm1] minReg=1 fixed regOptional> BB00 regmask=[allFloat] minReg=1 regOptional> BB00 regmask=[mm3] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> LCL_VAR BB08 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB08 regmask=[allFloat] minReg=1> BB09 regmask=[rcx] minReg=1> LCL_VAR BB09 regmask=[rcx] minReg=1 fixed> BB09 regmask=[rcx] minReg=1> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rcx] minReg=1 last fixed> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[mm0] minReg=1 last> BB09 regmask=[mm1] minReg=1 last> BB09 regmask=[mm2] minReg=1 last> BB09 regmask=[mm3] minReg=1 last> BB09 regmask=[mm4] minReg=1 last> BB09 regmask=[mm5] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1> STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> CNS_INT BB03 regmask=[allInt] minReg=1> BB03 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB03 regmask=[allInt] minReg=1> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> BB04 regmask=[allFloat] minReg=1 last delay regOptional> SUB BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> LCL_FLD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> CNS_DBL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1> ADD BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB04 regmask=[allFloat] minReg=1> ADD BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> LCL_FLD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> LCL_VAR BB04 regmask=[allInt] minReg=1 last> ADD BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> MUL BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last regOptional> BB04 regmask=[allFloat] minReg=1 last> ADD BB04 regmask=[allFloat] minReg=1> BB04 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> CNS_DBL BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last regOptional> BB04 regmask=[allFloat] minReg=1 last> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional> BB05 regmask=[allFloat] minReg=1 regOptional> BB05 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rcx] minReg=1> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[r8] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 fixed> BB06 regmask=[r8] minReg=1> PUTARG_REG BB06 regmask=[r8] minReg=1 fixed> BB06 regmask=[r9] minReg=1> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> PUTARG_REG BB06 regmask=[r9] minReg=1 fixed> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rdx] minReg=1 last fixed> BB06 regmask=[r8] minReg=1> BB06 regmask=[r8] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> BB06 regmask=[r9] minReg=1 last fixed> LCL_VAR BB06 regmask=[allInt] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[mm0] minReg=1 last> BB06 regmask=[mm1] minReg=1 last> BB06 regmask=[mm2] minReg=1 last> BB06 regmask=[mm3] minReg=1 last> BB06 regmask=[mm4] minReg=1 last> BB06 regmask=[mm5] minReg=1 last> LCL_VAR BB06 regmask=[allFloat] minReg=1 last> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> ADD BB06 regmask=[allFloat] minReg=1> BB06 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last> ADD BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[allFloat] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB07 regmask=[allFloat] minReg=1 last> LCL_VAR BB07 regmask=[allFloat] minReg=1 regOptional> ADD BB07 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allFloat] minReg=1> LCL_VAR BB07 regmask=[allInt] minReg=1 last> ADD BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB09 regmask=[rcx] minReg=1 fixed> LCL_VAR BB06 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[mm1] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB02 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> --- V02 (Interval 2) BB00 regmask=[mm2] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> --- V03 (Interval 3) BB00 regmask=[mm3] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allFloat] minReg=1 last> --- V04 (Interval 4) BB00 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB08 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> --- V05 (Interval 5) BB00 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> --- V06 (Interval 6) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 fixed> LCL_VAR BB07 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> --- V07 (Interval 7) STORE_LCL_VAR BB01 regmask=[allFloat] minReg=1> LCL_VAR BB08 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB07 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB07 regmask=[allFloat] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> --- V08 (Interval 8) STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 fixed> LCL_VAR BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> --- V09 (Interval 9) STORE_LCL_VAR BB02 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allFloat] minReg=1> LCL_VAR BB06 regmask=[allFloat] minReg=1 regOptional> BB06 regmask=[allFloat] minReg=1 regOptional> --- V10 --- V11 --- V12 (Interval 10) STORE_LCL_VAR BB03 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> --- V13 (Interval 11) STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last regOptional> --- V14 --- V15 --- V16 (Interval 12) STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> --- V17 (Interval 13) STORE_LCL_VAR BB04 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1 last> --- V18 --- V19 --- V20 --- V21 --- V22 --- V23 (Interval 14) STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 regOptional> --- V24 (Interval 15) STORE_LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB03 regmask=[allFloat] minReg=1> LCL_VAR BB04 regmask=[allFloat] minReg=1> BB05 regmask=[allFloat] minReg=1 regOptional> --- V25 --- V26 --- V27 --- V28 --- V29 --- V30 --- V31 --- V32 --- V33 --- V34 --- V35 (Interval 16) STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ | |V0 a| | | | | | | | |V1 a|V2 a| | | 0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | | |V1 a|V2 a| | | 0.#1 V2 Parm Alloc mm6 | | | | | |V0 a| | | | |V1 a| |V2 a| | 0.#2 V5 Parm Alloc mm7 | | | | | |V0 a| | | | |V1 a| |V2 a|V5 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |mm8 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#3 V1 Parm Alloc mm8 | | | | | |V0 a| | | | | | |V2 a|V5 a|V1 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm6 |mm7 |mm8 |mm9 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#4 V4 Parm Alloc mm9 | | | | | |V0 a| | | | | | |V2 a|V5 a|V1 a|V4 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#5 V3 Parm Keep mm3 | | | | | |V0 a| | | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| 1.#6 BB1 PredBB0 | | | | | |V0 a| | | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| 6.#7 C17 Def Alloc rdi | | | | | |V0 a|C17a| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| 7.#8 C17 Use * Keep rdi | | | | | |V0 a|C17a| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| 8.#9 V6 Def Alloc rdi | | | | | |V0 a|V6 a| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| 13.#10 V3 Use * Keep mm3 | | | | | |V0 a|V6 a| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 14.#11 V7 Def Alloc mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 15.#12 BB8 PredBB1 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 23.#13 V7 Use Keep mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 23.#14 V4 Use Keep mm9 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 27.#15 BB9 PredBB8 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 31.#16 rcx Fixd Keep rcx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 31.#17 V0 Use Copy rcx | |V0 a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 32.#18 rcx Fixd Keep rcx | |V0 a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 32.#19 I18 Def Alloc rcx | |I18a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 33.#20 rcx Fixd Keep rcx | |I18a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 33.#21 I18 Use * Keep rcx | |I18a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#22 rax Kill Keep rax | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#23 rcx Kill Keep rcx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#24 rdx Kill Keep rdx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#25 r8 Kill Keep r8 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#26 r9 Kill Keep r9 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#27 r10 Kill Keep r10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#28 r11 Kill Keep r11 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#29 mm0 Kill Keep mm0 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#30 mm1 Kill Keep mm1 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#31 mm2 Kill Keep mm2 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#32 mm3 Kill Keep mm3 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#33 mm4 Kill Keep mm4 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#34 mm5 Kill Keep mm5 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#35 rax Fixd Keep rax | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 34.#36 I19 Def Alloc rax |I19a| | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 37.#37 I19 Use * Keep rax |I19a| | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 41.#38 BB2 PredBB9 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 46.#39 C20 Def Alloc rbx | | | |C20a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 47.#40 C20 Use * Keep rbx | | | |C20a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 48.#41 V8 Def Alloc rbx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| 53.#42 V1 Use Keep mm8 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 54.#43 V9 Def Alloc mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 61.#44 V1 Use Keep mm8 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 61.#45 V2 Use Keep mm6 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 65.#46 BB3 PredBB2 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 71.#47 V9 Use Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 72.#48 V23 Def Alloc mm0 | | | |V8 a| |V0 a|V6 a| | |V23a| | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 77.#49 V7 Use Keep mm10 | | | |V8 a| |V0 a|V6 a| | |V23a| | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 78.#50 V24 Def Alloc mm1 | | | |V8 a| |V0 a|V6 a| | |V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 83.#51 V23 Use Keep mm0 | | | |V8 a| |V0 a|V6 a| | |V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 87.#52 V24 Use Keep mm1 | | | |V8 a| |V0 a|V6 a| | |V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 92.#53 C21 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |C21a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 93.#54 C21 Use * Keep r9 | | | |V8 a| |V0 a|V6 a| |C21a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 94.#55 V12 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 95.#56 BB4 PredBB3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 100.#57 C22 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C22a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 101.#58 C22 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C22a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 104.#59 C23 Def Reuse mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C23a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 105.#60 C23 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C23a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 110.#61 I24 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I24a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 113.#62 I24 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I24a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 114.#63 I25 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 116.#64 I26 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I26a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 119.#65 I26 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I26a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 120.#66 I27 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I27a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 121.#67 I25 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I27a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 121.#68 I27 Use *D Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I27a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 122.#69 I28 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I28a|I27a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 123.#70 I28 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I28a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 124.#71 V16 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 128.#72 I29 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I29a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 131.#73 I29 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I29a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 132.#74 I30 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I30a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 135.#75 I30 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I30a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 136.#76 I31 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I31a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 137.#77 I31 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I31a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 138.#78 V17 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|V17a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 143.#79 V16 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|V17a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 149.#80 V17 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| |V17a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 152.#81 I32 Def Alloc rcx | |I32a| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 153.#82 I32 Use * Keep rcx | |I32a| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 162.#83 C33 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C33a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 163.#84 C33 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C33a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 166.#85 C34 Def Reuse mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C34a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 167.#86 C34 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C34a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 175.#87 V23 Use Keep mm0 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C34i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 176.#88 I35 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I35a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 177.#89 I35 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I35a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 185.#90 V24 Use Keep mm1 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 186.#91 I36 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I36a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 187.#92 I36 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I36a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 190.#93 I37 Def Alloc rcx | |I37a| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 191.#94 I37 Use * Keep rcx | |I37a| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 199.#95 V12 Use * Keep r9 | | | |V8 a| |V0 a|V6 a| |V12i|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 200.#96 I38 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |I38a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 201.#97 I38 Use * Keep r9 | | | |V8 a| |V0 a|V6 a| |I38a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| Restr r9 | | | |V8 a| |V0 a|V6 a| |V12i|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 202.#98 V12 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 204.#99 I39 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I39a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 207.#100 I39 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I39a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 208.#101 I40 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 210.#102 I41 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I41a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 213.#103 I41 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I41a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 214.#104 I42 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I42a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 215.#105 I40 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I42a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 215.#106 I42 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I42a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 216.#107 I43 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I43a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 217.#108 I43 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I43a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 218.#109 V13 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 224.#110 C44 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13a|C44a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 225.#111 V13 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13a|C44a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 225.#112 C44 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13a|C44a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 229.#113 BB5 PredBB4 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 237.#114 V12 Use Keep r9 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 241.#115 V23 ExpU Keep NA | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 241.#116 V24 ExpU Keep NA | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 241.#117 BB6 PredBB4 | | | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 247.#118 V0 Use Keep rsi | | | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 248.#119 I45 Def Alloc rax |I45a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 249.#120 I45 Use * Keep rax |I45a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 250.#121 V35 Def Alloc rax |V35a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 255.#122 V35 Use Keep rax |V35a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 256.#123 I46 Def Alloc rcx |V35a|I46a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 257.#124 rcx Fixd Keep rcx |V35a|I46a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 257.#125 I46 Use * Keep rcx |V35a|I46a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 258.#126 rcx Fixd Keep rcx |V35a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 258.#127 I47 Def Alloc rcx |V35a|I47a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 261.#128 rdx Fixd Keep rdx |V35a|I47a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 261.#129 V8 Use Copy rdx |V35a|I47a|V8 a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 262.#130 rdx Fixd Keep rdx |V35a|I47a|V8 a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 262.#131 I48 Def Alloc rdx |V35a|I47a|I48a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 265.#132 r8 Fixd Keep r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 265.#133 V6 Use Copy r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|V6 a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 266.#134 r8 Fixd Keep r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|V6 a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 266.#135 I49 Def Alloc r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 269.#136 r9 Fixd Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 269.#137 V12 Use * Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 270.#138 r9 Fixd Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a| | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 270.#139 I50 Def Alloc r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#140 rcx Fixd Keep rcx |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#141 I47 Use * Keep rcx |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#142 rdx Fixd Keep rdx |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#143 I48 Use * Keep rdx |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#144 r8 Fixd Keep r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#145 I49 Use * Keep r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#146 r9 Fixd Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#147 I50 Use * Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#148 V35 Use * Keep rax |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#149 rax Kill Keep rax | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#150 rcx Kill Keep rcx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#151 rdx Kill Keep rdx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#152 r8 Kill Keep r8 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#153 r9 Kill Keep r9 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#154 r10 Kill Keep r10 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#155 r11 Kill Keep r11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#156 mm0 Kill Keep mm0 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#157 mm1 Kill Keep mm1 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#158 mm2 Kill Keep mm2 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#159 mm3 Kill Keep mm3 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#160 mm4 Kill Keep mm4 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#161 mm5 Kill Keep mm5 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 285.#162 V9 Use * Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 i| 285.#163 V5 Use Keep mm7 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 i| 286.#164 I51 Def Alloc mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|I51a| 287.#165 I51 Use * Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|I51a| Restr mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 i| 288.#166 V9 Def Alloc mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 295.#167 V8 Use * Keep rbx | | | |V8 i| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 296.#168 I52 Def Alloc rbx | | | |I52a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 297.#169 I52 Use * Keep rbx | | | |I52a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| Restr rbx | | | |V8 i| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 298.#170 V8 Def Alloc rbx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 305.#171 V9 Use Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 305.#172 V2 Use Keep mm6 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 309.#173 V8 ExpU Keep NA | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 309.#174 V9 ExpU Keep NA | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 309.#175 BB7 PredBB6 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 317.#176 V7 Use * Keep mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 i| | 317.#177 V5 Use Keep mm7 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 i| | 318.#178 I53 Def Alloc mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|I53a| | 319.#179 I53 Use * Keep mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|I53a| | Restr mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 i| | 320.#180 V7 Def Alloc mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 327.#181 V6 Use * Keep rdi | | | | | |V0 a|V6 i| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 328.#182 I54 Def Alloc rdi | | | | | |V0 a|I54a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 329.#183 I54 Use * Keep rdi | | | | | |V0 a|I54a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | Restr rdi | | | | | |V0 a|V6 i| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 330.#184 V6 Def Alloc rdi | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#185 V0 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#186 V6 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#187 V7 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#188 V2 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#189 V5 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#190 V1 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#191 V4 ExpU Keep NA | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 331.#192 BB10 PredBB8 | | | | | | | | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rsi] minReg=1 fixed regOptional> BB00 regmask=[mm6] minReg=1 fixed regOptional> BB00 regmask=[mm7] minReg=1 regOptional> BB00 regmask=[mm8] minReg=1 fixed regOptional> BB00 regmask=[mm9] minReg=1 regOptional> BB00 regmask=[mm3] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[mm3] minReg=1 last> STORE_LCL_VAR BB01 regmask=[mm10] minReg=1> LCL_VAR BB08 regmask=[mm10] minReg=1 regOptional> LCL_VAR BB08 regmask=[mm9] minReg=1> BB09 regmask=[rcx] minReg=1> LCL_VAR BB09 regmask=[rcx] minReg=1 copy fixed> BB09 regmask=[rcx] minReg=1> PUTARG_REG BB09 regmask=[rcx] minReg=1 fixed> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rcx] minReg=1 last fixed> BB09 regmask=[rax] minReg=1 last> BB09 regmask=[rcx] minReg=1 last> BB09 regmask=[rdx] minReg=1 last> BB09 regmask=[r8] minReg=1 last> BB09 regmask=[r9] minReg=1 last> BB09 regmask=[r10] minReg=1 last> BB09 regmask=[r11] minReg=1 last> BB09 regmask=[mm0] minReg=1 last> BB09 regmask=[mm1] minReg=1 last> BB09 regmask=[mm2] minReg=1 last> BB09 regmask=[mm3] minReg=1 last> BB09 regmask=[mm4] minReg=1 last> BB09 regmask=[mm5] minReg=1 last> BB09 regmask=[rax] minReg=1> CALL BB09 regmask=[rax] minReg=1 fixed> BB09 regmask=[rax] minReg=1 last regOptional> CNS_INT BB02 regmask=[rbx] minReg=1> BB02 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB02 regmask=[rbx] minReg=1> LCL_VAR BB02 regmask=[mm8] minReg=1> STORE_LCL_VAR BB02 regmask=[mm11] minReg=1> LCL_VAR BB02 regmask=[mm8] minReg=1 regOptional> LCL_VAR BB02 regmask=[mm6] minReg=1> LCL_VAR BB03 regmask=[mm11] minReg=1> STORE_LCL_VAR BB03 regmask=[mm0] minReg=1> LCL_VAR BB03 regmask=[mm10] minReg=1> STORE_LCL_VAR BB03 regmask=[mm1] minReg=1> LCL_VAR BB03 regmask=[mm0] minReg=1> LCL_VAR BB03 regmask=[mm1] minReg=1> CNS_INT BB03 regmask=[r9] minReg=1> BB03 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB03 regmask=[r9] minReg=1> CNS_DBL BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> CNS_DBL BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> LCL_VAR BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> MUL BB04 regmask=[mm2] minReg=1> LCL_VAR BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm3] minReg=1 last> MUL BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm2] minReg=1 last> BB04 regmask=[mm3] minReg=1 last delay regOptional> SUB BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> STORE_LCL_VAR BB04 regmask=[mm2] minReg=1> LCL_VAR BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm3] minReg=1 last> MUL BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm3] minReg=1 last> MUL BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm3] minReg=1 last> STORE_LCL_VAR BB04 regmask=[mm3] minReg=1> LCL_VAR BB04 regmask=[mm2] minReg=1 last> LCL_VAR BB04 regmask=[mm3] minReg=1 last> LCL_FLD BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last> CNS_DBL BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> CNS_DBL BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> LCL_VAR BB04 regmask=[mm0] minReg=1> ADD BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> LCL_VAR BB04 regmask=[mm1] minReg=1> ADD BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> LCL_FLD BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last> LCL_VAR BB04 regmask=[r9] minReg=1 last> ADD BB04 regmask=[r9] minReg=1> BB04 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB04 regmask=[r9] minReg=1> LCL_VAR BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> MUL BB04 regmask=[mm2] minReg=1> LCL_VAR BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm3] minReg=1 last> MUL BB04 regmask=[mm3] minReg=1> BB04 regmask=[mm2] minReg=1 last regOptional> BB04 regmask=[mm3] minReg=1 last> ADD BB04 regmask=[mm2] minReg=1> BB04 regmask=[mm2] minReg=1 last> STORE_LCL_VAR BB04 regmask=[mm2] minReg=1> CNS_DBL BB04 regmask=[mm3] minReg=1> LCL_VAR BB04 regmask=[mm2] minReg=1 last regOptional> BB04 regmask=[mm3] minReg=1 last> LCL_VAR BB05 regmask=[r9] minReg=1 regOptional> BB05 regmask=[allFloat] minReg=1 regOptional> BB05 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB06 regmask=[rsi] minReg=1> IND BB06 regmask=[rax] minReg=1> BB06 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB06 regmask=[rax] minReg=1> LCL_VAR BB06 regmask=[rax] minReg=1> IND BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rcx] minReg=1> PUTARG_REG BB06 regmask=[rcx] minReg=1 fixed> BB06 regmask=[rdx] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 copy fixed> BB06 regmask=[rdx] minReg=1> PUTARG_REG BB06 regmask=[rdx] minReg=1 fixed> BB06 regmask=[r8] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 copy fixed> BB06 regmask=[r8] minReg=1> PUTARG_REG BB06 regmask=[r8] minReg=1 fixed> BB06 regmask=[r9] minReg=1> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> PUTARG_REG BB06 regmask=[r9] minReg=1 fixed> BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last fixed> BB06 regmask=[rdx] minReg=1> BB06 regmask=[rdx] minReg=1 last fixed> BB06 regmask=[r8] minReg=1> BB06 regmask=[r8] minReg=1 last fixed> BB06 regmask=[r9] minReg=1> BB06 regmask=[r9] minReg=1 last fixed> LCL_VAR BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rax] minReg=1 last> BB06 regmask=[rcx] minReg=1 last> BB06 regmask=[rdx] minReg=1 last> BB06 regmask=[r8] minReg=1 last> BB06 regmask=[r9] minReg=1 last> BB06 regmask=[r10] minReg=1 last> BB06 regmask=[r11] minReg=1 last> BB06 regmask=[mm0] minReg=1 last> BB06 regmask=[mm1] minReg=1 last> BB06 regmask=[mm2] minReg=1 last> BB06 regmask=[mm3] minReg=1 last> BB06 regmask=[mm4] minReg=1 last> BB06 regmask=[mm5] minReg=1 last> LCL_VAR BB06 regmask=[mm11] minReg=1 last> LCL_VAR BB06 regmask=[mm7] minReg=1 regOptional> ADD BB06 regmask=[mm11] minReg=1> BB06 regmask=[mm11] minReg=1 last> STORE_LCL_VAR BB06 regmask=[mm11] minReg=1> LCL_VAR BB06 regmask=[rbx] minReg=1 last> ADD BB06 regmask=[rbx] minReg=1> BB06 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB06 regmask=[rbx] minReg=1> LCL_VAR BB06 regmask=[mm11] minReg=1 regOptional> LCL_VAR BB06 regmask=[mm6] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> BB06 regmask=[allFloat] minReg=1 regOptional> LCL_VAR BB07 regmask=[mm10] minReg=1 last> LCL_VAR BB07 regmask=[mm7] minReg=1 regOptional> ADD BB07 regmask=[mm10] minReg=1> BB07 regmask=[mm10] minReg=1 last> STORE_LCL_VAR BB07 regmask=[mm10] minReg=1> LCL_VAR BB07 regmask=[rdi] minReg=1 last> ADD BB07 regmask=[rdi] minReg=1> BB07 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB07 regmask=[rdi] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allInt] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[rsi] minReg=1 fixed regOptional> LCL_VAR BB09 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB06 regmask=[rsi] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[mm8] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[mm8] minReg=1> LCL_VAR BB02 regmask=[mm8] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> --- V02 (Interval 2) BB00 regmask=[mm6] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[mm6] minReg=1> LCL_VAR BB06 regmask=[mm6] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> --- V03 (Interval 3) BB00 regmask=[mm3] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[mm3] minReg=1 last> --- V04 (Interval 4) BB00 regmask=[mm9] minReg=1 regOptional> LCL_VAR BB08 regmask=[mm9] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> --- V05 (Interval 5) BB00 regmask=[mm7] minReg=1 regOptional> LCL_VAR BB06 regmask=[mm7] minReg=1 regOptional> LCL_VAR BB07 regmask=[mm7] minReg=1 regOptional> BB07 regmask=[allFloat] minReg=1 regOptional> --- V06 (Interval 6) STORE_LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB06 regmask=[r8] minReg=1 copy fixed> LCL_VAR BB07 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB07 regmask=[rdi] minReg=1> BB07 regmask=[allInt] minReg=1 regOptional> --- V07 (Interval 7) STORE_LCL_VAR BB01 regmask=[mm10] minReg=1> LCL_VAR BB08 regmask=[mm10] minReg=1 regOptional> LCL_VAR BB03 regmask=[mm10] minReg=1> LCL_VAR BB07 regmask=[mm10] minReg=1 last> STORE_LCL_VAR BB07 regmask=[mm10] minReg=1> BB07 regmask=[allFloat] minReg=1 regOptional> --- V08 (Interval 8) STORE_LCL_VAR BB02 regmask=[rbx] minReg=1> LCL_VAR BB06 regmask=[rdx] minReg=1 copy fixed> LCL_VAR BB06 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB06 regmask=[rbx] minReg=1> BB06 regmask=[allInt] minReg=1 regOptional> --- V09 (Interval 9) STORE_LCL_VAR BB02 regmask=[mm11] minReg=1> LCL_VAR BB03 regmask=[mm11] minReg=1> LCL_VAR BB06 regmask=[mm11] minReg=1 last> STORE_LCL_VAR BB06 regmask=[mm11] minReg=1> LCL_VAR BB06 regmask=[mm11] minReg=1 regOptional> BB06 regmask=[allFloat] minReg=1 regOptional> --- V10 --- V11 --- V12 (Interval 10) STORE_LCL_VAR BB03 regmask=[r9] minReg=1> LCL_VAR BB04 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB04 regmask=[r9] minReg=1> LCL_VAR BB05 regmask=[r9] minReg=1 regOptional> LCL_VAR BB06 regmask=[r9] minReg=1 last fixed> --- V13 (Interval 11) STORE_LCL_VAR BB04 regmask=[mm2] minReg=1> LCL_VAR BB04 regmask=[mm2] minReg=1 last regOptional> --- V14 --- V15 --- V16 (Interval 12) STORE_LCL_VAR BB04 regmask=[mm2] minReg=1> LCL_VAR BB04 regmask=[mm2] minReg=1 last> --- V17 (Interval 13) STORE_LCL_VAR BB04 regmask=[mm3] minReg=1> LCL_VAR BB04 regmask=[mm3] minReg=1 last> --- V18 --- V19 --- V20 --- V21 --- V22 --- V23 (Interval 14) STORE_LCL_VAR BB03 regmask=[mm0] minReg=1> LCL_VAR BB03 regmask=[mm0] minReg=1> LCL_VAR BB04 regmask=[mm0] minReg=1> BB05 regmask=[allFloat] minReg=1 regOptional> --- V24 (Interval 15) STORE_LCL_VAR BB03 regmask=[mm1] minReg=1> LCL_VAR BB03 regmask=[mm1] minReg=1> LCL_VAR BB04 regmask=[mm1] minReg=1> BB05 regmask=[allFloat] minReg=1 regOptional> --- V25 --- V26 --- V27 --- V28 --- V29 --- V30 --- V31 --- V32 --- V33 --- V34 --- V35 (Interval 16) STORE_LCL_VAR BB06 regmask=[rax] minReg=1> LCL_VAR BB06 regmask=[rax] minReg=1> LCL_VAR BB06 regmask=[rax] minReg=1 last> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V23 V24} Has Critical Edges Prior to Resolution BB01 use def in out {V03} {V06 V07} {V00 V01 V02 V03 V04 V05} {V00 V01 V02 V04 V05 V06 V07} Var=Reg beg of BB01: V00=rsi V02=mm6 V05=mm7 V01=mm8 V04=mm9 V03=mm3 Var=Reg end of BB01: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB02 use def in out {V01 V02} {V08 V09} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07 V08 V09} Var=Reg beg of BB02: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB02: V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB03 use def in out {V07 V09} {V12 V23 V24} {V00 V01 V02 V04 V05 V06 V07 V08 V09} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Var=Reg beg of BB03: V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB03: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB04 use def in out {V12 V23 V24} {V12 V13 V16 V17} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Var=Reg beg of BB04: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB04: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB05 use def in out {V12} {} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Var=Reg beg of BB05: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB05: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB06 use def in out {V00 V02 V05 V06 V08 V09 V12} {V08 V09 V35} {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12} {V00 V01 V02 V04 V05 V06 V07 V08 V09} Var=Reg beg of BB06: V12=r9 V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB06: V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB07 use def in out {V05 V06 V07} {V06 V07} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07} Var=Reg beg of BB07: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB07: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB08 use def in out {V04 V07} {} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07} Var=Reg beg of BB08: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB08: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB09 use def in out {V00} {} {V00 V01 V02 V04 V05 V06 V07} {V00 V01 V02 V04 V05 V06 V07} Var=Reg beg of BB09: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 Var=Reg end of BB09: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB10 use def in out {} {} {} {} Var=Reg beg of BB10: none Var=Reg end of BB10: none RESOLVING EDGES Set V00 argument initial register to rsi Set V01 argument initial register to mm8 Set V02 argument initial register to mm6 Set V03 argument initial register to mm3 Set V04 argument initial register to mm9 Set V05 argument initial register to mm7 Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..006) -> BB08 (always), preds={} succs={BB08} N003 (???,???) [000294] ------------ IL_OFFSET void IL offset: 0x0 REG NA N005 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 REG rdi $40 /--* t0 int N007 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rdi REG rdi N009 (???,???) [000295] ------------ IL_OFFSET void IL offset: 0x2 REG NA N011 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 mm3 (last use) REG mm3 $c2 /--* t3 float N013 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 mm10 REG mm10 ------------ BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} N043 (???,???) [000296] ------------ IL_OFFSET void IL offset: 0x6 REG NA N045 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 REG rbx $40 /--* t17 int N047 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 rbx REG rbx N049 (???,???) [000297] ------------ IL_OFFSET void IL offset: 0x8 REG NA N051 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 mm8 REG mm8 $c0 /--* t20 float N053 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 mm11 REG mm11 N055 (???,???) [000298] ------------ IL_OFFSET void IL offset: 0x70 REG NA N057 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 mm8 REG mm8 $c0 N059 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 mm6 REG mm6 $c1 /--* t266 float +--* t267 float N061 ( 3, 5) [000265] N------N---- * GE void REG NA $2c2 N063 ( 5, 7) [000268] ------------ * JTRUE void REG NA ------------ BB03 [00C..023), preds={BB02,BB06} succs={BB04} N001 ( 0, 0) [000291] ------------ t291 = PHI_ARG float V09 loc3 u:4 mm11 N002 ( 0, 0) [000286] ------------ t286 = PHI_ARG float V09 loc3 u:2 mm11 $c0 /--* t291 float +--* t286 float N003 ( 0, 0) [000279] ------------ t279 = * PHI float /--* t279 float N005 ( 0, 0) [000280] DA---------- * STORE_LCL_VAR float V09 loc3 d:3 mm11 N001 ( 0, 0) [000292] ------------ t292 = PHI_ARG int V08 loc2 u:4 rbx N002 ( 0, 0) [000287] ------------ t287 = PHI_ARG int V08 loc2 u:2 rbx $40 /--* t292 int +--* t287 int N003 ( 0, 0) [000276] ------------ t276 = * PHI int /--* t276 int N005 ( 0, 0) [000277] DA---------- * STORE_LCL_VAR int V08 loc2 d:3 rbx N067 (???,???) [000299] ------------ IL_OFFSET void IL offset: 0xc REG NA N069 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 mm11 REG mm11 $201 /--* t29 float N071 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 mm0 REG mm0 N073 (???,???) [000300] ------------ IL_OFFSET void IL offset: 0xc REG NA N075 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 mm10 REG mm10 $200 /--* t30 float N077 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 mm1 REG mm1 N079 (???,???) [000301] ------------ IL_OFFSET void IL offset: 0x15 REG NA N081 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 mm0 REG mm0 $201 /--* t224 float N083 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 NA REG NA N085 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 mm1 REG mm1 $200 /--* t227 float N087 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 NA REG NA N089 (???,???) [000302] ------------ IL_OFFSET void IL offset: 0x19 REG NA N091 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 REG r9 $40 /--* t36 int N093 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 r9 REG r9 ------------ BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} N001 ( 0, 0) [000293] ------------ t293 = PHI_ARG int V12 loc6 u:4 r9 N002 ( 0, 0) [000290] ------------ t290 = PHI_ARG int V12 loc6 u:2 r9 $40 /--* t293 int +--* t290 int N003 ( 0, 0) [000282] ------------ t282 = * PHI int /--* t282 int N005 ( 0, 0) [000283] DA---------- * STORE_LCL_VAR int V12 loc6 d:3 r9 N097 (???,???) [000303] ------------ IL_OFFSET void IL offset: 0x23 REG NA N099 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 REG mm2 $100 /--* t231 float N101 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 NA REG NA N103 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 REG mm2 $100 /--* t234 float N105 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 NA REG NA N107 (???,???) [000304] ------------ IL_OFFSET void IL offset: 0x23 REG NA N109 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 mm2 REG mm2 $480 N111 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 NA REG NA $481 /--* t119 float +--* t122 float N113 ( 7, 8) [000123] ------------ t123 = * MUL float REG mm2 $1c1 N115 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 mm3 REG mm3 $482 N117 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 NA REG NA $483 /--* t126 float +--* t129 float N119 ( 7, 8) [000130] ------------ t130 = * MUL float REG mm3 $1c2 /--* t123 float +--* t130 float N121 ( 19, 20) [000131] ------------ t131 = * SUB float REG mm2 $1c3 /--* t131 float N123 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 mm2 REG mm2 N125 (???,???) [000305] ------------ IL_OFFSET void IL offset: 0x23 REG NA N127 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 mm3 REG mm3 $485 N129 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 REG NA $101 /--* t135 float +--* t132 float N131 ( 9, 10) [000136] ------------ t136 = * MUL float REG mm3 $1c4 N133 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 NA REG NA $486 /--* t136 float +--* t139 float N135 ( 15, 16) [000140] ------------ t140 = * MUL float REG mm3 $1c5 /--* t140 float N137 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 mm3 REG mm3 N139 (???,???) [000306] ------------ IL_OFFSET void IL offset: 0x23 REG NA N141 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 mm2 (last use) REG mm2 $1c3 /--* t151 float N143 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 NA REG NA N145 (???,???) [000307] ------------ IL_OFFSET void IL offset: 0x23 REG NA N147 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 mm3 (last use) REG mm3 $1c5 /--* t156 float N149 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 NA REG NA N151 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] rcx * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 REG rcx $4c0 /--* t147 long N153 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] NA * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 REG NA N155 (???,???) [000308] ------------ IL_OFFSET void IL offset: 0x2c REG NA N157 (???,???) [000309] ------------ IL_OFFSET void IL offset: 0x2c REG NA N159 (???,???) [000310] ------------ IL_OFFSET void IL offset: 0x2c REG NA N161 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 REG mm2 $100 /--* t252 float N163 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 NA REG NA N165 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 REG mm2 $100 /--* t255 float N167 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 NA REG NA N169 (???,???) [000311] ------------ IL_OFFSET void IL offset: 0x2c REG NA N171 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 NA REG NA $488 N173 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 mm0 REG mm0 $201 /--* t166 float +--* t169 float N175 ( 7, 8) [000170] ------------ t170 = * ADD float REG mm2 $1c6 /--* t170 float N177 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 NA REG NA N179 (???,???) [000312] ------------ IL_OFFSET void IL offset: 0x2c REG NA N181 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 NA REG NA $489 N183 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 mm1 REG mm1 $200 /--* t173 float +--* t176 float N185 ( 7, 8) [000177] ------------ t177 = * ADD float REG mm2 $1c7 /--* t177 float N187 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 NA REG NA N189 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] rcx * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 REG rcx $4c1 /--* t184 long N191 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] NA * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 REG NA N193 (???,???) [000313] ------------ IL_OFFSET void IL offset: 0x37 REG NA N195 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 r9 (last use) REG r9 $242 N197 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 REG NA $41 /--* t62 int +--* t63 int N199 ( 3, 3) [000064] ------------ t64 = * ADD int REG r9 $2c3 /--* t64 int N201 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 r9 REG r9 N203 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 mm2 REG mm2 $48a N205 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 NA REG NA $48b /--* t205 float +--* t208 float N207 ( 7, 8) [000209] ------------ t209 = * MUL float REG mm2 $1c8 N209 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 mm3 REG mm3 $48c N211 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 NA REG NA $48d /--* t212 float +--* t215 float N213 ( 7, 8) [000216] ------------ t216 = * MUL float REG mm3 $1c9 /--* t209 float +--* t216 float N215 ( 19, 20) [000217] ------------ t217 = * ADD float REG mm2 $1ca /--* t217 float N217 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 mm2 REG mm2 N219 (???,???) [000314] ------------ IL_OFFSET void IL offset: 0x46 REG NA N221 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 mm2 (last use) REG mm2 $1ca N223 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 REG mm3 $102 /--* t73 float +--* t74 float N225 ( 5, 7) [000075] N------N-U-- * GE void REG NA $2c4 N227 ( 7, 9) [000076] ------------ * JTRUE void REG NA ------------ BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} N231 (???,???) [000315] ------------ IL_OFFSET void IL offset: 0x4f REG NA N233 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 r9 REG r9 $2c3 N235 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 REG NA $47 /--* t94 int +--* t95 int N237 ( 3, 6) [000096] J------N---- * LT void REG NA $2c5 N239 ( 5, 8) [000097] ------------ * JTRUE void REG NA ------------ BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} N243 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 rsi REG rsi $80 /--* t77 ref N245 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref REG NA /--* t259 byref N247 ( 4, 4) [000219] ---XG------- t219 = * IND ref REG rax /--* t219 ref N249 (???,???) [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 rax REG rax N251 (???,???) [000329] ------------ t329 = LCL_VAR ref V35 rat0 rax REG rax /--* t329 ref N253 (???,???) [000330] -c---------- t330 = * LEA(b+8) byref REG NA /--* t330 byref N255 (???,???) [000331] ------------ t331 = * IND ref REG rcx /--* t331 ref N257 (???,???) [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx N259 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 rbx REG rbx $241 /--* t80 int N261 (???,???) [000324] ------------ t324 = * PUTARG_REG int REG rdx N263 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 rdi REG rdi $240 /--* t81 int N265 (???,???) [000325] ------------ t325 = * PUTARG_REG int REG r8 N267 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 r9 (last use) REG r9 $2c3 /--* t82 int N269 (???,???) [000326] ------------ t326 = * PUTARG_REG int REG r9 N271 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 rax (last use) REG rax /--* t332 ref N273 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref REG NA /--* t333 ref N275 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr N277 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke REG NA $VN.Void N279 (???,???) [000316] ------------ IL_OFFSET void IL offset: 0x67 REG NA N281 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 mm11 (last use) REG mm11 $201 N283 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 mm7 REG mm7 $c4 /--* t84 float +--* t85 float N285 ( 7, 8) [000086] ------------ t86 = * ADD float REG mm11 $1cb /--* t86 float N287 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 mm11 REG mm11 N289 (???,???) [000317] ------------ IL_OFFSET void IL offset: 0x6c REG NA N291 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 rbx (last use) REG rbx $241 N293 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 REG NA $41 /--* t89 int +--* t90 int N295 ( 3, 3) [000091] ------------ t91 = * ADD int REG rbx $2c6 /--* t91 int N297 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 rbx REG rbx N299 (???,???) [000318] ------------ IL_OFFSET void IL offset: 0x70 REG NA N301 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 mm11 REG mm11 $1cb N303 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 mm6 REG mm6 $c1 /--* t23 float +--* t24 float N305 ( 3, 5) [000025] J------N---- * LT void REG NA $2c7 N307 ( 5, 7) [000026] ------------ * JTRUE void REG NA ------------ BB07 [074..07D), preds={BB02,BB06} succs={BB08} N311 (???,???) [000319] ------------ IL_OFFSET void IL offset: 0x74 REG NA N313 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 mm10 (last use) REG mm10 $200 N315 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 mm7 REG mm7 $c4 /--* t98 float +--* t99 float N317 ( 7, 8) [000100] ------------ t100 = * ADD float REG mm10 $1cc /--* t100 float N319 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 mm10 REG mm10 N321 (???,???) [000320] ------------ IL_OFFSET void IL offset: 0x79 REG NA N323 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 rdi (last use) REG rdi $240 N325 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 REG NA $41 /--* t103 int +--* t104 int N327 ( 3, 3) [000105] ------------ t105 = * ADD int REG rdi $2c8 /--* t105 int N329 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 rdi REG rdi ------------ BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} N001 ( 0, 0) [000288] ------------ t288 = PHI_ARG float V07 loc1 u:4 mm10 N002 ( 0, 0) [000284] ------------ t284 = PHI_ARG float V07 loc1 u:2 mm10 $c2 /--* t288 float +--* t284 float N003 ( 0, 0) [000273] ------------ t273 = * PHI float /--* t273 float N005 ( 0, 0) [000274] DA---------- * STORE_LCL_VAR float V07 loc1 d:3 mm10 N001 ( 0, 0) [000289] ------------ t289 = PHI_ARG int V06 loc0 u:4 rdi N002 ( 0, 0) [000285] ------------ t285 = PHI_ARG int V06 loc0 u:2 rdi $40 /--* t289 int +--* t285 int N003 ( 0, 0) [000270] ------------ t270 = * PHI int /--* t270 int N005 ( 0, 0) [000271] DA---------- * STORE_LCL_VAR int V06 loc0 d:3 rdi N017 (???,???) [000321] ------------ IL_OFFSET void IL offset: 0x7d REG NA N019 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 mm10 REG mm10 $200 N021 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 mm9 REG mm9 $c3 /--* t6 float +--* t7 float N023 ( 3, 5) [000008] N------N-U-- * GE void REG NA $2c0 N025 ( 5, 7) [000009] ------------ * JTRUE void REG NA ------------ BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} N029 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 rsi REG rsi $80 /--* t11 ref N031 (???,???) [000335] ------------ t335 = * PUTARG_REG ref REG rcx /--* t335 ref this in rcx N033 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort REG rax $300 N035 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 REG NA $40 /--* t12 int +--* t14 int N037 ( 17, 10) [000015] J--XG--N---- * EQ void REG NA $2c1 N039 ( 19, 12) [000016] ---XG------- * JTRUE void REG NA ------------ BB10 [08D..08E) (return), preds={BB08,BB09} succs={} N333 (???,???) [000322] ------------ IL_OFFSET void IL offset: 0x8d REG NA N335 ( 0, 0) [000010] ------------ RETURN void REG NA $380 ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | | | | | | | | | | | | 0.#1 V2 Parm Alloc mm6 | | | | | |V0 a| | | | | | | |V2 a| | | | | | 0.#2 V5 Parm Alloc mm7 | | | | | |V0 a| | | | | | | |V2 a|V5 a| | | | | 0.#3 V1 Parm Alloc mm8 | | | | | |V0 a| | | | | | | |V2 a|V5 a|V1 a| | | | 0.#4 V4 Parm Alloc mm9 | | | | | |V0 a| | | | | | | |V2 a|V5 a|V1 a|V4 a| | | 0.#5 V3 Parm Alloc mm3 | | | | | |V0 a| | | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| | | 1.#6 BB1 PredBB0 | | | | | |V0 a| | | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| | | 6.#7 C17 Def Alloc rdi | | | | | |V0 a|C17a| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| | | 7.#8 C17 Use * Keep rdi | | | | | |V0 a|C17i| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| | | 8.#9 V6 Def Alloc rdi | | | | | |V0 a|V6 a| | | | | |V3 a|V2 a|V5 a|V1 a|V4 a| | | 13.#10 V3 Use * Keep mm3 | | | | | |V0 a|V6 a| | | | | |V3 i|V2 a|V5 a|V1 a|V4 a| | | 14.#11 V7 Def Alloc mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 15.#12 BB8 PredBB1 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 23.#13 V7 Use Keep mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 23.#14 V4 Use Keep mm9 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 27.#15 BB9 PredBB8 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 31.#16 rcx Fixd Keep rcx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 31.#17 V0 Use Copy rcx | |V0 a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 32.#18 rcx Fixd Keep rcx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 32.#19 I18 Def Alloc rcx | |I18a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 33.#20 rcx Fixd Keep rcx | |I18a| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 33.#21 I18 Use * Keep rcx | |I18i| | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#22 rax Kill Keep rax | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#23 rcx Kill Keep rcx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#24 rdx Kill Keep rdx | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#25 r8 Kill Keep r8 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#26 r9 Kill Keep r9 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#27 r10 Kill Keep r10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#28 r11 Kill Keep r11 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#29 mm0 Kill Keep mm0 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#30 mm1 Kill Keep mm1 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#31 mm2 Kill Keep mm2 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#32 mm3 Kill Keep mm3 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#33 mm4 Kill Keep mm4 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#34 mm5 Kill Keep mm5 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#35 rax Fixd Keep rax | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 34.#36 I19 Def Alloc rax |I19a| | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 37.#37 I19 Use * Keep rax |I19i| | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 41.#38 BB2 PredBB9 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 46.#39 C20 Def Alloc rbx | | | |C20a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 47.#40 C20 Use * Keep rbx | | | |C20i| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 48.#41 V8 Def Alloc rbx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 53.#42 V1 Use Keep mm8 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 54.#43 V9 Def Alloc mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 61.#44 V1 Use Keep mm8 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 61.#45 V2 Use Keep mm6 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 65.#46 BB3 PredBB2 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 71.#47 V9 Use Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 72.#48 V23 Def Alloc mm0 | | | |V8 a| |V0 a|V6 a| | |V23a| | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 77.#49 V7 Use Keep mm10 | | | |V8 a| |V0 a|V6 a| | |V23a| | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 78.#50 V24 Def Alloc mm1 | | | |V8 a| |V0 a|V6 a| | |V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 83.#51 V23 Use Keep mm0 | | | |V8 a| |V0 a|V6 a| | |V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 87.#52 V24 Use Keep mm1 | | | |V8 a| |V0 a|V6 a| | |V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 92.#53 C21 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |C21a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 93.#54 C21 Use * Keep r9 | | | |V8 a| |V0 a|V6 a| |C21i|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 94.#55 V12 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 95.#56 BB4 PredBB3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 100.#57 C22 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C22a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 101.#58 C22 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C22i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 104.#59 C23 Def Reuse mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C23a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 105.#60 C23 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C23i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 110.#61 I24 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I24a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 113.#62 I24 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I24i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 114.#63 I25 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 116.#64 I26 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I26a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 119.#65 I26 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I26i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 120.#66 I27 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25a|I27a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 121.#67 I25 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I25i|I27a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 121.#68 I27 Use *D Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| |I27i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 122.#69 I28 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I28a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 123.#70 I28 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I28i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 124.#71 V16 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 128.#72 I29 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I29a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 131.#73 I29 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I29i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 132.#74 I30 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I30a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 135.#75 I30 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I30i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 136.#76 I31 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I31a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 137.#77 I31 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|I31i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 138.#78 V17 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16a|V17a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 143.#79 V16 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V16i|V17a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 149.#80 V17 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| |V17i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 152.#81 I32 Def Alloc rcx | |I32a| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 153.#82 I32 Use * Keep rcx | |I32i| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 162.#83 C33 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C33a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 163.#84 C33 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C33i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 166.#85 C34 Def Reuse mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C34a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 167.#86 C34 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|C34i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 175.#87 V23 Use Keep mm0 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 176.#88 I35 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I35a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 177.#89 I35 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I35i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 185.#90 V24 Use Keep mm1 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 186.#91 I36 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I36a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 187.#92 I36 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I36i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 190.#93 I37 Def Alloc rcx | |I37a| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 191.#94 I37 Use * Keep rcx | |I37i| |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 199.#95 V12 Use * Keep r9 | | | |V8 a| |V0 a|V6 a| |V12i|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 200.#96 I38 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |I38a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 201.#97 I38 Use * Keep r9 | | | |V8 a| |V0 a|V6 a| |I38i|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 202.#98 V12 Def Alloc r9 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 204.#99 I39 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I39a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 207.#100 I39 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I39i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 208.#101 I40 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 210.#102 I41 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I41a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 213.#103 I41 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I41i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 214.#104 I42 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40a|I42a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 215.#105 I40 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I40i|I42a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 215.#106 I42 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| |I42i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 216.#107 I43 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I43a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 217.#108 I43 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|I43i| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 218.#109 V13 Def Alloc mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13a| |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 224.#110 C44 Def Alloc mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13a|C44a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 225.#111 V13 Use * Keep mm2 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a|V13i|C44a|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 225.#112 C44 Use * Keep mm3 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| |C44i|V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 229.#113 BB5 PredBB4 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 237.#114 V12 Use Keep r9 | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 241.#115 V23 ExpU | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 241.#116 V24 ExpU | | | |V8 a| |V0 a|V6 a| |V12a|V23a|V24a| | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 241.#117 BB6 PredBB4 | | | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 247.#118 V0 Use Keep rsi | | | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 248.#119 I45 Def Alloc rax |I45a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 249.#120 I45 Use * Keep rax |I45i| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 250.#121 V35 Def Alloc rax |V35a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 255.#122 V35 Use Keep rax |V35a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 256.#123 I46 Def Alloc rcx |V35a|I46a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 257.#124 rcx Fixd Keep rcx |V35a|I46a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 257.#125 I46 Use * Keep rcx |V35a|I46i| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 258.#126 rcx Fixd Keep rcx |V35a| | |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 258.#127 I47 Def Alloc rcx |V35a|I47a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 261.#128 rdx Fixd Keep rdx |V35a|I47a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 261.#129 V8 Use Copy rdx |V35a|I47a|V8 a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 262.#130 rdx Fixd Keep rdx |V35a|I47a| |V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 262.#131 I48 Def Alloc rdx |V35a|I47a|I48a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 265.#132 r8 Fixd Keep r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 265.#133 V6 Use Copy r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|V6 a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 266.#134 r8 Fixd Keep r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a| |V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 266.#135 I49 Def Alloc r8 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 269.#136 r9 Fixd Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|V12a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 269.#137 V12 Use * Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|V12i| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 270.#138 r9 Fixd Keep r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a| | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 270.#139 I50 Def Alloc r9 |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#140 rcx Fixd Keep rcx |V35a|I47a|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#141 I47 Use * Keep rcx |V35a|I47i|I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#142 rdx Fixd Keep rdx |V35a| |I48a|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#143 I48 Use * Keep rdx |V35a| |I48i|V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#144 r8 Fixd Keep r8 |V35a| | |V8 a| |V0 a|V6 a|I49a|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#145 I49 Use * Keep r8 |V35a| | |V8 a| |V0 a|V6 a|I49i|I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#146 r9 Fixd Keep r9 |V35a| | |V8 a| |V0 a|V6 a| |I50a| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#147 I50 Use * Keep r9 |V35a| | |V8 a| |V0 a|V6 a| |I50i| | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 277.#148 V35 Use * Keep rax |V35i| | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#149 rax Kill Keep rax | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#150 rcx Kill Keep rcx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#151 rdx Kill Keep rdx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#152 r8 Kill Keep r8 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#153 r9 Kill Keep r9 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#154 r10 Kill Keep r10 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#155 r11 Kill Keep r11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#156 mm0 Kill Keep mm0 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#157 mm1 Kill Keep mm1 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#158 mm2 Kill Keep mm2 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#159 mm3 Kill Keep mm3 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#160 mm4 Kill Keep mm4 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 278.#161 mm5 Kill Keep mm5 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 285.#162 V9 Use * Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 i| 285.#163 V5 Use Keep mm7 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 286.#164 I51 Def Alloc mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|I51a| 287.#165 I51 Use * Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|I51i| 288.#166 V9 Def Alloc mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 295.#167 V8 Use * Keep rbx | | | |V8 i| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 296.#168 I52 Def Alloc rbx | | | |I52a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 297.#169 I52 Use * Keep rbx | | | |I52i| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 298.#170 V8 Def Alloc rbx | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 305.#171 V9 Use Keep mm11 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 305.#172 V2 Use Keep mm6 | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 309.#173 V8 ExpU | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| 309.#174 V9 ExpU | | | |V8 a| |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a|V9 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 309.#175 BB7 PredBB6 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 317.#176 V7 Use * Keep mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 i| | 317.#177 V5 Use Keep mm7 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a| | | 318.#178 I53 Def Alloc mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|I53a| | 319.#179 I53 Use * Keep mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|I53i| | 320.#180 V7 Def Alloc mm10 | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 327.#181 V6 Use * Keep rdi | | | | | |V0 a|V6 i| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 328.#182 I54 Def Alloc rdi | | | | | |V0 a|I54a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 329.#183 I54 Use * Keep rdi | | | | | |V0 a|I54i| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 330.#184 V6 Def Alloc rdi | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#185 V0 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#186 V6 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#187 V7 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#188 V2 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#189 V5 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#190 V1 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | 331.#191 V4 ExpU | | | | | |V0 a|V6 a| | | | | | |V2 a|V5 a|V1 a|V4 a|V7 a| | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |mm0 |mm1 |mm2 |mm3 |mm6 |mm7 |mm8 |mm9 |mm10|mm11| --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ 331.#192 BB10 PredBB8 | | | | | | | | | | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 17 Total Reg Cand Vars: 17 Total number of Intervals: 54 Total number of RefPositions: 192 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rcx=>rsi) V02(mm2=>mm6) V05(STK=>mm7) V01(mm1=>mm8) V04(STK=>mm9) V03(mm3) BB01 [000..006) -> BB08 (always), preds={} succs={BB08} ===== N003. IL_OFFSET IL offset: 0x0 N005. rdi = CNS_INT 0 * N007. V06(rdi); rdi N009. IL_OFFSET IL offset: 0x2 N011. V03(mm3*) * N013. V07(mm10); mm3* Var=Reg end of BB01: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB08: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N017. IL_OFFSET IL offset: 0x7d N019. V07(mm10) N021. V04(mm9) N023. GE ; mm10,mm9 N025. JTRUE Var=Reg end of BB08: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB09: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N029. V00(rsi) N031. rcx = PUTARG_REG; rsi N033. rax = CALL ; rcx N035. CNS_INT 0 N037. EQ ; rax N039. JTRUE Var=Reg end of BB09: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB02: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N043. IL_OFFSET IL offset: 0x6 N045. rbx = CNS_INT 0 * N047. V08(rbx); rbx N049. IL_OFFSET IL offset: 0x8 N051. V01(mm8) * N053. V09(mm11); mm8 N055. IL_OFFSET IL offset: 0x70 N057. V01(mm8) N059. V02(mm6) N061. GE ; mm8,mm6 N063. JTRUE Var=Reg end of BB02: V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB03 [00C..023), preds={BB02,BB06} succs={BB04} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N067. IL_OFFSET IL offset: 0xc N069. V09(mm11) * N071. V23(mm0); mm11 N073. IL_OFFSET IL offset: 0xc N075. V07(mm10) * N077. V24(mm1); mm10 N079. IL_OFFSET IL offset: 0x15 N081. V23(mm0) N083. V25 MEM; mm0 N085. V24(mm1) N087. V26 MEM; mm1 N089. IL_OFFSET IL offset: 0x19 N091. r9 = CNS_INT 0 * N093. V12(r9); r9 Var=Reg end of BB03: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB04: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N097. IL_OFFSET IL offset: 0x23 N099. mm2 = CNS_DBL 0.00000000000000000 N101. V27 MEM; mm2 N103. mm2 = CNS_DBL 0.00000000000000000 N105. V28 MEM; mm2 N107. IL_OFFSET IL offset: 0x23 N109. mm2 = V25 MEM N111. V25 MEM N113. mm2 = MUL ; mm2 N115. mm3 = V26 MEM N117. V26 MEM N119. mm3 = MUL ; mm3 N121. mm2 = SUB ; mm2,mm3 * N123. V16(mm2); mm2 N125. IL_OFFSET IL offset: 0x23 N127. mm3 = V25 MEM N129. CNS_DBL 2.0000000000000000 N131. mm3 = MUL ; mm3 N133. V26 MEM N135. mm3 = MUL ; mm3 * N137. V17(mm3); mm3 N139. IL_OFFSET IL offset: 0x23 N141. V16(mm2*) N143. V27 MEM; mm2* N145. IL_OFFSET IL offset: 0x23 N147. V17(mm3*) N149. V28 MEM; mm3* N151. rcx = V15 MEM N153. V11 MEM; rcx N155. IL_OFFSET IL offset: 0x2c N157. IL_OFFSET IL offset: 0x2c N159. IL_OFFSET IL offset: 0x2c N161. mm2 = CNS_DBL 0.00000000000000000 N163. V33 MEM; mm2 N165. mm2 = CNS_DBL 0.00000000000000000 N167. V34 MEM; mm2 N169. IL_OFFSET IL offset: 0x2c N171. V25 MEM N173. V23(mm0) N175. mm2 = ADD ; mm0 N177. V33 MEM; mm2 N179. IL_OFFSET IL offset: 0x2c N181. V26 MEM N183. V24(mm1) N185. mm2 = ADD ; mm1 N187. V34 MEM; mm2 N189. rcx = V20 MEM N191. V11 MEM; rcx N193. IL_OFFSET IL offset: 0x37 N195. V12(r9*) N197. CNS_INT 1 N199. r9 = ADD ; r9* * N201. V12(r9); r9 N203. mm2 = V25 MEM N205. V25 MEM N207. mm2 = MUL ; mm2 N209. mm3 = V26 MEM N211. V26 MEM N213. mm3 = MUL ; mm3 N215. mm2 = ADD ; mm2,mm3 * N217. V13(mm2); mm2 N219. IL_OFFSET IL offset: 0x46 N221. V13(mm2*) N223. mm3 = CNS_DBL 4.0000000000000000 N225. GE ; mm2*,mm3 N227. JTRUE Var=Reg end of BB04: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N231. IL_OFFSET IL offset: 0x4f N233. V12(r9) N235. CNS_INT 0x3E8 N237. LT ; r9 N239. JTRUE Var=Reg end of BB05: V12=r9 V08=rbx V00=rsi V06=rdi V23=mm0 V24=mm1 V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB06: V12=r9 V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N243. V00(rsi) N245. STK = LEA(b+16); rsi N247. rax = IND ; STK * N249. V35(rax); rax N251. V35(rax) N253. STK = LEA(b+8) ; rax N255. rcx = IND ; STK N257. rcx = PUTARG_REG; rcx N259. V08(rbx) N261. rdx = PUTARG_REG; rbx N263. V06(rdi) N265. r8 = PUTARG_REG; rdi N267. V12(r9*) N269. r9 = PUTARG_REG; r9* N271. V35(rax*) N273. STK = LEA(b+24); rax* N275. STK = IND ; STK N277. CALL ; rcx,rdx,r8,r9,STK N279. IL_OFFSET IL offset: 0x67 N281. V09(mm11*) N283. V05(mm7) N285. mm11 = ADD ; mm11*,mm7 * N287. V09(mm11); mm11 N289. IL_OFFSET IL offset: 0x6c N291. V08(rbx*) N293. CNS_INT 1 N295. rbx = ADD ; rbx* * N297. V08(rbx); rbx N299. IL_OFFSET IL offset: 0x70 N301. V09(mm11) N303. V02(mm6) N305. LT ; mm11,mm6 N307. JTRUE Var=Reg end of BB06: V08=rbx V00=rsi V06=rdi V09=mm11 V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB07 [074..07D), preds={BB02,BB06} succs={BB08} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 N311. IL_OFFSET IL offset: 0x74 N313. V07(mm10*) N315. V05(mm7) N317. mm10 = ADD ; mm10*,mm7 * N319. V07(mm10); mm10 N321. IL_OFFSET IL offset: 0x79 N323. V06(rdi*) N325. CNS_INT 1 N327. rdi = ADD ; rdi* * N329. V06(rdi); rdi Var=Reg end of BB07: V00=rsi V06=rdi V07=mm10 V02=mm6 V05=mm7 V01=mm8 V04=mm9 BB10 [08D..08E) (return), preds={BB08,BB09} succs={} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB10: none N333. IL_OFFSET IL offset: 0x8d N335. RETURN Var=Reg end of BB10: none *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..006)-> BB08 (always) i label target LIR BB02 [0001] 1 BB09 2 0 [006..00C)-> BB07 ( cond ) i Loop Loop1 label target gcsafe bwd LIR BB03 [0002] 2 BB02,BB06 16 1 [00C..023) i Loop Loop1 label target gcsafe bwd LIR BB04 [0003] 2 BB03,BB05 128 2 [023..04F)-> BB06 ( cond ) i Loop Loop0 label target bwd LIR BB05 [0004] 1 BB04 64 2 [04F..058)-> BB04 ( cond ) i bwd LIR BB06 [0005] 2 BB04,BB05 16 1 [058..074)-> BB03 ( cond ) i label target gcsafe bwd LIR BB07 [0007] 2 BB02,BB06 2 0 [074..07D) i label target gcsafe bwd LIR BB08 [0008] 2 BB01,BB07 8 0 [07D..082)-> BB10 ( cond ) i label target bwd LIR BB09 [0009] 1 BB08 4 0 [082..08D)-> BB02 ( cond ) i gcsafe bwd LIR BB10 [0010] 2 BB08,BB09 1 [08D..08E) (return) i label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rsi) V02(mm6) V05(mm7) V01(mm8) V04(mm9) V03(mm3) Modified regs: [rax rcx rdx rbx rsi rdi r8-r11 mm0-mm11] Callee-saved registers pushed: 3 [rbx rsi rdi] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V11 loc5, size=8, stkOffs=-0x88 Assign V15 tmp1, size=8, stkOffs=-0x90 Assign V20 tmp6, size=8, stkOffs=-0x98 Assign V14 OutArgs, size=32, stkOffs=-0xb8 ; Final local variable assignments ; ; V00 this [V00,T03] ( 4, 22 ) ref -> rsi this class-hnd ; V01 arg1 [V01,T14] ( 4, 6 ) float -> mm8 ; V02 arg2 [V02,T12] ( 4, 20 ) float -> mm6 ; V03 arg3 [V03,T16] ( 3, 3 ) float -> mm3 ; V04 arg4 [V04,T15] ( 1, 8 ) float -> mm9 ; V05 arg5 [V05,T13] ( 2, 18 ) float -> mm7 ; V06 loc0 [V06,T04] ( 4, 21 ) int -> rdi ; V07 loc1 [V07,T11] ( 5, 29 ) float -> mm10 ; V08 loc2 [V08,T02] ( 4, 50 ) int -> rbx ; V09 loc3 [V09,T10] ( 5, 66 ) float -> mm11 ;* V10 loc4 [V10 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op ; V11 loc5 [V11 ] ( 16,1824 ) struct ( 8) [rsp+0x38] do-not-enreg[SF] must-init ld-addr-op ; V12 loc6 [V12,T00] ( 5, 352 ) int -> r9 ; V13 loc7 [V13,T07] ( 2, 256 ) float -> mm2 ; V14 OutArgs [V14 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace" ; V15 tmp1 [V15 ] ( 5,1280 ) struct ( 8) [rsp+0x30] do-not-enreg[SF] "NewObj constructor temp" ; V16 tmp2 [V16,T05] ( 2, 512 ) float -> mm2 "Inlining Arg" ; V17 tmp3 [V17,T06] ( 2, 512 ) float -> mm3 "Inlining Arg" ;* V18 tmp4 [V18 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" ;* V19 tmp5 [V19 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" ; V20 tmp6 [V20 ] ( 5,1280 ) struct ( 8) [rsp+0x28] do-not-enreg[SF] "NewObj constructor temp" ;* V21 tmp7 [V21 ] ( 0, 0 ) float -> zero-ref "Inlining Arg" ;* V22 tmp8 [V22 ] ( 0, 0 ) float -> zero-ref "Inlining Arg" ; V23 tmp9 [V23,T08] ( 3, 160 ) float -> mm0 V10.Real(offs=0x00) P-INDEP "field V10.Real (fldOffset=0x0)" ; V24 tmp10 [V24,T09] ( 3, 160 ) float -> mm1 V10.Imaginary(offs=0x04) P-INDEP "field V10.Imaginary (fldOffset=0x4)" ; V25 tmp11 [V25 ] ( 9,1040 ) float -> [rsp+0x38] do-not-enreg[] V11.Real(offs=0x00) P-DEP "field V11.Real (fldOffset=0x0)" ; V26 tmp12 [V26 ] ( 9,1040 ) float -> [rsp+0x3C] do-not-enreg[] V11.Imaginary(offs=0x04) P-DEP "field V11.Imaginary (fldOffset=0x4)" ; V27 tmp13 [V27 ] ( 3, 512 ) float -> [rsp+0x30] do-not-enreg[] V15.Real(offs=0x00) P-DEP "field V15.Real (fldOffset=0x0)" ; V28 tmp14 [V28 ] ( 3, 512 ) float -> [rsp+0x34] do-not-enreg[] V15.Imaginary(offs=0x04) P-DEP "field V15.Imaginary (fldOffset=0x4)" ;* V29 tmp15 [V29 ] ( 0, 0 ) float -> zero-ref V18.Real(offs=0x00) P-INDEP "field V18.Real (fldOffset=0x0)" ;* V30 tmp16 [V30 ] ( 0, 0 ) float -> zero-ref V18.Imaginary(offs=0x04) P-INDEP "field V18.Imaginary (fldOffset=0x4)" ;* V31 tmp17 [V31 ] ( 0, 0 ) float -> zero-ref V19.Real(offs=0x00) P-INDEP "field V19.Real (fldOffset=0x0)" ;* V32 tmp18 [V32 ] ( 0, 0 ) float -> zero-ref V19.Imaginary(offs=0x04) P-INDEP "field V19.Imaginary (fldOffset=0x4)" ; V33 tmp19 [V33 ] ( 3, 512 ) float -> [rsp+0x28] do-not-enreg[] V20.Real(offs=0x00) P-DEP "field V20.Real (fldOffset=0x0)" ; V34 tmp20 [V34 ] ( 3, 512 ) float -> [rsp+0x2C] do-not-enreg[] V20.Imaginary(offs=0x04) P-DEP "field V20.Imaginary (fldOffset=0x4)" ; V35 rat0 [V35,T01] ( 3, 96 ) ref -> rax "delegate invoke call" ; ; Lcl frame size = 160 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..006) -> BB08 (always), preds={} succs={BB08} flags=0x00000000.40030020: i label target LIR BB01 IN (6)={V00 V02 V05 V01 V04 V03} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04 } + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(rsi) V02(mm6) V05(mm7) V01(mm8) V04(mm9) V03(mm3) Change life 0000000000000000 {} -> 000000000001F008 {V00 V01 V02 V03 V04 V05} V00 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} V02 in reg mm6 is becoming live [------] Live regs: 00000040 {rsi} => 00000040 {rsi xmm6} V05 in reg mm7 is becoming live [------] Live regs: 00000040 {rsi xmm6} => 00000040 {rsi xmm6 xmm7} V01 in reg mm8 is becoming live [------] Live regs: 00000040 {rsi xmm6 xmm7} => 00000040 {rsi xmm6 xmm7 xmm8} V04 in reg mm9 is becoming live [------] Live regs: 00000040 {rsi xmm6 xmm7 xmm8} => 00000040 {rsi xmm6 xmm7 xmm8 xmm9} V03 in reg mm3 is becoming live [------] Live regs: 00000040 {rsi xmm6 xmm7 xmm8 xmm9} => 00000040 {rsi xmm3 xmm6 xmm7 xmm8 xmm9} Live regs: (unchanged) 00000040 {rsi xmm3 xmm6 xmm7 xmm8 xmm9} GC regs: (unchanged) 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB01: Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB01, IL range [000..006) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 3 (V03 arg3) [000..08E) Added IP mapping: 0x0000 STACK_EMPTY (G_M39786_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [000294] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N005 ( 1, 1) [000000] ------------ t0 = CNS_INT int 0 REG rdi $40 IN0001: xor edi, edi /--* t0 int Generating: N007 ( 1, 3) [000002] DA---------- * STORE_LCL_VAR int V06 loc0 d:2 rdi REG rdi V06 in reg rdi is becoming live [000002] Live regs: 00000040 {rsi xmm3 xmm6 xmm7 xmm8 xmm9} => 000000C0 {rsi rdi xmm3 xmm6 xmm7 xmm8 xmm9} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V06} Added IP mapping: 0x0002 STACK_EMPTY (G_M39786_IG02,ins#1,ofs#2) Generating: N009 (???,???) [000295] ------------ IL_OFFSET void IL offset: 0x2 REG NA Generating: N011 ( 1, 2) [000003] ------------ t3 = LCL_VAR float V03 arg3 u:1 mm3 (last use) REG mm3 $c2 /--* t3 float Generating: N013 ( 1, 3) [000005] DA---------- * STORE_LCL_VAR float V07 loc1 d:2 mm10 REG mm10 V03 in reg mm3 is becoming dead [000003] Live regs: 000000C0 {rsi rdi xmm3 xmm6 xmm7 xmm8 xmm9} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9} Live vars: {V00 V01 V02 V03 V04 V05 V06} => {V00 V01 V02 V04 V05 V06} IN0002: vmovaps xmm10, xmm3 V07 in reg mm10 is becoming live [000005] Live regs: 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} Live vars: {V00 V01 V02 V04 V05 V06} => {V00 V01 V02 V04 V05 V06 V07} Scope info: end block BB01, IL range [000..006) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) IN0003: jmp L_M39786_BB08 =============== Generating BB02 [006..00C) -> BB07 (cond), preds={BB09} succs={BB03,BB07} flags=0x00000000.420ba020: i Loop Loop1 label target gcsafe bwd LIR BB02 IN (7)={ V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(9)={V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V00(rsi) V06(rdi) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Liveness not changing: 000000000000F818 {V00 V01 V02 V04 V05 V06 V07} Live regs: 00000000 {} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB02: G_M39786_IG02: ; offs=000000H, funclet=00, bbWeight=1 Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB02, IL range [006..00C) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) Added IP mapping: 0x0006 STACK_EMPTY (G_M39786_IG03,ins#0,ofs#0) label Generating: N043 (???,???) [000296] ------------ IL_OFFSET void IL offset: 0x6 REG NA Generating: N045 ( 1, 1) [000017] ------------ t17 = CNS_INT int 0 REG rbx $40 IN0004: xor ebx, ebx /--* t17 int Generating: N047 ( 1, 3) [000019] DA---------- * STORE_LCL_VAR int V08 loc2 d:2 rbx REG rbx V08 in reg rbx is becoming live [000019] Live regs: 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} Live vars: {V00 V01 V02 V04 V05 V06 V07} => {V00 V01 V02 V04 V05 V06 V07 V08} Added IP mapping: 0x0008 STACK_EMPTY (G_M39786_IG03,ins#1,ofs#2) Generating: N049 (???,???) [000297] ------------ IL_OFFSET void IL offset: 0x8 REG NA Generating: N051 ( 1, 2) [000020] ------------ t20 = LCL_VAR float V01 arg1 u:1 mm8 REG mm8 $c0 /--* t20 float Generating: N053 ( 1, 3) [000022] DA---------- * STORE_LCL_VAR float V09 loc3 d:2 mm11 REG mm11 IN0005: vmovaps xmm11, xmm8 V09 in reg mm11 is becoming live [000022] Live regs: 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} Added IP mapping: 0x0070 STACK_EMPTY (G_M39786_IG03,ins#2,ofs#7) Generating: N055 (???,???) [000298] ------------ IL_OFFSET void IL offset: 0x70 REG NA Generating: N057 ( 1, 2) [000266] ------------ t266 = LCL_VAR float V01 arg1 u:1 mm8 REG mm8 $c0 Generating: N059 ( 1, 2) [000267] ------------ t267 = LCL_VAR float V02 arg2 u:1 mm6 REG mm6 $c1 /--* t266 float +--* t267 float Generating: N061 ( 3, 5) [000265] N------N---- * GE void REG NA $2c2 IN0006: vucomiss xmm6, xmm8 Generating: N063 ( 5, 7) [000268] ------------ * JTRUE void REG NA IN0007: jbe L_M39786_BB07 Scope info: end block BB02, IL range [006..00C) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) =============== Generating BB03 [00C..023), preds={BB02,BB06} succs={BB04} flags=0x00000000.420ba020: i Loop Loop1 label target gcsafe bwd LIR BB03 IN (9)={ V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V08(rbx) V00(rsi) V06(rdi) V09(mm11) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Liveness not changing: 000000000000FC1C {V00 V01 V02 V04 V05 V06 V07 V08 V09} Live regs: 00000000 {} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB03: G_M39786_IG03: ; offs=00000CH, funclet=00, bbWeight=2 Label: IG04, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB03, IL range [00C..023) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) Added IP mapping: 0x000C STACK_EMPTY (G_M39786_IG04,ins#0,ofs#0) label Generating: N067 (???,???) [000299] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N069 ( 1, 2) [000029] ------------ t29 = LCL_VAR float V09 loc3 u:3 mm11 REG mm11 $201 /--* t29 float Generating: N071 ( 1, 3) [000111] DA---------- * STORE_LCL_VAR float V23 tmp9 d:2 mm0 REG mm0 IN0008: vmovaps xmm0, xmm11 V23 in reg mm0 is becoming live [000111] Live regs: 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C8 {rbx rsi rdi xmm0 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23} genIPmappingAdd: ignoring duplicate IL offset 0xc Generating: N073 (???,???) [000300] ------------ IL_OFFSET void IL offset: 0xc REG NA Generating: N075 ( 1, 2) [000030] ------------ t30 = LCL_VAR float V07 loc1 u:3 mm10 REG mm10 $200 /--* t30 float Generating: N077 ( 1, 3) [000115] DA---------- * STORE_LCL_VAR float V24 tmp10 d:2 mm1 REG mm1 IN0009: vmovaps xmm1, xmm10 V24 in reg mm1 is becoming live [000115] Live regs: 000000C8 {rbx rsi rdi xmm0 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C8 {rbx rsi rdi xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} Added IP mapping: 0x0015 STACK_EMPTY (G_M39786_IG04,ins#2,ofs#10) Generating: N079 (???,???) [000301] ------------ IL_OFFSET void IL offset: 0x15 REG NA Generating: N081 ( 1, 2) [000224] ------------ t224 = LCL_VAR float V23 tmp9 u:2 mm0 REG mm0 $201 /--* t224 float Generating: N083 ( 1, 3) [000225] DA---------- * STORE_LCL_VAR float V25 tmp11 NA REG NA IN000a: vmovss dword ptr [V25 rsp+38H], xmm0 Generating: N085 ( 1, 2) [000227] ------------ t227 = LCL_VAR float V24 tmp10 u:2 mm1 REG mm1 $200 /--* t227 float Generating: N087 ( 1, 3) [000228] DA---------- * STORE_LCL_VAR float V26 tmp12 NA REG NA IN000b: vmovss dword ptr [V26 rsp+3CH], xmm1 Added IP mapping: 0x0019 STACK_EMPTY (G_M39786_IG04,ins#4,ofs#24) Generating: N089 (???,???) [000302] ------------ IL_OFFSET void IL offset: 0x19 REG NA Generating: N091 ( 1, 1) [000036] ------------ t36 = CNS_INT int 0 REG r9 $40 IN000c: xor r9d, r9d /--* t36 int Generating: N093 ( 1, 3) [000038] DA---------- * STORE_LCL_VAR int V12 loc6 d:2 r9 REG r9 V12 in reg r9 is becoming live [000038] Live regs: 000000C8 {rbx rsi rdi xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Scope info: end block BB03, IL range [00C..023) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) =============== Generating BB04 [023..04F) -> BB06 (cond), preds={BB03,BB05} succs={BB05,BB06} flags=0x00000000.42036020: i Loop Loop0 label target bwd LIR BB04 IN (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V12(r9) V08(rbx) V00(rsi) V06(rdi) V23(mm0) V24(mm1) V09(mm11) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Liveness not changing: 000000000000FF1D {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Live regs: 00000000 {} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB04: G_M39786_IG04: ; offs=00001EH, funclet=00, bbWeight=16 Label: IG05, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB04, IL range [023..04F) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) 12 (V12 loc6) [000..08E) Added IP mapping: 0x0023 STACK_EMPTY (G_M39786_IG05,ins#0,ofs#0) label Generating: N097 (???,???) [000303] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N099 ( 1, 1) [000231] ------------ t231 = CNS_DBL float 0.00000000000000000 REG mm2 $100 IN000d: vxorps xmm2, xmm2 /--* t231 float Generating: N101 ( 1, 3) [000232] DA---------- * STORE_LCL_VAR float V27 tmp13 NA REG NA IN000e: vmovss dword ptr [V27 rsp+30H], xmm2 Generating: N103 ( 1, 1) [000234] ------------ t234 = CNS_DBL float 0.00000000000000000 REG mm2 $100 TreeNode is marked ReuseReg /--* t234 float Generating: N105 ( 1, 3) [000235] DA---------- * STORE_LCL_VAR float V28 tmp14 NA REG NA IN000f: vmovss dword ptr [V28 rsp+34H], xmm2 genIPmappingAdd: ignoring duplicate IL offset 0x23 Generating: N107 (???,???) [000304] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N109 ( 1, 2) [000119] ------------ t119 = LCL_VAR float V25 tmp11 mm2 REG mm2 $480 IN0010: vmovss xmm2, dword ptr [V25 rsp+38H] Generating: N111 ( 1, 2) [000122] -c---------- t122 = LCL_VAR float V25 tmp11 NA REG NA $481 /--* t119 float +--* t122 float Generating: N113 ( 7, 8) [000123] ------------ t123 = * MUL float REG mm2 $1c1 IN0011: vmulss xmm2, dword ptr [V25 rsp+38H] Generating: N115 ( 1, 2) [000126] ------------ t126 = LCL_VAR float V26 tmp12 mm3 REG mm3 $482 IN0012: vmovss xmm3, dword ptr [V26 rsp+3CH] Generating: N117 ( 1, 2) [000129] -c---------- t129 = LCL_VAR float V26 tmp12 NA REG NA $483 /--* t126 float +--* t129 float Generating: N119 ( 7, 8) [000130] ------------ t130 = * MUL float REG mm3 $1c2 IN0013: vmulss xmm3, dword ptr [V26 rsp+3CH] /--* t123 float +--* t130 float Generating: N121 ( 19, 20) [000131] ------------ t131 = * SUB float REG mm2 $1c3 IN0014: vsubss xmm2, xmm3 /--* t131 float Generating: N123 ( 19, 20) [000160] DA---------- * STORE_LCL_VAR float V16 tmp2 d:2 mm2 REG mm2 V16 in reg mm2 is becoming live [000160] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm2 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V23 V24} genIPmappingAdd: ignoring duplicate IL offset 0x23 Generating: N125 (???,???) [000305] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N127 ( 1, 2) [000135] ------------ t135 = LCL_VAR float V25 tmp11 mm3 REG mm3 $485 IN0015: vmovss xmm3, dword ptr [V25 rsp+38H] Generating: N129 ( 3, 4) [000132] -c---------- t132 = CNS_DBL float 2.0000000000000000 REG NA $101 /--* t135 float +--* t132 float Generating: N131 ( 9, 10) [000136] ------------ t136 = * MUL float REG mm3 $1c4 IN0016: vmulss xmm3, dword ptr [reloc @RWD00] Generating: N133 ( 1, 2) [000139] -c---------- t139 = LCL_VAR float V26 tmp12 NA REG NA $486 /--* t136 float +--* t139 float Generating: N135 ( 15, 16) [000140] ------------ t140 = * MUL float REG mm3 $1c5 IN0017: vmulss xmm3, dword ptr [V26 rsp+3CH] /--* t140 float Generating: N137 ( 15, 16) [000162] DA---------- * STORE_LCL_VAR float V17 tmp3 d:2 mm3 REG mm3 V17 in reg mm3 is becoming live [000162] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm2 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm2 xmm3 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V17 V23 V24} genIPmappingAdd: ignoring duplicate IL offset 0x23 Generating: N139 (???,???) [000306] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N141 ( 1, 2) [000151] ------------ t151 = LCL_VAR float V16 tmp2 u:2 mm2 (last use) REG mm2 $1c3 /--* t151 float Generating: N143 ( 1, 3) [000153] DA---------- * STORE_LCL_VAR float V27 tmp13 NA REG NA V16 in reg mm2 is becoming dead [000151] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm2 xmm3 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm3 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V16 V17 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V17 V23 V24} IN0018: vmovss dword ptr [V27 rsp+30H], xmm2 genIPmappingAdd: ignoring duplicate IL offset 0x23 Generating: N145 (???,???) [000307] ------------ IL_OFFSET void IL offset: 0x23 REG NA Generating: N147 ( 1, 2) [000156] ------------ t156 = LCL_VAR float V17 tmp3 u:2 mm3 (last use) REG mm3 $1c5 /--* t156 float Generating: N149 ( 1, 3) [000158] DA---------- * STORE_LCL_VAR float V28 tmp14 NA REG NA V17 in reg mm3 is becoming dead [000156] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm3 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V17 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} IN0019: vmovss dword ptr [V28 rsp+34H], xmm3 Generating: N151 ( 3, 4) [000147] ------------ t147 = LCL_FLD long V15 tmp1 [+0] rcx * float V15.Real (offs=0x00) -> V27 tmp13 * float V15.Imaginary (offs=0x04) -> V28 tmp14 REG rcx $4c0 IN001a: mov rcx, qword ptr [V15 rsp+30H] /--* t147 long Generating: N153 ( 7, 9) [000049] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] NA * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 REG NA IN001b: mov qword ptr [V11 rsp+38H], rcx Added IP mapping: 0x002C STACK_EMPTY (G_M39786_IG05,ins#15,ofs#99) Generating: N155 (???,???) [000308] ------------ IL_OFFSET void IL offset: 0x2c REG NA genIPmappingAdd: ignoring duplicate IL offset 0x2c Generating: N157 (???,???) [000309] ------------ IL_OFFSET void IL offset: 0x2c REG NA genIPmappingAdd: ignoring duplicate IL offset 0x2c Generating: N159 (???,???) [000310] ------------ IL_OFFSET void IL offset: 0x2c REG NA Generating: N161 ( 1, 1) [000252] ------------ t252 = CNS_DBL float 0.00000000000000000 REG mm2 $100 IN001c: vxorps xmm2, xmm2 /--* t252 float Generating: N163 ( 1, 3) [000253] DA---------- * STORE_LCL_VAR float V33 tmp19 NA REG NA IN001d: vmovss dword ptr [V33 rsp+28H], xmm2 Generating: N165 ( 1, 1) [000255] ------------ t255 = CNS_DBL float 0.00000000000000000 REG mm2 $100 TreeNode is marked ReuseReg /--* t255 float Generating: N167 ( 1, 3) [000256] DA---------- * STORE_LCL_VAR float V34 tmp20 NA REG NA IN001e: vmovss dword ptr [V34 rsp+2CH], xmm2 genIPmappingAdd: ignoring duplicate IL offset 0x2c Generating: N169 (???,???) [000311] ------------ IL_OFFSET void IL offset: 0x2c REG NA Generating: N171 ( 1, 2) [000166] -c---------- t166 = LCL_VAR float V25 tmp11 NA REG NA $488 Generating: N173 ( 1, 2) [000169] ------------ t169 = LCL_VAR float V23 tmp9 u:2 mm0 REG mm0 $201 /--* t166 float +--* t169 float Generating: N175 ( 7, 8) [000170] ------------ t170 = * ADD float REG mm2 $1c6 IN001f: vmovaps xmm2, xmm0 IN0020: vaddss xmm2, dword ptr [V25 rsp+38H] /--* t170 float Generating: N177 ( 7, 8) [000196] DA---------- * STORE_LCL_VAR float V33 tmp19 NA REG NA IN0021: vmovss dword ptr [V33 rsp+28H], xmm2 genIPmappingAdd: ignoring duplicate IL offset 0x2c Generating: N179 (???,???) [000312] ------------ IL_OFFSET void IL offset: 0x2c REG NA Generating: N181 ( 1, 2) [000173] -c---------- t173 = LCL_VAR float V26 tmp12 NA REG NA $489 Generating: N183 ( 1, 2) [000176] ------------ t176 = LCL_VAR float V24 tmp10 u:2 mm1 REG mm1 $200 /--* t173 float +--* t176 float Generating: N185 ( 7, 8) [000177] ------------ t177 = * ADD float REG mm2 $1c7 IN0022: vmovaps xmm2, xmm1 IN0023: vaddss xmm2, dword ptr [V26 rsp+3CH] /--* t177 float Generating: N187 ( 7, 8) [000201] DA---------- * STORE_LCL_VAR float V34 tmp20 NA REG NA IN0024: vmovss dword ptr [V34 rsp+2CH], xmm2 Generating: N189 ( 3, 4) [000184] ------------ t184 = LCL_FLD long V20 tmp6 [+0] rcx * float V20.Real (offs=0x00) -> V33 tmp19 * float V20.Imaginary (offs=0x04) -> V34 tmp20 REG rcx $4c1 IN0025: mov rcx, qword ptr [V20 rsp+28H] /--* t184 long Generating: N191 ( 7, 9) [000061] DA---------- * STORE_LCL_FLD long V11 loc5 [+0] NA * float V11.Real (offs=0x00) -> V25 tmp11 * float V11.Imaginary (offs=0x04) -> V26 tmp12 REG NA IN0026: mov qword ptr [V11 rsp+38H], rcx Added IP mapping: 0x0037 STACK_EMPTY (G_M39786_IG05,ins#26,ofs#166) Generating: N193 (???,???) [000313] ------------ IL_OFFSET void IL offset: 0x37 REG NA Generating: N195 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V12 loc6 u:3 r9 (last use) REG r9 $242 Generating: N197 ( 1, 1) [000063] -c---------- t63 = CNS_INT int 1 REG NA $41 /--* t62 int +--* t63 int Generating: N199 ( 3, 3) [000064] ------------ t64 = * ADD int REG r9 $2c3 V12 in reg r9 is becoming dead [000062] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C8 {rbx rsi rdi xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} IN0027: inc r9d /--* t64 int Generating: N201 ( 3, 3) [000066] DA---------- * STORE_LCL_VAR int V12 loc6 d:4 r9 REG r9 V12 in reg r9 is becoming live [000066] Live regs: 000000C8 {rbx rsi rdi xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Generating: N203 ( 1, 2) [000205] ------------ t205 = LCL_VAR float V25 tmp11 mm2 REG mm2 $48a IN0028: vmovss xmm2, dword ptr [V25 rsp+38H] Generating: N205 ( 1, 2) [000208] -c---------- t208 = LCL_VAR float V25 tmp11 NA REG NA $48b /--* t205 float +--* t208 float Generating: N207 ( 7, 8) [000209] ------------ t209 = * MUL float REG mm2 $1c8 IN0029: vmulss xmm2, dword ptr [V25 rsp+38H] Generating: N209 ( 1, 2) [000212] ------------ t212 = LCL_VAR float V26 tmp12 mm3 REG mm3 $48c IN002a: vmovss xmm3, dword ptr [V26 rsp+3CH] Generating: N211 ( 1, 2) [000215] -c---------- t215 = LCL_VAR float V26 tmp12 NA REG NA $48d /--* t212 float +--* t215 float Generating: N213 ( 7, 8) [000216] ------------ t216 = * MUL float REG mm3 $1c9 IN002b: vmulss xmm3, dword ptr [V26 rsp+3CH] /--* t209 float +--* t216 float Generating: N215 ( 19, 20) [000217] ------------ t217 = * ADD float REG mm2 $1ca IN002c: vaddss xmm2, xmm3 /--* t217 float Generating: N217 ( 19, 20) [000072] DA---------- * STORE_LCL_VAR float V13 loc7 d:2 mm2 REG mm2 V13 in reg mm2 is becoming live [000072] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm2 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V13 V23 V24} Added IP mapping: 0x0046 STACK_EMPTY (G_M39786_IG05,ins#32,ofs#202) Generating: N219 (???,???) [000314] ------------ IL_OFFSET void IL offset: 0x46 REG NA Generating: N221 ( 1, 2) [000073] ------------ t73 = LCL_VAR float V13 loc7 u:2 mm2 (last use) REG mm2 $1ca Generating: N223 ( 3, 4) [000074] ------------ t74 = CNS_DBL float 4.0000000000000000 REG mm3 $102 IN002d: vmovss xmm3, dword ptr [reloc @RWD04] /--* t73 float +--* t74 float Generating: N225 ( 5, 7) [000075] N------N-U-- * GE void REG NA $2c4 V13 in reg mm2 is becoming dead [000073] Live regs: 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm2 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V13 V23 V24} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} IN002e: vucomiss xmm3, xmm2 Generating: N227 ( 7, 9) [000076] ------------ * JTRUE void REG NA IN002f: jbe L_M39786_BB06 Scope info: end block BB04, IL range [023..04F) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) =============== Generating BB05 [04F..058) -> BB04 (cond), preds={BB04} succs={BB06,BB04} flags=0x00000000.42000020: i bwd LIR BB05 IN (12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(12)={V12 V08 V00 V06 V23 V24 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V12(r9) V08(rbx) V00(rsi) V06(rdi) V23(mm0) V24(mm1) V09(mm11) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Liveness not changing: 000000000000FF1D {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} Live regs: 00000000 {} => 000002C8 {rbx rsi rdi r9 xmm0 xmm1 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB05: G_M39786_IG05: ; offs=000039H, funclet=00, bbWeight=128 Label: IG06, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB05, IL range [04F..058) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) 12 (V12 loc6) [000..08E) Added IP mapping: 0x004F STACK_EMPTY (G_M39786_IG06,ins#0,ofs#0) label Generating: N231 (???,???) [000315] ------------ IL_OFFSET void IL offset: 0x4f REG NA Generating: N233 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V12 loc6 u:4 r9 REG r9 $2c3 Generating: N235 ( 1, 4) [000095] -c---------- t95 = CNS_INT int 0x3E8 REG NA $47 /--* t94 int +--* t95 int Generating: N237 ( 3, 6) [000096] J------N---- * LT void REG NA $2c5 IN0030: cmp r9d, 0x3E8 Generating: N239 ( 5, 8) [000097] ------------ * JTRUE void REG NA IN0031: jl L_M39786_BB04 Scope info: end block BB05, IL range [04F..058) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) 12 (V12 loc6) [000..08E) =============== Generating BB06 [058..074) -> BB03 (cond), preds={BB04,BB05} succs={BB07,BB03} flags=0x00000004.420b0020: i label target gcsafe bwd LIR BB06 IN (10)={V12 V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(9)={ V08 V00 V06 V09 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V12(r9) V08(rbx) V00(rsi) V06(rdi) V09(mm11) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Change life 000000000000FF1D {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V23 V24} -> 000000000000FC1D {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12} V23 in reg mm0 is becoming dead [------] Live regs: (unchanged) 00000000 {} V24 in reg mm1 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000002C8 {rbx rsi rdi r9 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB06: G_M39786_IG06: ; offs=000117H, funclet=00, bbWeight=64 Label: IG07, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB06, IL range [058..074) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) 8 (V08 loc2) [000..08E) 9 (V09 loc3) [000..08E) 12 (V12 loc6) [000..08E) Generating: N243 ( 1, 1) [000077] ------------ t77 = LCL_VAR ref V00 this u:1 rsi REG rsi $80 /--* t77 ref Generating: N245 ( 2, 2) [000259] -c---------- t259 = * LEA(b+16) byref REG NA /--* t259 byref Generating: N247 ( 4, 4) [000219] ---XG------- t219 = * IND ref REG rax IN0032: mov rax, gword ptr [rsi+16] GC regs: 00000040 {rsi} => 00000041 {rax rsi} /--* t219 ref Generating: N249 (???,???) [000328] DA-XG------- * STORE_LCL_VAR ref V35 rat0 rax REG rax GC regs: 00000041 {rax rsi} => 00000040 {rsi} V35 in reg rax is becoming live [000328] Live regs: 000002C8 {rbx rsi rdi r9 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000002C9 {rax rbx rsi rdi r9 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V35} GC regs: 00000040 {rsi} => 00000041 {rax rsi} Generating: N251 (???,???) [000329] ------------ t329 = LCL_VAR ref V35 rat0 rax REG rax /--* t329 ref Generating: N253 (???,???) [000330] -c---------- t330 = * LEA(b+8) byref REG NA /--* t330 byref Generating: N255 (???,???) [000331] ------------ t331 = * IND ref REG rcx IN0033: mov rcx, gword ptr [rax+8] GC regs: 00000041 {rax rsi} => 00000043 {rax rcx rsi} /--* t331 ref Generating: N257 (???,???) [000323] ---XG------- t323 = * PUTARG_REG ref REG rcx GC regs: 00000043 {rax rcx rsi} => 00000041 {rax rsi} GC regs: 00000041 {rax rsi} => 00000043 {rax rcx rsi} Generating: N259 ( 1, 1) [000080] ------------ t80 = LCL_VAR int V08 loc2 u:3 rbx REG rbx $241 /--* t80 int Generating: N261 (???,???) [000324] ------------ t324 = * PUTARG_REG int REG rdx IN0034: mov edx, ebx Generating: N263 ( 1, 1) [000081] ------------ t81 = LCL_VAR int V06 loc0 u:3 rdi REG rdi $240 /--* t81 int Generating: N265 (???,???) [000325] ------------ t325 = * PUTARG_REG int REG r8 IN0035: mov r8d, edi Generating: N267 ( 1, 1) [000082] ------------ t82 = LCL_VAR int V12 loc6 u:4 r9 (last use) REG r9 $2c3 /--* t82 int Generating: N269 (???,???) [000326] ------------ t326 = * PUTARG_REG int REG r9 V12 in reg r9 is becoming dead [000082] Live regs: 000002C9 {rax rbx rsi rdi r9 xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C9 {rax rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V12 V35} => {V00 V01 V02 V04 V05 V06 V07 V08 V09 V35} Generating: N271 ( 3, 2) [000332] ------------ t332 = LCL_VAR ref V35 rat0 rax (last use) REG rax /--* t332 ref Generating: N273 ( 4, 3) [000333] -c---------- t333 = * LEA(b+24) ref REG NA /--* t333 ref Generating: N275 ( 7, 5) [000334] -c---------- t334 = * IND long REG NA /--* t323 ref this in rcx +--* t324 int arg1 in rdx +--* t325 int arg2 in r8 +--* t326 int arg3 in r9 +--* t334 long control expr Generating: N277 ( 21, 17) [000083] --CXG------- * CALL void System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32].Invoke REG NA $VN.Void GC regs: 00000043 {rax rcx rsi} => 00000041 {rax rsi} V35 in reg rax is becoming dead [000332] Live regs: 000000C9 {rax rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09 V35} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} GC regs: 00000041 {rax rsi} => 00000040 {rsi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0036: call qword ptr [rax+24]System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32]:Invoke(int,int,int):this Added IP mapping: 0x0067 STACK_EMPTY (G_M39786_IG07,ins#5,ofs#16) label Generating: N279 (???,???) [000316] ------------ IL_OFFSET void IL offset: 0x67 REG NA Generating: N281 ( 1, 2) [000084] ------------ t84 = LCL_VAR float V09 loc3 u:3 mm11 (last use) REG mm11 $201 Generating: N283 ( 1, 2) [000085] ------------ t85 = LCL_VAR float V05 arg5 u:1 mm7 REG mm7 $c4 /--* t84 float +--* t85 float Generating: N285 ( 7, 8) [000086] ------------ t86 = * ADD float REG mm11 $1cb V09 in reg mm11 is becoming dead [000084] Live regs: 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V04 V05 V06 V07 V08} IN0037: vaddss xmm11, xmm7 /--* t86 float Generating: N287 ( 7, 8) [000088] DA---------- * STORE_LCL_VAR float V09 loc3 d:4 mm11 REG mm11 V09 in reg mm11 is becoming live [000088] Live regs: 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} Added IP mapping: 0x006C STACK_EMPTY (G_M39786_IG07,ins#6,ofs#21) Generating: N289 (???,???) [000317] ------------ IL_OFFSET void IL offset: 0x6c REG NA Generating: N291 ( 1, 1) [000089] ------------ t89 = LCL_VAR int V08 loc2 u:3 rbx (last use) REG rbx $241 Generating: N293 ( 1, 1) [000090] -c---------- t90 = CNS_INT int 1 REG NA $41 /--* t89 int +--* t90 int Generating: N295 ( 3, 3) [000091] ------------ t91 = * ADD int REG rbx $2c6 V08 in reg rbx is becoming dead [000089] Live regs: 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V04 V05 V06 V07 V09} IN0038: inc ebx /--* t91 int Generating: N297 ( 3, 3) [000093] DA---------- * STORE_LCL_VAR int V08 loc2 d:4 rbx REG rbx V08 in reg rbx is becoming live [000093] Live regs: 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} => 000000C8 {rbx rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10 xmm11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V09} => {V00 V01 V02 V04 V05 V06 V07 V08 V09} Added IP mapping: 0x0070 STACK_EMPTY (G_M39786_IG07,ins#7,ofs#23) Generating: N299 (???,???) [000318] ------------ IL_OFFSET void IL offset: 0x70 REG NA Generating: N301 ( 1, 2) [000023] ------------ t23 = LCL_VAR float V09 loc3 u:4 mm11 REG mm11 $1cb Generating: N303 ( 1, 2) [000024] ------------ t24 = LCL_VAR float V02 arg2 u:1 mm6 REG mm6 $c1 /--* t23 float +--* t24 float Generating: N305 ( 3, 5) [000025] J------N---- * LT void REG NA $2c7 IN0039: vucomiss xmm6, xmm11 Generating: N307 ( 5, 7) [000026] ------------ * JTRUE void REG NA IN003a: ja L_M39786_BB03 Scope info: end block BB06, IL range [058..074) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) =============== Generating BB07 [074..07D), preds={BB02,BB06} succs={BB08} flags=0x00000000.420b0020: i label target gcsafe bwd LIR BB07 IN (7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V00(rsi) V06(rdi) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Change life 000000000000FC1C {V00 V01 V02 V04 V05 V06 V07 V08 V09} -> 000000000000F818 {V00 V01 V02 V04 V05 V06 V07} V08 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V09 in reg mm11 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB07: G_M39786_IG07: ; offs=000124H, funclet=00, bbWeight=16 Label: IG08, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB07, IL range [074..07D) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) Added IP mapping: 0x0074 STACK_EMPTY (G_M39786_IG08,ins#0,ofs#0) label Generating: N311 (???,???) [000319] ------------ IL_OFFSET void IL offset: 0x74 REG NA Generating: N313 ( 1, 2) [000098] ------------ t98 = LCL_VAR float V07 loc1 u:3 mm10 (last use) REG mm10 $200 Generating: N315 ( 1, 2) [000099] ------------ t99 = LCL_VAR float V05 arg5 u:1 mm7 REG mm7 $c4 /--* t98 float +--* t99 float Generating: N317 ( 7, 8) [000100] ------------ t100 = * ADD float REG mm10 $1cc V07 in reg mm10 is becoming dead [000098] Live regs: 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9} Live vars: {V00 V01 V02 V04 V05 V06 V07} => {V00 V01 V02 V04 V05 V06} IN003b: vaddss xmm10, xmm7 /--* t100 float Generating: N319 ( 7, 8) [000102] DA---------- * STORE_LCL_VAR float V07 loc1 d:4 mm10 REG mm10 V07 in reg mm10 is becoming live [000102] Live regs: 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} Live vars: {V00 V01 V02 V04 V05 V06} => {V00 V01 V02 V04 V05 V06 V07} Added IP mapping: 0x0079 STACK_EMPTY (G_M39786_IG08,ins#1,ofs#5) Generating: N321 (???,???) [000320] ------------ IL_OFFSET void IL offset: 0x79 REG NA Generating: N323 ( 1, 1) [000103] ------------ t103 = LCL_VAR int V06 loc0 u:3 rdi (last use) REG rdi $240 Generating: N325 ( 1, 1) [000104] -c---------- t104 = CNS_INT int 1 REG NA $41 /--* t103 int +--* t104 int Generating: N327 ( 3, 3) [000105] ------------ t105 = * ADD int REG rdi $2c8 V06 in reg rdi is becoming dead [000103] Live regs: 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} => 00000040 {rsi xmm6 xmm7 xmm8 xmm9 xmm10} Live vars: {V00 V01 V02 V04 V05 V06 V07} => {V00 V01 V02 V04 V05 V07} IN003c: inc edi /--* t105 int Generating: N329 ( 3, 3) [000107] DA---------- * STORE_LCL_VAR int V06 loc0 d:4 rdi REG rdi V06 in reg rdi is becoming live [000107] Live regs: 00000040 {rsi xmm6 xmm7 xmm8 xmm9 xmm10} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} Live vars: {V00 V01 V02 V04 V05 V07} => {V00 V01 V02 V04 V05 V06 V07} Scope info: end block BB07, IL range [074..07D) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) =============== Generating BB08 [07D..082) -> BB10 (cond), preds={BB01,BB07} succs={BB09,BB10} flags=0x00000000.42030020: i label target bwd LIR BB08 IN (7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V00(rsi) V06(rdi) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Liveness not changing: 000000000000F818 {V00 V01 V02 V04 V05 V06 V07} Live regs: 00000000 {} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB08: G_M39786_IG08: ; offs=000146H, funclet=00, bbWeight=2 Label: IG09, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB08, IL range [07D..082) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) Added IP mapping: 0x007D STACK_EMPTY (G_M39786_IG09,ins#0,ofs#0) label Generating: N017 (???,???) [000321] ------------ IL_OFFSET void IL offset: 0x7d REG NA Generating: N019 ( 1, 2) [000006] ------------ t6 = LCL_VAR float V07 loc1 u:3 mm10 REG mm10 $200 Generating: N021 ( 1, 2) [000007] ------------ t7 = LCL_VAR float V04 arg4 u:1 mm9 REG mm9 $c3 /--* t6 float +--* t7 float Generating: N023 ( 3, 5) [000008] N------N-U-- * GE void REG NA $2c0 IN003d: vucomiss xmm9, xmm10 Generating: N025 ( 5, 7) [000009] ------------ * JTRUE void REG NA IN003e: jbe L_M39786_BB10 Scope info: end block BB08, IL range [07D..082) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) =============== Generating BB09 [082..08D) -> BB02 (cond), preds={BB08} succs={BB10,BB02} flags=0x00000004.42080020: i gcsafe bwd LIR BB09 IN (7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap OUT(7)={V00 V06 V07 V02 V05 V01 V04} + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V00(rsi) V06(rdi) V07(mm10) V02(mm6) V05(mm7) V01(mm8) V04(mm9) Liveness not changing: 000000000000F818 {V00 V01 V02 V04 V05 V06 V07} Live regs: 00000000 {} => 000000C0 {rsi rdi xmm6 xmm7 xmm8 xmm9 xmm10} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M39786_BB09: G_M39786_IG09: ; offs=00014DH, funclet=00, bbWeight=8 Label: IG10, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB09, IL range [082..08D) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) Generating: N029 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V00 this u:1 rsi REG rsi $80 /--* t11 ref Generating: N031 (???,???) [000335] ------------ t335 = * PUTARG_REG ref REG rcx IN003f: mov rcx, rsi GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t335 ref this in rcx Generating: N033 ( 15, 8) [000012] --CXG------- t12 = * CALL int Algorithms.FractalRenderer.get_Abort REG rax $300 GC regs: 00000042 {rcx rsi} => 00000040 {rsi} Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0040: call Algorithms.FractalRenderer:get_Abort():bool:this Generating: N035 ( 1, 1) [000014] -c---------- t14 = CNS_INT int 0 REG NA $40 /--* t12 int +--* t14 int Generating: N037 ( 17, 10) [000015] J--XG--N---- * EQ void REG NA $2c1 IN0041: test eax, eax Generating: N039 ( 19, 12) [000016] ---XG------- * JTRUE void REG NA IN0042: je L_M39786_BB02 Scope info: end block BB09, IL range [082..08D) Scope info: open scopes = 0 (V00 this) [000..08E) 2 (V02 arg2) [000..08E) 5 (V05 arg5) [000..08E) 1 (V01 arg1) [000..08E) 4 (V04 arg4) [000..08E) 6 (V06 loc0) [000..08E) 7 (V07 loc1) [000..08E) =============== Generating BB10 [08D..08E) (return), preds={BB08,BB09} succs={} flags=0x00000000.40030020: i label target LIR BB10 IN (0)={} OUT(0)={} Recording Var Locations at start of BB10 Change life 000000000000F818 {V00 V01 V02 V04 V05 V06 V07} -> 0000000000000000 {} V00 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} V06 in reg rdi is becoming dead [------] Live regs: (unchanged) 00000000 {} V07 in reg mm10 is becoming dead [------] Live regs: (unchanged) 00000000 {} V02 in reg mm6 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg mm7 is becoming dead [------] Live regs: (unchanged) 00000000 {} V01 in reg mm8 is becoming dead [------] Live regs: (unchanged) 00000000 {} V04 in reg mm9 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M39786_BB10: G_M39786_IG10: ; offs=000158H, funclet=00, bbWeight=4 Label: IG11, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB10, IL range [08D..08E) Scope info: open scopes = Added IP mapping: 0x008D STACK_EMPTY (G_M39786_IG11,ins#0,ofs#0) label Generating: N333 (???,???) [000322] ------------ IL_OFFSET void IL offset: 0x8d REG NA Generating: N335 ( 0, 0) [000010] ------------ RETURN void REG NA $380 Scope info: end block BB10, IL range [08D..08E) Scope info: ending scope, LVnum=0 [000..08E) Scope info: ending scope, LVnum=1 [000..08E) Scope info: ending scope, LVnum=2 [000..08E) Scope info: ending scope, LVnum=3 [000..08E) Scope info: ending scope, LVnum=4 [000..08E) Scope info: ending scope, LVnum=5 [000..08E) Scope info: ending scope, LVnum=6 [000..08E) Scope info: ending scope, LVnum=7 [000..08E) Scope info: ending scope, LVnum=8 [000..08E) Scope info: ending scope, LVnum=9 [000..08E) Scope info: ending scope, LVnum=10 [000..08E) siEndScope: Failed to end scope for V10 Scope info: ending scope, LVnum=11 [000..08E) siEndScope: Failed to end scope for V11 Scope info: ending scope, LVnum=12 [000..08E) Scope info: ending scope, LVnum=13 [000..08E) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M39786_IG11,ins#0,ofs#0) label Reserving epilog IG for block BB10 *************** After placeholder IG creation G_M39786_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M39786_IG02: ; offs=000000H, size=000CH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG03: ; offs=00000CH, size=0012H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG04: ; offs=00001EH, size=001BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG05: ; offs=000039H, size=00DEH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG06: ; offs=000117H, size=000DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG07: ; offs=000124H, size=0022H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG08: ; offs=000146H, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG09: ; offs=00014DH, size=000BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG10: ; offs=000158H, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG11: ; epilog placeholder, next placeholder=, BB10 [0010], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000040 {rsi}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Liveness not changing: 0000000000000000 {} # compCycleEstimate = 186, compSizeEstimate = 227 Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this ; Final local variable assignments ; ; V00 this [V00,T03] ( 4, 22 ) ref -> rsi this class-hnd ; V01 arg1 [V01,T14] ( 4, 6 ) float -> mm8 ; V02 arg2 [V02,T12] ( 4, 20 ) float -> mm6 ; V03 arg3 [V03,T16] ( 3, 3 ) float -> mm3 ; V04 arg4 [V04,T15] ( 1, 8 ) float -> mm9 ; V05 arg5 [V05,T13] ( 2, 18 ) float -> mm7 ; V06 loc0 [V06,T04] ( 4, 21 ) int -> rdi ; V07 loc1 [V07,T11] ( 5, 29 ) float -> mm10 ; V08 loc2 [V08,T02] ( 4, 50 ) int -> rbx ; V09 loc3 [V09,T10] ( 5, 66 ) float -> mm11 ;* V10 loc4 [V10 ] ( 0, 0 ) struct ( 8) zero-ref ld-addr-op ; V11 loc5 [V11 ] ( 16,1824 ) struct ( 8) [rsp+0x38] do-not-enreg[SF] must-init ld-addr-op ; V12 loc6 [V12,T00] ( 5, 352 ) int -> r9 ; V13 loc7 [V13,T07] ( 2, 256 ) float -> mm2 ; V14 OutArgs [V14 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] "OutgoingArgSpace" ; V15 tmp1 [V15 ] ( 5,1280 ) struct ( 8) [rsp+0x30] do-not-enreg[SF] "NewObj constructor temp" ; V16 tmp2 [V16,T05] ( 2, 512 ) float -> mm2 "Inlining Arg" ; V17 tmp3 [V17,T06] ( 2, 512 ) float -> mm3 "Inlining Arg" ;* V18 tmp4 [V18 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" ;* V19 tmp5 [V19 ] ( 0, 0 ) struct ( 8) zero-ref "Inlining Arg" ; V20 tmp6 [V20 ] ( 5,1280 ) struct ( 8) [rsp+0x28] do-not-enreg[SF] "NewObj constructor temp" ;* V21 tmp7 [V21 ] ( 0, 0 ) float -> zero-ref "Inlining Arg" ;* V22 tmp8 [V22 ] ( 0, 0 ) float -> zero-ref "Inlining Arg" ; V23 tmp9 [V23,T08] ( 3, 160 ) float -> mm0 V10.Real(offs=0x00) P-INDEP "field V10.Real (fldOffset=0x0)" ; V24 tmp10 [V24,T09] ( 3, 160 ) float -> mm1 V10.Imaginary(offs=0x04) P-INDEP "field V10.Imaginary (fldOffset=0x4)" ; V25 tmp11 [V25 ] ( 9,1040 ) float -> [rsp+0x38] do-not-enreg[] V11.Real(offs=0x00) P-DEP "field V11.Real (fldOffset=0x0)" ; V26 tmp12 [V26 ] ( 9,1040 ) float -> [rsp+0x3C] do-not-enreg[] V11.Imaginary(offs=0x04) P-DEP "field V11.Imaginary (fldOffset=0x4)" ; V27 tmp13 [V27 ] ( 3, 512 ) float -> [rsp+0x30] do-not-enreg[] V15.Real(offs=0x00) P-DEP "field V15.Real (fldOffset=0x0)" ; V28 tmp14 [V28 ] ( 3, 512 ) float -> [rsp+0x34] do-not-enreg[] V15.Imaginary(offs=0x04) P-DEP "field V15.Imaginary (fldOffset=0x4)" ;* V29 tmp15 [V29 ] ( 0, 0 ) float -> zero-ref V18.Real(offs=0x00) P-INDEP "field V18.Real (fldOffset=0x0)" ;* V30 tmp16 [V30 ] ( 0, 0 ) float -> zero-ref V18.Imaginary(offs=0x04) P-INDEP "field V18.Imaginary (fldOffset=0x4)" ;* V31 tmp17 [V31 ] ( 0, 0 ) float -> zero-ref V19.Real(offs=0x00) P-INDEP "field V19.Real (fldOffset=0x0)" ;* V32 tmp18 [V32 ] ( 0, 0 ) float -> zero-ref V19.Imaginary(offs=0x04) P-INDEP "field V19.Imaginary (fldOffset=0x4)" ; V33 tmp19 [V33 ] ( 3, 512 ) float -> [rsp+0x28] do-not-enreg[] V20.Real(offs=0x00) P-DEP "field V20.Real (fldOffset=0x0)" ; V34 tmp20 [V34 ] ( 3, 512 ) float -> [rsp+0x2C] do-not-enreg[] V20.Imaginary(offs=0x04) P-DEP "field V20.Imaginary (fldOffset=0x4)" ; V35 rat0 [V35,T01] ( 3, 96 ) ref -> rax "delegate invoke call" ; ; Lcl frame size = 160 *************** Before prolog / epilog generation G_M39786_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M39786_IG02: ; offs=000000H, size=000CH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG03: ; offs=00000CH, size=0012H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG04: ; offs=00001EH, size=001BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG05: ; offs=000039H, size=00DEH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG06: ; offs=000117H, size=000DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG07: ; offs=000124H, size=0022H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG08: ; offs=000146H, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG09: ; offs=00014DH, size=000BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG10: ; offs=000158H, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG11: ; epilog placeholder, next placeholder=, BB10 [0010], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000040 {rsi}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Recording Var Locations at start of BB01 V00(rsi) V02(mm6) V05(mm7) V01(mm8) V04(mm9) V03(mm3) *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M39786_IG01,ins#0,ofs#0) label __prolog: Found 2 lvMustInit int-sized stack slots, frame offsets -56 through -64 IN0043: push rdi IN0044: push rsi IN0045: push rbx IN0046: sub rsp, 160 IN0047: vzeroupper IN0048: vmovaps qword ptr [rsp+90H], xmm6 IN0049: vmovaps qword ptr [rsp+80H], xmm7 IN004a: vmovaps qword ptr [rsp+70H], xmm8 IN004b: vmovaps qword ptr [rsp+60H], xmm9 IN004c: vmovaps qword ptr [rsp+50H], xmm10 IN004d: vmovaps qword ptr [rsp+40H], xmm11 IN004e: xor rax, rax IN004f: mov qword ptr [V11 rsp+38H], rax *************** In genFnPrologCalleeRegArgs() for int regs IN0050: mov rsi, rcx *************** In genFnPrologCalleeRegArgs() for float regs IN0051: vmovaps xmm8, xmm1 IN0052: vmovaps xmm6, xmm2 *************** In genEnregisterIncomingStackArgs() IN0053: vmovss xmm9, dword ptr [V04 rsp+E0H] IN0054: vmovss xmm7, dword ptr [V05 rsp+E8H] G_M39786_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN0055: vmovaps xmm6, qword ptr [rsp+90H] IN0056: vmovaps xmm7, qword ptr [rsp+80H] IN0057: vmovaps xmm8, qword ptr [rsp+70H] IN0058: vmovaps xmm9, qword ptr [rsp+60H] IN0059: vmovaps xmm10, qword ptr [rsp+50H] IN005a: vmovaps xmm11, qword ptr [rsp+40H] IN005b: add rsp, 160 IN005c: pop rbx IN005d: pop rsi IN005e: pop rdi IN005f: ret G_M39786_IG11: ; offs=000168H, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M39786_IG01: ; func=00, offs=000000H, size=0065H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M39786_IG02: ; offs=000065H, size=000CH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG03: ; offs=000071H, size=0012H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG04: ; offs=000083H, size=001BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG05: ; offs=00009EH, size=00DEH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG06: ; offs=00017CH, size=000DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG07: ; offs=000189H, size=0022H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG08: ; offs=0001ABH, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG09: ; offs=0001B2H, size=000BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG10: ; offs=0001BDH, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M39786_IG11: ; offs=0001CDH, size=003BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc *************** In emitJumpDistBind() Binding: IN0003: 000000 jmp L_M39786_BB08 Binding L_M39786_BB08to G_M39786_IG09 Estimate of fwd jump [7EAE42CC/003]: 006C -> 01B2 = 0144 Adjusted offset of BB03 from 0071 to 0071 Binding: IN0007: 000000 jbe L_M39786_BB07 Binding L_M39786_BB07to G_M39786_IG08 Estimate of fwd jump [7EAE4554/007]: 007D -> 01AB = 012C Adjusted offset of BB04 from 0083 to 0083 Adjusted offset of BB05 from 009E to 009E Binding: IN002f: 000000 jbe L_M39786_BB06 Binding L_M39786_BB06to G_M39786_IG07 Estimate of fwd jump [7EAE532C/047]: 0176 -> 0189 = 0011 Shrinking jump [7EAE532C/047] Adjusted offset of BB06 from 017C to 0178 Binding: IN0031: 000000 jl L_M39786_BB04 Binding L_M39786_BB04to G_M39786_IG05 Estimate of bwd jump [7EAE54CC/049]: 017F -> 009E = 00E3 Adjusted offset of BB07 from 0189 to 0185 Binding: IN003a: 000000 ja L_M39786_BB03 Binding L_M39786_BB03to G_M39786_IG04 Estimate of bwd jump [7EAE58DC/058]: 01A1 -> 0083 = 0120 Adjusted offset of BB08 from 01AB to 01A7 Adjusted offset of BB09 from 01B2 to 01AE Binding: IN003e: 000000 jbe L_M39786_BB10 Binding L_M39786_BB10to G_M39786_IG11 Estimate of fwd jump [7EAE5BE4/062]: 01B3 -> 01C9 = 0014 Shrinking jump [7EAE5BE4/062] Adjusted offset of BB10 from 01BD to 01B5 Binding: IN0042: 000000 je L_M39786_BB02 Binding L_M39786_BB02to G_M39786_IG03 Estimate of bwd jump [7EAE5DFC/066]: 01BF -> 0071 = 0150 Adjusted offset of BB11 from 01CD to 01C5 Total shrinkage = 8, min extra jump size = 99 Hot code size = 0x200 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x26) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M39786_IG01: ; func=00, offs=000000H, size=0065H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0043: 000000 57 push rdi IN0044: 000001 56 push rsi IN0045: 000002 53 push rbx IN0046: 000003 4881ECA0000000 sub rsp, 160 IN0047: 00000A C5F877 vzeroupper IN0048: 00000D C5F829B42490000000 vmovaps qword ptr [rsp+90H], xmm6 (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN0049: 000016 C5F829BC2480000000 vmovaps qword ptr [rsp+80H], xmm7 (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN004a: 00001F C57829442470 vmovaps qword ptr [rsp+70H], xmm8 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN004b: 000025 C578294C2460 vmovaps qword ptr [rsp+60H], xmm9 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN004c: 00002B C57829542450 vmovaps qword ptr [rsp+50H], xmm10 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN004d: 000031 C578295C2440 vmovaps qword ptr [rsp+40H], xmm11 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN004e: 000037 33C0 xor rax, rax IN004f: 000039 4889442438 mov qword ptr [rsp+38H], rax gcrReg +[rsi] IN0050: 00003E 488BF1 mov rsi, rcx IN0051: 000041 C57828C1 vmovaps xmm8, xmm1 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0052: 000045 C5F828F2 vmovaps xmm6, xmm2 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0053: 000049 C57A108C24E0000000 vmovss xmm9, dword ptr [rsp+E0H] (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN0054: 000052 C5FA10BC24E8000000 vmovss xmm7, dword ptr [rsp+E8H] (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 ;; bbWeight=1 PerfScore 28.25 G_M39786_IG02: ; func=00, offs=000065H, size=000CH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 00000065, actual = 0000005B -> size adj = 10 IN0001: 00005B 33FF xor edi, edi IN0002: 00005D C57828D3 vmovaps xmm10, xmm3 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0003: 000061 E93E010000 jmp G_M39786_IG09 ;; bbWeight=1 PerfScore 2.50 G_M39786_IG03: ; func=00, offs=000071H, size=0012H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 00000071, actual = 00000066 -> size adj = 11 IN0004: 000066 33DB xor ebx, ebx IN0005: 000068 C4417828D8 vmovaps xmm11, xmm8 IN0006: 00006D C4C1782EF0 vucomiss xmm6, xmm8 IN0007: 000072 0F8624010000 jbe G_M39786_IG08 ;; bbWeight=2 PerfScore 5.00 G_M39786_IG04: ; func=00, offs=000083H, size=001BH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 00000083, actual = 00000078 -> size adj = 11 IN0008: 000078 C4C17828C3 vmovaps xmm0, xmm11 IN0009: 00007D C4C17828CA vmovaps xmm1, xmm10 IN000a: 000082 C5FA11442438 vmovss dword ptr [rsp+38H], xmm0 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN000b: 000088 C5FA114C243C vmovss dword ptr [rsp+3CH], xmm1 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN000c: 00008E 4533C9 xor r9d, r9d ;; bbWeight=16 PerfScore 28.00 G_M39786_IG05: ; func=00, offs=00009EH, size=00DAH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz Block predicted offs = 0000009E, actual = 00000091 -> size adj = 13 IN000d: 000091 C5E857D2 vxorps xmm2, xmm2 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN000e: 000095 C5FA11542430 vmovss dword ptr [rsp+30H], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN000f: 00009B C5FA11542434 vmovss dword ptr [rsp+34H], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0010: 0000A1 C5FA10542438 vmovss xmm2, dword ptr [rsp+38H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0011: 0000A7 C5EA59542438 vmulss xmm2, dword ptr [rsp+38H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0012: 0000AD C5FA105C243C vmovss xmm3, dword ptr [rsp+3CH] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0013: 0000B3 C5E2595C243C vmulss xmm3, dword ptr [rsp+3CH] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0014: 0000B9 C5EA5CD3 vsubss xmm2, xmm3 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0015: 0000BD C5FA105C2438 vmovss xmm3, dword ptr [rsp+38H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0016: 0000C3 C5E2591D35010000 vmulss xmm3, dword ptr [reloc @RWD00] (ECS:9, ACS:8) Instruction predicted size = 9, actual = 8 IN0017: 0000CB C5E2595C243C vmulss xmm3, dword ptr [rsp+3CH] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0018: 0000D1 C5FA11542430 vmovss dword ptr [rsp+30H], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0019: 0000D7 C5FA115C2434 vmovss dword ptr [rsp+34H], xmm3 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN001a: 0000DD 488B4C2430 mov rcx, qword ptr [rsp+30H] IN001b: 0000E2 48894C2438 mov qword ptr [rsp+38H], rcx IN001c: 0000E7 C5E857D2 vxorps xmm2, xmm2 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN001d: 0000EB C5FA11542428 vmovss dword ptr [rsp+28H], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN001e: 0000F1 C5FA1154242C vmovss dword ptr [rsp+2CH], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN001f: 0000F7 C5F828D0 vmovaps xmm2, xmm0 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0020: 0000FB C5EA58542438 vaddss xmm2, dword ptr [rsp+38H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0021: 000101 C5FA11542428 vmovss dword ptr [rsp+28H], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0022: 000107 C5F828D1 vmovaps xmm2, xmm1 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0023: 00010B C5EA5854243C vaddss xmm2, dword ptr [rsp+3CH] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0024: 000111 C5FA1154242C vmovss dword ptr [rsp+2CH], xmm2 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0025: 000117 488B4C2428 mov rcx, qword ptr [rsp+28H] IN0026: 00011C 48894C2438 mov qword ptr [rsp+38H], rcx IN0027: 000121 41FFC1 inc r9d IN0028: 000124 C5FA10542438 vmovss xmm2, dword ptr [rsp+38H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0029: 00012A C5EA59542438 vmulss xmm2, dword ptr [rsp+38H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN002a: 000130 C5FA105C243C vmovss xmm3, dword ptr [rsp+3CH] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN002b: 000136 C5E2595C243C vmulss xmm3, dword ptr [rsp+3CH] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN002c: 00013C C5EA58D3 vaddss xmm2, xmm3 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN002d: 000140 C5FA101DBC000000 vmovss xmm3, dword ptr [reloc @RWD04] (ECS:9, ACS:8) Instruction predicted size = 9, actual = 8 IN002e: 000148 C5F82EDA vucomiss xmm3, xmm2 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN002f: 00014C 762A jbe SHORT G_M39786_IG07 ;; bbWeight=128 PerfScore 8885.33 G_M39786_IG06: ; func=00, offs=000178H, size=000DH, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 00000178, actual = 0000014E -> size adj = 42 IN0030: 00014E 4181F9E8030000 cmp r9d, 0x3E8 IN0031: 000155 0F8C36FFFFFF jl G_M39786_IG05 ;; bbWeight=64 PerfScore 80.00 G_M39786_IG07: ; func=00, offs=000185H, size=0022H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 00000185, actual = 0000015B -> size adj = 42 gcrReg +[rax] IN0032: 00015B 488B4610 mov rax, gword ptr [rsi+16] gcrReg +[rcx] IN0033: 00015F 488B4808 mov rcx, gword ptr [rax+8] IN0034: 000163 8BD3 mov edx, ebx IN0035: 000165 448BC7 mov r8d, edi New gcrReg live regs=00000040 {rsi} gcrReg -[rax] gcrReg -[rcx] [7EAE69E8] ptr arg pop 0 IN0036: 000168 FF5018 call qword ptr [rax+24]System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32]:Invoke(int,int,int):this IN0037: 00016B C52258DF vaddss xmm11, xmm7 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0038: 00016F FFC3 inc ebx IN0039: 000171 C4C1782EF3 vucomiss xmm6, xmm11 IN003a: 000176 0F87FCFEFFFF ja G_M39786_IG04 ;; bbWeight=16 PerfScore 204.00 G_M39786_IG08: ; func=00, offs=0001A7H, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 000001A7, actual = 0000017C -> size adj = 43 IN003b: 00017C C52A58D7 vaddss xmm10, xmm7 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN003c: 000180 FFC7 inc edi ;; bbWeight=2 PerfScore 6.50 G_M39786_IG09: ; func=00, offs=0001AEH, size=0007H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz Block predicted offs = 000001AE, actual = 00000182 -> size adj = 44 IN003d: 000182 C441782ECA vucomiss xmm9, xmm10 IN003e: 000187 7610 jbe SHORT G_M39786_IG11 ;; bbWeight=8 PerfScore 16.00 G_M39786_IG10: ; func=00, offs=0001B5H, size=0010H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref Block predicted offs = 000001B5, actual = 00000189 -> size adj = 44 gcrReg +[rcx] IN003f: 000189 488BCE mov rcx, rsi New gcrReg live regs=00000040 {rsi} gcrReg -[rcx] [7EAE6AC8] ptr arg pop 0 IN0040: 00018C E8F7DFFFFF call Algorithms.FractalRenderer:get_Abort():bool:this IN0041: 000191 85C0 test eax, eax IN0042: 000193 0F84CDFEFFFF je G_M39786_IG03 ;; bbWeight=4 PerfScore 10.00 G_M39786_IG11: ; func=00, offs=0001C5H, size=003BH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc Block predicted offs = 000001C5, actual = 00000199 -> size adj = 44 New gcrReg live regs=00000000 {} gcrReg -[rsi] IN0055: 000199 C5F828B42490000000 vmovaps xmm6, qword ptr [rsp+90H] (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN0056: 0001A2 C5F828BC2480000000 vmovaps xmm7, qword ptr [rsp+80H] (ECS:10, ACS:9) Instruction predicted size = 10, actual = 9 IN0057: 0001AB C57828442470 vmovaps xmm8, qword ptr [rsp+70H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0058: 0001B1 C578284C2460 vmovaps xmm9, qword ptr [rsp+60H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0059: 0001B7 C57828542450 vmovaps xmm10, qword ptr [rsp+50H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN005a: 0001BD C578285C2440 vmovaps xmm11, qword ptr [rsp+40H] (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN005b: 0001C3 4881C4A0000000 add rsp, 160 IN005c: 0001CA 5B pop rbx IN005d: 0001CB 5E pop rsi IN005e: 0001CC 5F pop rdi IN005f: 0001CD C3 ret ;; bbWeight=1 PerfScore 26.75 Emitting data sections: 8 total bytes section 0, size 4, raw data 00 00 00 40 section 1, size 4, raw data 00 00 80 40 Allocated method code size = 512 , actual size = 462 ; Total bytes of code 462, prolog size 91, PerfScore 9343.53, (MethodHash=c129bf6f) for method Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this ; ============================================================ *************** After end code gen, before unwindEmit() G_M39786_IG01: ; func=00, offs=000000H, size=005BH, bbWeight=1 PerfScore 28.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG IN0043: 000000 push rdi IN0044: 000001 push rsi IN0045: 000002 push rbx IN0046: 000003 sub rsp, 160 IN0047: 00000A vzeroupper IN0048: 00000D vmovaps qword ptr [rsp+90H], xmm6 IN0049: 000016 vmovaps qword ptr [rsp+80H], xmm7 IN004a: 00001F vmovaps qword ptr [rsp+70H], xmm8 IN004b: 000025 vmovaps qword ptr [rsp+60H], xmm9 IN004c: 00002B vmovaps qword ptr [rsp+50H], xmm10 IN004d: 000031 vmovaps qword ptr [rsp+40H], xmm11 IN004e: 000037 xor rax, rax IN004f: 000039 mov qword ptr [V11 rsp+38H], rax IN0050: 00003E mov rsi, rcx IN0051: 000041 vmovaps xmm8, xmm1 IN0052: 000045 vmovaps xmm6, xmm2 IN0053: 000049 vmovss xmm9, dword ptr [V04 rsp+E0H] IN0054: 000052 vmovss xmm7, dword ptr [V05 rsp+E8H] G_M39786_IG02: ; offs=00005BH, size=000BH, bbWeight=1 PerfScore 2.50, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz IN0001: 00005B xor edi, edi IN0002: 00005D vmovaps xmm10, xmm3 IN0003: 000061 jmp G_M39786_IG09 G_M39786_IG03: ; offs=000066H, size=0012H, bbWeight=2 PerfScore 5.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0004: 000066 xor ebx, ebx IN0005: 000068 vmovaps xmm11, xmm8 IN0006: 00006D vucomiss xmm6, xmm8 IN0007: 000072 jbe G_M39786_IG08 G_M39786_IG04: ; offs=000078H, size=0019H, bbWeight=16 PerfScore 28.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz IN0008: 000078 vmovaps xmm0, xmm11 IN0009: 00007D vmovaps xmm1, xmm10 IN000a: 000082 vmovss dword ptr [V25 rsp+38H], xmm0 IN000b: 000088 vmovss dword ptr [V26 rsp+3CH], xmm1 IN000c: 00008E xor r9d, r9d G_M39786_IG05: ; offs=000091H, size=00BDH, bbWeight=128 PerfScore 8885.33, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz IN000d: 000091 vxorps xmm2, xmm2 IN000e: 000095 vmovss dword ptr [V27 rsp+30H], xmm2 IN000f: 00009B vmovss dword ptr [V28 rsp+34H], xmm2 IN0010: 0000A1 vmovss xmm2, dword ptr [V25 rsp+38H] IN0011: 0000A7 vmulss xmm2, dword ptr [V25 rsp+38H] IN0012: 0000AD vmovss xmm3, dword ptr [V26 rsp+3CH] IN0013: 0000B3 vmulss xmm3, dword ptr [V26 rsp+3CH] IN0014: 0000B9 vsubss xmm2, xmm3 IN0015: 0000BD vmovss xmm3, dword ptr [V25 rsp+38H] IN0016: 0000C3 vmulss xmm3, dword ptr [reloc @RWD00] IN0017: 0000CB vmulss xmm3, dword ptr [V26 rsp+3CH] IN0018: 0000D1 vmovss dword ptr [V27 rsp+30H], xmm2 IN0019: 0000D7 vmovss dword ptr [V28 rsp+34H], xmm3 IN001a: 0000DD mov rcx, qword ptr [V15 rsp+30H] IN001b: 0000E2 mov qword ptr [V11 rsp+38H], rcx IN001c: 0000E7 vxorps xmm2, xmm2 IN001d: 0000EB vmovss dword ptr [V33 rsp+28H], xmm2 IN001e: 0000F1 vmovss dword ptr [V34 rsp+2CH], xmm2 IN001f: 0000F7 vmovaps xmm2, xmm0 IN0020: 0000FB vaddss xmm2, dword ptr [V25 rsp+38H] IN0021: 000101 vmovss dword ptr [V33 rsp+28H], xmm2 IN0022: 000107 vmovaps xmm2, xmm1 IN0023: 00010B vaddss xmm2, dword ptr [V26 rsp+3CH] IN0024: 000111 vmovss dword ptr [V34 rsp+2CH], xmm2 IN0025: 000117 mov rcx, qword ptr [V20 rsp+28H] IN0026: 00011C mov qword ptr [V11 rsp+38H], rcx IN0027: 000121 inc r9d IN0028: 000124 vmovss xmm2, dword ptr [V25 rsp+38H] IN0029: 00012A vmulss xmm2, dword ptr [V25 rsp+38H] IN002a: 000130 vmovss xmm3, dword ptr [V26 rsp+3CH] IN002b: 000136 vmulss xmm3, dword ptr [V26 rsp+3CH] IN002c: 00013C vaddss xmm2, xmm3 IN002d: 000140 vmovss xmm3, dword ptr [reloc @RWD04] IN002e: 000148 vucomiss xmm3, xmm2 IN002f: 00014C jbe SHORT G_M39786_IG07 G_M39786_IG06: ; offs=00014EH, size=000DH, bbWeight=64 PerfScore 80.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0030: 00014E cmp r9d, 0x3E8 IN0031: 000155 jl G_M39786_IG05 G_M39786_IG07: ; offs=00015BH, size=0021H, bbWeight=16 PerfScore 204.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz IN0032: 00015B mov rax, gword ptr [rsi+16] IN0033: 00015F mov rcx, gword ptr [rax+8] IN0034: 000163 mov edx, ebx IN0035: 000165 mov r8d, edi IN0036: 000168 call qword ptr [rax+24]System.Action`3[Int32,Int32,Int32][System.Int32,System.Int32,System.Int32]:Invoke(int,int,int):this IN0037: 00016B vaddss xmm11, xmm7 IN0038: 00016F inc ebx IN0039: 000171 vucomiss xmm6, xmm11 IN003a: 000176 ja G_M39786_IG04 G_M39786_IG08: ; offs=00017CH, size=0006H, bbWeight=2 PerfScore 6.50, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz IN003b: 00017C vaddss xmm10, xmm7 IN003c: 000180 inc edi G_M39786_IG09: ; offs=000182H, size=0007H, bbWeight=8 PerfScore 16.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref, isz IN003d: 000182 vucomiss xmm9, xmm10 IN003e: 000187 jbe SHORT G_M39786_IG11 G_M39786_IG10: ; offs=000189H, size=0010H, bbWeight=4 PerfScore 10.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN003f: 000189 mov rcx, rsi IN0040: 00018C call Algorithms.FractalRenderer:get_Abort():bool:this IN0041: 000191 test eax, eax IN0042: 000193 je G_M39786_IG03 G_M39786_IG11: ; offs=000199H, size=0035H, bbWeight=1 PerfScore 26.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc, isz IN0055: 000199 vmovaps xmm6, qword ptr [rsp+90H] IN0056: 0001A2 vmovaps xmm7, qword ptr [rsp+80H] IN0057: 0001AB vmovaps xmm8, qword ptr [rsp+70H] IN0058: 0001B1 vmovaps xmm9, qword ptr [rsp+60H] IN0059: 0001B7 vmovaps xmm10, qword ptr [rsp+50H] IN005a: 0001BD vmovaps xmm11, qword ptr [rsp+40H] IN005b: 0001C3 add rsp, 160 IN005c: 0001CA pop rbx IN005d: 0001CB pop rsi IN005e: 0001CC pop rdi IN005f: 0001CD ret Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x0001ce (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x3D CountOfUnwindCodes: 17 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x3D UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM11 (11) Scaled Small Offset: 4 * 16 = 64 = 0x00040 CodeOffset: 0x36 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM10 (10) Scaled Small Offset: 5 * 16 = 80 = 0x00050 CodeOffset: 0x2F UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM9 (9) Scaled Small Offset: 6 * 16 = 96 = 0x00060 CodeOffset: 0x28 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM8 (8) Scaled Small Offset: 7 * 16 = 112 = 0x00070 CodeOffset: 0x21 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM7 (7) Scaled Small Offset: 8 * 16 = 128 = 0x00080 CodeOffset: 0x17 UnwindOp: UWOP_SAVE_XMM128 (8) OpInfo: XMM6 (6) Scaled Small Offset: 9 * 16 = 144 = 0x00090 CodeOffset: 0x0A UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small Size: 20 * 8 = 160 = 0x000A0 CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) allocUnwindInfo(pHotCode=0x00007FFB22FB6AA0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x1ce, unwindSize=0x26, pUnwindBlock=0x000001987EA9D6EA, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 22 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x0000005B ( STACK_EMPTY ) IL offs 0x0002 : 0x0000005D ( STACK_EMPTY ) IL offs 0x0006 : 0x00000066 ( STACK_EMPTY ) IL offs 0x0008 : 0x00000068 ( STACK_EMPTY ) IL offs 0x0070 : 0x0000006D ( STACK_EMPTY ) IL offs 0x000C : 0x00000078 ( STACK_EMPTY ) IL offs 0x0015 : 0x00000082 ( STACK_EMPTY ) IL offs 0x0019 : 0x0000008E ( STACK_EMPTY ) IL offs 0x0023 : 0x00000091 ( STACK_EMPTY ) IL offs 0x002C : 0x000000E7 ( STACK_EMPTY ) IL offs 0x0037 : 0x00000121 ( STACK_EMPTY ) IL offs 0x0046 : 0x00000140 ( STACK_EMPTY ) IL offs 0x004F : 0x0000014E ( STACK_EMPTY ) IL offs 0x0067 : 0x0000016B ( STACK_EMPTY ) IL offs 0x006C : 0x0000016F ( STACK_EMPTY ) IL offs 0x0070 : 0x00000171 ( STACK_EMPTY ) IL offs 0x0074 : 0x0000017C ( STACK_EMPTY ) IL offs 0x0079 : 0x00000180 ( STACK_EMPTY ) IL offs 0x007D : 0x00000182 ( STACK_EMPTY ) IL offs 0x008D : 0x00000199 ( STACK_EMPTY ) IL offs EPILOG : 0x00000199 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 20 *************** Variable debug info 20 live ranges 0( UNKNOWN) : From 00000000h to 0000005Bh, in rcx 1( UNKNOWN) : From 00000000h to 0000005Bh, in mm1 2( UNKNOWN) : From 00000000h to 0000005Bh, in mm2 3( UNKNOWN) : From 00000000h to 0000005Bh, in mm3 4( UNKNOWN) : From 00000000h to 0000005Bh, in rsp[40] (1 slot) 5( UNKNOWN) : From 00000000h to 0000005Bh, in rsp[48] (1 slot) 3( UNKNOWN) : From 0000005Bh to 0000005Dh, in mm3 12( UNKNOWN) : From 00000091h to 00000121h, in r9 12( UNKNOWN) : From 0000014Eh to 00000168h, in r9 9( UNKNOWN) : From 00000078h to 0000016Bh, in mm11 8( UNKNOWN) : From 00000078h to 0000016Fh, in rbx 7( UNKNOWN) : From 00000066h to 0000017Ch, in mm10 6( UNKNOWN) : From 00000066h to 00000180h, in rdi 0( UNKNOWN) : From 0000005Bh to 00000199h, in rsi 6( UNKNOWN) : From 00000182h to 00000199h, in rdi 7( UNKNOWN) : From 00000182h to 00000199h, in mm10 2( UNKNOWN) : From 0000005Bh to 00000199h, in mm6 5( UNKNOWN) : From 0000005Bh to 00000199h, in mm7 1( UNKNOWN) : From 0000005Bh to 00000199h, in mm8 4( UNKNOWN) : From 0000005Bh to 00000199h, in mm9 *************** In gcInfoBlockHdrSave() Set code length to 462. Set ReturnKind to Scalar. Set Outgoing stack arg area size to 32. Register slot id for reg rsi = 0. Register slot id for reg rax = 1. Register slot id for reg rcx = 2. Set state of slot 0 at instr offset 0x41 to Live. Set state of slot 1 at instr offset 0x15f to Live. Set state of slot 2 at instr offset 0x163 to Live. Set state of slot 1 at instr offset 0x16b to Dead. Set state of slot 2 at instr offset 0x16b to Dead. Set state of slot 2 at instr offset 0x18c to Live. Set state of slot 2 at instr offset 0x191 to Dead. Set state of slot 0 at instr offset 0x199 to Dead. Defining interruptible range: [0x5b, 0x199). Method code size: 462 Allocations for Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this (MethodHash=c129bf6f) count: 3027, size: 225560, max = 5160 allocateMemory: 262144, nraUsed: 232208 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 2.86% ASTNode | 44032 | 19.52% InstDesc | 9116 | 4.04% ImpStack | 384 | 0.17% BasicBlock | 5888 | 2.61% fgArgInfo | 280 | 0.12% fgArgInfoPtrArr | 40 | 0.02% FlowList | 640 | 0.28% TreeStatementList | 0 | 0.00% SiScope | 1464 | 0.65% DominatorMemory | 528 | 0.23% LSRA | 4240 | 1.88% LSRA_Interval | 4840 | 2.15% LSRA_RefPosition | 12352 | 5.48% Reachability | 16 | 0.01% SSA | 4688 | 2.08% ValueNumber | 15283 | 6.78% LvaTable | 8804 | 3.90% UnwindInfo | 0 | 0.00% hashBv | 528 | 0.23% bitset | 528 | 0.23% FixedBitVect | 96 | 0.04% Generic | 3890 | 1.72% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 176 | 0.08% ZeroOffsetFieldMap | 320 | 0.14% ArrayInfoMap | 40 | 0.02% MemoryPhiArg | 96 | 0.04% CSE | 2608 | 1.16% GC | 2764 | 1.23% CorSig | 728 | 0.32% Inlining | 5416 | 2.40% ArrayStack | 0 | 0.00% DebugInfo | 1264 | 0.56% DebugOnly | 80493 | 35.69% Codegen | 1128 | 0.50% LoopOpt | 2560 | 1.13% LoopHoist | 936 | 0.41% Unknown | 814 | 0.36% RangeCheck | 0 | 0.00% CopyProp | 2048 | 0.91% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 72 | 0.03% TailMergeThrows | 0 | 0.00% ****** DONE compiling Algorithms.ScalarFloatRenderer:RenderSingleThreadedWithADT(float,float,float,float,float):this