-
Notifications
You must be signed in to change notification settings - Fork 0
/
ram.v
322 lines (306 loc) · 10.1 KB
/
ram.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
// megafunction wizard: %RAM initializer%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTMEM_INIT
// ============================================================
// File Name: ram.v
// Megafunction Name(s):
// ALTMEM_INIT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 22.1std.2 Build 922 07/20/2023 SC Lite Edition
// ************************************************************
//Copyright (C) 2023 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" INIT_TO_ZERO="YES" NUMWORDS=10000 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=14 clock dataout init init_busy ram_address ram_wren
//VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2023:07:21:07:12:20:SC cbx_altmem_init 2023:07:21:07:12:21:SC cbx_altsyncram 2023:07:21:07:12:21:SC cbx_cycloneii 2023:07:21:07:12:21:SC cbx_lpm_add_sub 2023:07:21:07:12:21:SC cbx_lpm_compare 2023:07:21:07:12:21:SC cbx_lpm_counter 2023:07:21:07:12:21:SC cbx_lpm_decode 2023:07:21:07:12:20:SC cbx_lpm_mux 2023:07:21:07:12:21:SC cbx_mgl 2023:07:21:07:12:36:SC cbx_nadder 2023:07:21:07:12:21:SC cbx_stratix 2023:07:21:07:12:21:SC cbx_stratixii 2023:07:21:07:12:21:SC cbx_stratixiii 2023:07:21:07:12:21:SC cbx_stratixv 2023:07:21:07:12:21:SC cbx_util_mgl 2023:07:21:07:12:21:SC VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_compare 2 lpm_counter 2 reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ram_meminit_qfk
(
clock,
dataout,
init,
init_busy,
ram_address,
ram_wren) ;
input clock;
output [7:0] dataout;
input init;
output init_busy;
output [13:0] ram_address;
output ram_wren;
reg [0:0] capture_init;
reg [1:0] prev_state;
wire [1:0] wire_state_reg_d;
reg [1:0] state_reg;
wire [1:0] wire_state_reg_sclr;
wire [1:0] wire_state_reg_sload;
wire wire_addr_cmpr_aeb;
wire wire_addr_cmpr_alb;
wire wire_wait_cmpr_aeb;
wire wire_wait_cmpr_alb;
wire [13:0] wire_addr_ctr_q;
wire [0:0] wire_wait_ctr_q;
wire [0:0] addrct_eq_numwords;
wire [0:0] addrct_lt_numwords;
wire clken;
wire [0:0] done_state;
wire [0:0] idle_state;
wire [0:0] ram_addr_state;
wire [0:0] ram_write_state;
wire [0:0] reset_state_machine;
wire [0:0] state_machine_clken;
wire [0:0] waitct_eq_latency;
wire [0:0] waitct_lt_latency;
// synopsys translate_off
initial
capture_init = 0;
// synopsys translate_on
always @ ( posedge clock)
if (clken == 1'b1) capture_init <= ((init | capture_init) & (~ done_state));
// synopsys translate_off
initial
prev_state = 0;
// synopsys translate_on
always @ ( posedge clock)
if (clken == 1'b1) prev_state <= state_reg;
// synopsys translate_off
initial
state_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock)
if (state_machine_clken == 1'b1)
if (wire_state_reg_sclr[0:0] == 1'b1) state_reg[0:0] <= 1'b0;
else if (wire_state_reg_sload[0:0] == 1'b1) state_reg[0:0] <= 1;
else state_reg[0:0] <= wire_state_reg_d[0:0];
// synopsys translate_off
initial
state_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock)
if (state_machine_clken == 1'b1)
if (wire_state_reg_sclr[1:1] == 1'b1) state_reg[1:1] <= 1'b0;
else if (wire_state_reg_sload[1:1] == 1'b1) state_reg[1:1] <= 1;
else state_reg[1:1] <= wire_state_reg_d[1:1];
assign
wire_state_reg_d = {(state_reg[1] ^ state_reg[0]), (~ state_reg[0])};
assign
wire_state_reg_sclr = {reset_state_machine, 1'b0},
wire_state_reg_sload = {1'b0, reset_state_machine};
lpm_compare addr_cmpr
(
.aeb(wire_addr_cmpr_aeb),
.agb(),
.ageb(),
.alb(wire_addr_cmpr_alb),
.aleb(),
.aneb(),
.dataa(wire_addr_ctr_q),
.datab(14'b10011100001111)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addr_cmpr.lpm_width = 14,
addr_cmpr.lpm_type = "lpm_compare";
lpm_compare wait_cmpr
(
.aeb(wire_wait_cmpr_aeb),
.agb(),
.ageb(),
.alb(wire_wait_cmpr_alb),
.aleb(),
.aneb(),
.dataa(wire_wait_ctr_q),
.datab(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
wait_cmpr.lpm_width = 1,
wait_cmpr.lpm_type = "lpm_compare";
lpm_counter addr_ctr
(
.clk_en(clken),
.clock(clock),
.cnt_en((prev_state[1] & (~ prev_state[0]))),
.cout(),
.eq(),
.q(wire_addr_ctr_q),
.sclr(idle_state)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.data({14{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addr_ctr.lpm_direction = "UP",
addr_ctr.lpm_modulus = 10000,
addr_ctr.lpm_port_updown = "PORT_UNUSED",
addr_ctr.lpm_width = 14,
addr_ctr.lpm_type = "lpm_counter";
lpm_counter wait_ctr
(
.clk_en(clken),
.clock(clock),
.cnt_en(ram_addr_state),
.cout(),
.eq(),
.q(wire_wait_ctr_q),
.sclr((~ ram_addr_state))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.data({1{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
wait_ctr.lpm_direction = "UP",
wait_ctr.lpm_modulus = 1,
wait_ctr.lpm_port_updown = "PORT_UNUSED",
wait_ctr.lpm_width = 1,
wait_ctr.lpm_type = "lpm_counter";
assign
addrct_eq_numwords = wire_addr_cmpr_aeb,
addrct_lt_numwords = wire_addr_cmpr_alb,
clken = 1'b1,
dataout = {8{1'b0}},
done_state = (state_reg[1] & state_reg[0]),
idle_state = ((~ state_reg[1]) & (~ state_reg[0])),
init_busy = capture_init,
ram_addr_state = ((~ state_reg[1]) & state_reg[0]),
ram_address = wire_addr_ctr_q,
ram_wren = ((~ prev_state[1]) & prev_state[0]),
ram_write_state = (state_reg[1] & (~ state_reg[0])),
reset_state_machine = (ram_write_state & addrct_lt_numwords),
state_machine_clken = (clken & (((idle_state & capture_init) | (done_state & waitct_eq_latency)) | (capture_init & (((~ (ram_addr_state & waitct_lt_latency)) | (ram_addr_state & waitct_eq_latency)) | (ram_write_state & addrct_eq_numwords))))),
waitct_eq_latency = wire_wait_cmpr_aeb,
waitct_lt_latency = wire_wait_cmpr_alb;
endmodule //ram_meminit_qfk
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram (
clock,
init,
dataout,
init_busy,
ram_address,
ram_wren);
input clock;
input init;
output [7:0] dataout;
output init_busy;
output [13:0] ram_address;
output ram_wren;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [13:0] sub_wire2;
wire sub_wire3;
wire [7:0] dataout = sub_wire0[7:0];
wire init_busy = sub_wire1;
wire [13:0] ram_address = sub_wire2[13:0];
wire ram_wren = sub_wire3;
ram_meminit_qfk ram_meminit_qfk_component (
.clock (clock),
.init (init),
.dataout (sub_wire0),
.init_busy (sub_wire1),
.ram_address (sub_wire2),
.ram_wren (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INIT_FILE STRING "UNUSED"
// Retrieval info: CONSTANT: INIT_TO_ZERO STRING "YES"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init"
// Retrieval info: CONSTANT: NUMWORDS NUMERIC "10000"
// Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD NUMERIC "14"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
// Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
// Retrieval info: USED_PORT: init 0 0 0 0 INPUT NODEFVAL "init"
// Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0
// Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy"
// Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0
// Retrieval info: USED_PORT: ram_address 0 0 14 0 OUTPUT NODEFVAL "ram_address[13..0]"
// Retrieval info: CONNECT: ram_address 0 0 14 0 @ram_address 0 0 14 0
// Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren"
// Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm