getting-started.v.bak

module blink (
	input wire clk, 
	output wire LED, 
	output wire LE 
);


reg [31:0] cnt;


initial begin

cnt <= 32'h00000000; 

end


always @(posedge clk) begin

cnt<= cnt + 1; 

end


assign LED = cnt[24];
assign LE = cnt[25];

endmodule