{"payload":{"header_redesign_enabled":false,"results":[{"id":"93193187","archived":false,"color":"#adb2cb","followers":11,"has_funding_file":false,"hl_name":"aminrashidbeigi/SAYEH","hl_trunc_description":"SAYEH cpu-memory basic computer","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":93193187,"name":"SAYEH","owner_id":16760509,"owner_login":"aminrashidbeigi","updated_at":"2017-07-12T13:48:40.313Z","has_issues":true}},"sponsorable":false,"topics":["cpu","vhdl","basic-computer","sayeh","vhdl-basic-cumputer","basic-cumputer","vhdl-controller","vhdl-alu","vhdl-address-logic","vhdl-datapath","vhdl-memory"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":63,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aaminrashidbeigi%252FSAYEH%2B%2Blanguage%253AVHDL","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/aminrashidbeigi/SAYEH/star":{"post":"6D1udkH-b10JVgzj_0wqfiTFSRVZchTcenaly30l3ZhM61NTvXg3ObWP-XUPigUnPnyZOR7lttug2USpy5RH-w"},"/aminrashidbeigi/SAYEH/unstar":{"post":"jlx8DzYqe9PeJKfZ2QroiTQc1fJzKz7Bkjt9FLvRjF5K3aPEnxesXCpBaqYGDF2hT8xE_n38swLD0P07l8sFAA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"qPw7X-ii44sfCNNbMOKLWceJ0Dps-7jYAfxv4Ah-hEU63SnwnWl-tWhwpi9UHc_ZemyMyq1cqbtJ7QrB9iac0A"}}},"title":"Repository search results"}