From dc230ae98b06c3f0fe902812c558ae1ce79e7bf9 Mon Sep 17 00:00:00 2001
From: rowanG077 <goemansrowan@gmail.com>
Date: Sun, 11 Jun 2023 09:04:43 +0200
Subject: [PATCH] Timing: Fix combinational paths through all ports

Fixes https://github.com/YosysHQ/nextpnr/issues/1174
---
 common/kernel/timing.cc | 48 +++++++++++++++++++----------------------
 1 file changed, 22 insertions(+), 26 deletions(-)

diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc
index 7888e34a2f..df159c7913 100644
--- a/common/kernel/timing.cc
+++ b/common/kernel/timing.cc
@@ -113,23 +113,21 @@ void TimingAnalyser::get_cell_delays()
                                               info.edge);
                 }
             }
-            // Combinational delays through cell
-            else if (cls == TMG_COMB_INPUT) {
-                for (auto &other_port : ci->ports) {
-                    auto &op = other_port.second;
-                    // ignore dangling ports and non-outputs
-                    if (op.net == nullptr || op.type != PORT_OUT)
-                        continue;
-                    DelayQuad delay;
-                    bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
-                    if (is_path)
-                        pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
-                }
-            }
             // asynchronous endpoint
             else if (cls == TMG_ENDPOINT) {
                 pd.cell_arcs.emplace_back(CellArc::ENDPOINT, async_clk_key.key.clock, DelayQuad {});
             }
+            // Combinational delays through cell
+            for (auto &other_port : ci->ports) {
+                auto &op = other_port.second;
+                // ignore dangling ports and non-outputs
+                if (op.net == nullptr || op.type != PORT_OUT)
+                    continue;
+                DelayQuad delay;
+                bool is_path = ctx->getCellDelay(ci, name, other_port.first, delay);
+                if (is_path)
+                    pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+            }
         } else if (pi.type == PORT_OUT) {
             // Output ports might have clk-to-q relationships
             if (cls == TMG_REGISTER_OUTPUT) {
@@ -140,23 +138,21 @@ void TimingAnalyser::get_cell_delays()
                     pd.cell_arcs.emplace_back(CellArc::CLK_TO_Q, info.clock_port, info.clockToQ, info.edge);
                 }
             }
-            // Combinational delays through cell
-            else if (cls == TMG_COMB_OUTPUT) {
-                for (auto &other_port : ci->ports) {
-                    auto &op = other_port.second;
-                    // ignore dangling ports and non-inputs
-                    if (op.net == nullptr || op.type != PORT_IN)
-                        continue;
-                    DelayQuad delay;
-                    bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
-                    if (is_path)
-                        pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
-                }
-            }
             // Asynchronous startpoint
             else if (cls == TMG_STARTPOINT) {
                 pd.cell_arcs.emplace_back(CellArc::STARTPOINT, async_clk_key.key.clock, DelayQuad {});
             }
+            // Combinational delays through cell
+            for (auto &other_port : ci->ports) {
+                auto &op = other_port.second;
+                // ignore dangling ports and non-inputs
+                if (op.net == nullptr || op.type != PORT_IN)
+                    continue;
+                DelayQuad delay;
+                bool is_path = ctx->getCellDelay(ci, other_port.first, name, delay);
+                if (is_path)
+                    pd.cell_arcs.emplace_back(CellArc::COMBINATIONAL, other_port.first, delay);
+            }
         }
     }
 }