From 9b71b914efc330498c414dc8b443e42b8087aef5 Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 28 Jul 2018 09:53:55 +0200 Subject: [PATCH 01/90] improved reliability using sector erase,write,verify retry --- programmer/tinyprog/__init__.py | 83 ++++++++++++++++++++++++++------- 1 file changed, 66 insertions(+), 17 deletions(-) diff --git a/programmer/tinyprog/__init__.py b/programmer/tinyprog/__init__.py index 104eed6..f347288 100644 --- a/programmer/tinyprog/__init__.py +++ b/programmer/tinyprog/__init__.py @@ -167,7 +167,7 @@ def _read_metadata(self): import math meta_roots = ( [self._parse_json(self.prog.read_security_register_page(p).replace(b"\x00", b"").replace(b"\xff", b"")) for p in [1, 2, 3]] + - [self._parse_json(self.prog.read(int(math.pow(2, p) - (4 * 1024)), (4 * 1024)).replace(b"\x00", b"").replace(b"\xff", b"")) for p in [17, 18, 19, 20, 21, 22, 23, 24]] + [self._parse_json(self.prog.read(int(math.pow(2, p) - (4 * 1024)), (4 * 1024) - 256).replace(b"\x00", b"").replace(b"\xff", b"")) for p in [17, 18, 19, 20, 21, 22, 23, 24]] ) meta_roots = [root for root in meta_roots if root is not None] if len(meta_roots) > 0: @@ -273,11 +273,14 @@ def read(self, addr, length, disable_progress=True): with tqdm(desc=" Reading", unit="B", unit_scale=True, total=length, disable=disable_progress) as pbar: while length > 0: read_length = min(255, length) - data += self.cmd(0x0b, addr, b'\x00', read_len=read_length) - self.progress(read_length) - addr += read_length - length -= read_length - pbar.update(read_length) + read_payload = self.cmd(0x0b, addr, b'\x00', read_len=read_length) + payload_length = len(read_payload) + if payload_length > 0: + data += read_payload + self.progress(payload_length) + addr += payload_length + length -= payload_length + pbar.update(payload_length) return data def write_enable(self): @@ -301,12 +304,32 @@ def _erase(self, addr, length): self.wait_while_busy() def erase(self, addr, length, disable_progress=True): + return self.program_sectors(addr, length, disable_progress) + + # for each sector: erase,program,verify + # this programming is much more reliable than previous program() + # because each written sector will be verified and in case of + # error, retried several times + # if integer value is passed to data, this will erase that much bytes + def program_sectors(self, addr, data, disable_progress=True, verify_only=False, retry=10): possible_lengths = (1, 4 * 1024, 32 * 1024, 64 * 1024) - - with tqdm(desc=" Erasing", unit="B", unit_scale=True, total=length, disable=disable_progress) as pbar: - while length > 0: + retries_remaining = retry + data_enable = False + description = " Erasing" + try: + if len(data) > 0: + length = len(data) + description = " Writing" + data_enable = True + except: + length = data # probably integer = number of bytes to erase + offset = 0 + write_addr = addr + offset + if verify_only == False: + with tqdm(desc=description, unit="B", unit_scale=True, total=length, disable=disable_progress) as pbar: + while length > 0 and retries_remaining > 0: erase_length = max(p for p in possible_lengths - if p <= length and addr % p == 0) + if p <= length and write_addr % p == 0) if erase_length == 1: # there are no opcode to erase that much @@ -320,8 +343,8 @@ def erase(self, addr, length, disable_progress=True): # +------------------+------------------+----------------+ # <- start_length -> <- erase_length -> <- end_length -> - start_addr = addr & 0xfff000 - start_length = addr & 0xfff + start_addr = write_addr & 0xfff000 + start_length = write_addr & 0xfff erase_length = min(0x1000 - start_length, length) end_addr = start_addr + start_length + erase_length end_length = start_addr + 0x1000 - end_addr @@ -344,12 +367,38 @@ def erase(self, addr, length, disable_progress=True): else: # there is an opcode to erase that much data self.progress(erase_length) - self._erase(addr, erase_length) + self._erase(write_addr, erase_length) + + if data_enable: + # write part of the data into erased place + write_data = data[offset : offset + erase_length] + self.write(write_addr, write_data) + read_back = self.read(write_addr, erase_length) + else: + # forces retry compare to succeed + # todo: compare erased sector against 0xFF + write_data = None + read_back = None # update - length -= erase_length - addr += erase_length - pbar.update(erase_length) + if read_back == write_data: + length -= erase_length + write_addr += erase_length + offset += erase_length + retries_remaining = retry + pbar.update(erase_length) + else: + retries_remaining -= 1 + + if data_enable: + read_back = self.read(addr, len(data), disable_progress=disable_progress) + + if read_back == data: + self.progress("Success!") + return True + else: + self.progress("Failure!") + return False # don't use this directly, use the public "write" function instead def _write(self, addr, data): @@ -416,4 +465,4 @@ def program_bitstream(self, addr, bitstream): self.progress("Waking up SPI flash") self.wake() self.progress(str(len(bitstream)) + " bytes to program") - return self.program(addr, bitstream) + return self.program_sectors(addr, bitstream, disable_progress=False) From 6798b2a2626ae6c3ccca66e39bdf8320e1bf75e1 Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 28 Jul 2018 10:38:57 +0200 Subject: [PATCH 02/90] --no-boot option --- programmer/tinyprog/__main__.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/programmer/tinyprog/__main__.py b/programmer/tinyprog/__main__.py index 4b6cf57..1f3d7dd 100644 --- a/programmer/tinyprog/__main__.py +++ b/programmer/tinyprog/__main__.py @@ -188,6 +188,8 @@ def parse_int(str_value): parser.add_argument("-b", "--boot", action="store_true", help="command the FPGA board to exit the " "bootloader and load the user configuration") + parser.add_argument("--no-boot", action="store_true", + help="don't boot after programing") parser.add_argument("-c", "--com", type=str, help="serial port name") parser.add_argument("-i", "--id", type=str, help="FPGA board ID") parser.add_argument("-d", "--device", type=str, default="1d50:6130", @@ -331,7 +333,8 @@ def progress(info): if not fpga.program_bitstream(addr, bitstream): sys.exit(1) - fpga.boot() + if not args.no_boot: + fpga.boot() print("") sys.exit(0) @@ -340,7 +343,6 @@ def progress(info): print(" Booting " + str(active_port)) with active_port: fpga = TinyProg(active_port) - fpga.boot() print("") From 6f026024140727299b8b46747d05f378798952e2 Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 28 Jul 2018 09:59:11 +0200 Subject: [PATCH 03/90] delete last "," before ")" to fix verilog syntax error --- common/serial.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/serial.v b/common/serial.v index 360d204..b776c70 100644 --- a/common/serial.v +++ b/common/serial.v @@ -11,7 +11,7 @@ module width_adapter #( output data_out_put, input data_out_free, - output [OUTPUT_WIDTH-1:0] data_out, + output [OUTPUT_WIDTH-1:0] data_out ); generate From c623c0d232c0c3d4b847873233f982027c51d159 Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 28 Jul 2018 10:00:05 +0200 Subject: [PATCH 04/90] reset input resets LED fade state, making reset visible --- common/tinyfpga_bootloader.v | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/common/tinyfpga_bootloader.v b/common/tinyfpga_bootloader.v index 578ca22..922d5a0 100644 --- a/common/tinyfpga_bootloader.v +++ b/common/tinyfpga_bootloader.v @@ -74,7 +74,11 @@ module tinyfpga_bootloader ( end end end - always @(posedge clk_48mhz) pwm_cnt <= pwm_cnt + 1'b1; + always @(posedge clk_48mhz) + if (reset) + pwm_cnt <= 0; + else + pwm_cnt <= pwm_cnt + 1'b1; assign led = led_pwm > pwm_cnt; From ac2741b1883766c9a0dd800551d34e6f6eb37828 Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 28 Jul 2018 10:18:31 +0200 Subject: [PATCH 05/90] ulx3s board support --- boards/ulx3s-v1.7-45f/Makefile | 127 +++++ boards/ulx3s-v1.7-45f/bootloader.ldf | 62 +++ boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v | 75 +++ boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v | 75 +++ .../constraints/ulx3s_v17patch.lpf | 435 ++++++++++++++++++ .../initialize/boardmeta4MB.bin | 119 +++++ .../initialize/boardmeta8MB.bin | 58 +++ .../initialize/initialize4MB.sh | 30 ++ .../initialize/initialize8MB.sh | 31 ++ boards/ulx3s-v1.7-45f/initialize/jump.py | 95 ++++ boards/ulx3s-v1.7-45f/tinyfpga_45k.bit | 1 + ...fpga_45k_multiboot_flash_micron_32mbit.svf | 1 + ...fpga_45k_multiboot_flash_micron_32mbit.vme | 1 + ...ga_45k_multiboot_flash_spansion_64mbit.svf | 1 + ...ga_45k_multiboot_flash_spansion_64mbit.vme | 1 + boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf | 1 + boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme | 1 + boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v | 108 +++++ .../ulx3s_45f_flash_micron_32mbit.xcf | 104 +++++ .../ulx3s_45f_flash_spansion_64mbit.xcf | 104 +++++ .../ulx3s_45f_multiboot_micron_32mbit.xcf | 104 +++++ .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 104 +++++ boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf | 48 ++ 23 files changed, 1686 insertions(+) create mode 100644 boards/ulx3s-v1.7-45f/Makefile create mode 100644 boards/ulx3s-v1.7-45f/bootloader.ldf create mode 100644 boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v create mode 100644 boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v create mode 100644 boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf create mode 100644 boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin create mode 100644 boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin create mode 100755 boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh create mode 100755 boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh create mode 100755 boards/ulx3s-v1.7-45f/initialize/jump.py create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k.bit create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf create mode 120000 boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme create mode 100644 boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v create mode 100644 boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf diff --git a/boards/ulx3s-v1.7-45f/Makefile b/boards/ulx3s-v1.7-45f/Makefile new file mode 100644 index 0000000..7990438 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/Makefile @@ -0,0 +1,127 @@ + +PROJ_FILE := $(shell ls *.ldf | head -1) +PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) +IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) +IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) + +DIAMOND_BASE := /usr/local/diamond +DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) +DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) +DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) + +OPENOCD_BASE := ../../programmer/openocd/ulx3s/ + +# name of the project as defined in project file +PROJECT = project + +# FPGA flashing device for programming +FPGA_DEVICE = LFE5U-45F + +JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml +JUNK += dummy_sym.sort project_tcl.html promote.xml +JUNK += generate_core.tcl generate_ngd.tcl msg_file.log +JUNK += project_tcr.dir + +all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf + +$(PROJECT)/$(PROJECT)_$(PROJECT).bit: + echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} + +# same file with different name required for multiboot to work +$(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + cp $< $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_sram.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_sram.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT).mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_flash_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 32 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_micron_32mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + dd if=/dev/zero of=/tmp/zero.bit bs=1k count=300 + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 64 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_spansion_64mbit.xcf -of $@ + +program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + echo pgr_project open ulx3s_45f_sram.xcf \; pgr_program run | ${DIAMONDC} + +program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-45f.ocd + +program_web: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + svfupload.py ulx3s.lan $< + +program_web_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf + svfupload.py ulx3s.lan $< + +program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-45f.ocd + +program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + +program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme + FleaFPGA-JTAG $< + +program_flea_flash_spansion: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme + FleaFPGA-JTAG $< + +#$(PROJECT)/$(PROJECT)_$(PROJECT).jed: +# echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -fullvme -if sparrowhawk_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ + +flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme + ${PROGRAMMERC} $< + # after this, to gain access to serial port on linux + # rmmod ftdi_sio; modprobe ftdi_sio + +# example another project +#%.svf : %.jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ +# mv -f $@ $@.flash +# ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ +# mv -f $@ $@.sram +# ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ + +clean: + rm -rf $(JUNK) *~ diff --git a/boards/ulx3s-v1.7-45f/bootloader.ldf b/boards/ulx3s-v1.7-45f/bootloader.ldf new file mode 100644 index 0000000..b725c28 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/bootloader.ldf @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v b/boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v new file mode 100644 index 0000000..2e9bb80 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_200M_48M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 200.00 -fclkop 48.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_200M_48M/clk_200M_48M.fdc */ +/* Wed Jul 11 00:10:22 2018 */ + + +`timescale 1 ns / 1 ps +module clk_200M_48M (CLKI, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire LOCK; + + wire REFCLK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 11 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 12 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 25 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="48.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="200.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 200.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v b/boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v new file mode 100644 index 0000000..0ce5c18 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_200M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 200.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_25M_200M/clk_25M_200M.fdc */ +/* Wed Jul 11 00:09:44 2018 */ + + +`timescale 1 ns / 1 ps +module clk_25M_200M (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire REFCLK; + wire LOCK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 2 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 3 ; + defparam PLLInst_0.CLKFB_DIV = 8 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="200.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="25.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 200.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf new file mode 100644 index 0000000..8e0d34c --- /dev/null +++ b/boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf @@ -0,0 +1,435 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v1.7 patched towards v1.8 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "W1"; # UP +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "Y2"; # RIGHT +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "J1"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J3"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "K2"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "K1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "H2"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "H1"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; +LOCATE COMP "wifi_gpio17" SITE "N3"; +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Read + +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_clkp" SITE "A17"; # Clock + +LOCATE COMP "gpdi_clkn" SITE "B18"; # Clock - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "C12"; # I2C shared with RTC +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "D15"; # J2_25+ GP22 +LOCATE COMP "gn[22]" SITE "E15"; # J2_25- GN22 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "B15"; # J2_31+ GP25 +LOCATE COMP "gn[25]" SITE "C15"; # J2_31- GN25 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin b/boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin new file mode 100644 index 0000000..7a525c7 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin @@ -0,0 +1,119 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x2FFFFF", + "userdata": "0x300000-0x3FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin b/boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin new file mode 100644 index 0000000..89be03c --- /dev/null +++ b/boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin @@ -0,0 +1,58 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x3FFFFF", + "userdata": "0x500000-0x7FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh b/boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh new file mode 100755 index 0000000..3d67d93 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh @@ -0,0 +1,30 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x3FF000) # flash size - 0x1000 +jump_command_address=$(printf "%d" 0x3FFF00) # flash size - 0x100 + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta4MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh b/boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh new file mode 100755 index 0000000..b127f53 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh @@ -0,0 +1,31 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 8 Mbit = 1 MB = 0x100000 +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x7FF000) # flash size - 0x1000 (-4KB) +jump_command_address=$(printf "%d" 0x7FFF00) # flash size - 0x100 (-256) + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta8MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v1.7-45f/initialize/jump.py b/boards/ulx3s-v1.7-45f/initialize/jump.py new file mode 100755 index 0000000..b1ff948 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/initialize/jump.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# Lattice ECP5 jump command generator +# TN1216 p.23 describes the jump command syntax which does not work. +# The syntax has been fixed by looking at dual boot intel hex file +# generated by diamond, this actually works. + +import struct +import sys + +# write output of this funtion at FLASH address: +# jump_command_address = 0x3FFF00 = 4194048 + +# write "golden" bitstream at FLASH address: +golden_image_address = 0x140000 +golden_image_address = int(sys.argv[1]) + +# normally both 0 +reverse_bytes = 0 +reverse_bits = 0 + +# to compare with intel HEX file generated by diamond: +# (not for normal use) +# reverse_bytes = 1 +# reverse_bits = 1 +# ./jump.py | hexdump -C + +def reverse_Bits(n, no_of_bits): + result = 0 + for i in range(no_of_bits): + result <<= 1 + result |= n & 1 + n >>= 1 + return result + +def uint8(n): + if reverse_bits: + n = reverse_Bits(n, 8) + return struct.pack(">B", n) + +def uint16(n): + if reverse_bits: + n = reverse_Bits(n, 16) + if reverse_bytes: + return struct.pack("H", n) + +def uint24(n): + if reverse_bits: + n = reverse_Bits(n, 24) + if reverse_bytes: + return struct.pack("> 8 ) + else: + return struct.pack(">HB", n >> 8, n & 0xFF ) + +def uint32(n): + if reverse_bits: + n = reverse_Bits(n, 32) + if reverse_bytes: + return struct.pack("L", n) + +packet = b'' +# Frame (START) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) +# Preamble +packet += uint16(0xBDB3) # Preamble +# Frame (Control Register 0) commented out, diamond doesn't output this +# if uncommented, jump won't work: +#packet += uint8(0xC4) # Write control register 0 command +#packet += uint24(0) # 24-bit Command Information +#packet += uint32(0) # Control Register 0 data +# This is generated by diamond: +packet += uint32(0xFFFFFFFF) # I don't know what it does but it works +# Framme (Jump Command) +#packet += uint8(0xFE) # Jump command Wrong noted in TN1216 +packet += uint8(0x7E) # Jump command generated by diamond +packet += uint24(0) # 24-bit Command Information +packet += uint8(0x03) # SPI Flash Read opcode (0x03 = regular read, 0x0B = fast read) +packet += uint24(golden_image_address) # 24-bit SPI Flash Sector X address +# Frame (END) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) + +sys.stdout.write(packet) +# print([elem.encode("hex") for elem in packet]) diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k.bit b/boards/ulx3s-v1.7-45f/tinyfpga_45k.bit new file mode 120000 index 0000000..59e9556 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k.bit @@ -0,0 +1 @@ +project/project_project.bit \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf new file mode 120000 index 0000000..623c0d8 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme new file mode 120000 index 0000000..bc0382a --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf new file mode 120000 index 0000000..2c6afa4 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme new file mode 120000 index 0000000..9e1e580 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf b/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf new file mode 120000 index 0000000..bb7617d --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf @@ -0,0 +1 @@ +project/project_project_sram.svf \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme b/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme new file mode 120000 index 0000000..d098048 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme @@ -0,0 +1 @@ +project/project_project_sram.vme \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v b/boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v new file mode 100644 index 0000000..47812de --- /dev/null +++ b/boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v @@ -0,0 +1,108 @@ +module bootloader_ulx3s ( + input clk_25mhz, + + inout usb_fpga_dp, + inout usb_fpga_dn, + + output [7:0] led, + + input flash_miso, + output flash_mosi, + output flash_clk, + output flash_csn, + + input [6:0] btn, + output wifi_gpio0 +); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// generate 48 mhz clock + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + wire clk_200mhz; + clk_25M_200M clk_200M_inst ( + .CLKI(clk_25mhz), + .CLKOP(clk_200mhz) + ); + + wire clk_48mhz; + wire clk_ready; + clk_200M_48M clk_48M_inst ( + .CLKI(clk_200mhz), + .CLKOP(clk_48mhz), + .LOCK(clk_ready) + ); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// instantiate tinyfpga bootloader + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg reset = 1'b1; + wire usb_p_tx; + wire usb_n_tx; + wire usb_p_rx; + wire usb_n_rx; + wire usb_tx_en; + wire pin_led; + wire boot; + wire S_flash_clk; + wire S_flash_csn; + + tinyfpga_bootloader tinyfpga_bootloader_inst ( + .clk_48mhz(clk_48mhz), + .reset(reset), + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + .led(pin_led), + .spi_miso(flash_miso), + .spi_mosi(flash_mosi), + .spi_sck(S_flash_clk), + .spi_cs(S_flash_csn), + .boot(boot) + ); + + assign usb_fpga_dp = reset ? 1'b0 : (usb_tx_en ? usb_p_tx : 1'bz); + assign usb_fpga_dn = reset ? 1'b0 : (usb_tx_en ? usb_n_tx : 1'bz); + assign usb_p_rx = usb_tx_en ? 1'b1 : usb_fpga_dp; + assign usb_n_rx = usb_tx_en ? 1'b0 : usb_fpga_dn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Vendor-specific clock output to SPI config flash + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + USRMCLK usrmclk_inst ( + .USRMCLKI(S_flash_clk), + .USRMCLKTS(S_flash_csn) + ) /* synthesis syn_noprune=1 */; + assign flash_clk = S_flash_clk; + assign flash_csn = S_flash_csn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// ULX3S board buttons and LEDs + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + assign wifi_gpio0 = btn[0]; + assign led[5] = boot; + assign led[0] = pin_led; + + always @(posedge clk_48mhz) + begin + reset <= btn[1] | ~clk_ready; + end + +endmodule diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf new file mode 100644 index 0000000..8bde416 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P32 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x00080000 + 32 + 4194304 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf new file mode 100644 index 0000000..5ab9626 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x00100000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf new file mode 100644 index 0000000..f20aa77 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_32mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_32mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_32mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf new file mode 100644 index 0000000..8ccb7e7 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_spansion_64mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf new file mode 100644 index 0000000..b11ed78 --- /dev/null +++ b/boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf @@ -0,0 +1,48 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5UM + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + project/project_project.bit + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A + + From 934d3f1fdbec619add4adb0f77b2a569e048a170 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 10:08:17 +0200 Subject: [PATCH 06/90] initial WIP for future HID/vendorspecific transfer --- common/usb_hid_ctrl_ep.v | 476 +++++++++++++++++++++++++++++++++++++ common/usbasp_bootloader.v | 266 +++++++++++++++++++++ 2 files changed, 742 insertions(+) create mode 100644 common/usb_hid_ctrl_ep.v create mode 100644 common/usbasp_bootloader.v diff --git a/common/usb_hid_ctrl_ep.v b/common/usb_hid_ctrl_ep.v new file mode 100644 index 0000000..1551878 --- /dev/null +++ b/common/usb_hid_ctrl_ep.v @@ -0,0 +1,476 @@ +module usb_hid_ctrl_ep ( + input clk, + input reset, + output [6:0] dev_addr, + + output reg [7:0] debug_led, + + //////////////////// + // out endpoint interface + //////////////////// + output out_ep_req, + input out_ep_grant, + input out_ep_data_avail, + input out_ep_setup, + output out_ep_data_get, + input [7:0] out_ep_data, + output out_ep_stall, + input out_ep_acked, + + + //////////////////// + // in endpoint interface + //////////////////// + output in_ep_req, + input in_ep_grant, + input in_ep_data_free, + output in_ep_data_put, + output [7:0] in_ep_data, + output in_ep_data_done, + output reg in_ep_stall, + input in_ep_acked +); + + + localparam IDLE = 0; + localparam SETUP = 1; + localparam DATA_IN = 2; + localparam DATA_OUT = 3; + localparam STATUS_IN = 4; + localparam STATUS_OUT = 5; + + reg [5:0] ctrl_xfr_state = IDLE; + reg [5:0] ctrl_xfr_state_next; + + + + reg setup_stage_end = 0; + reg data_stage_end = 0; + reg status_stage_end = 0; + reg send_zero_length_data_pkt = 0; + + + + // the default control endpoint gets assigned the device address + reg [6:0] dev_addr_i = 0; + assign dev_addr = dev_addr_i; + + assign out_ep_req = out_ep_data_avail; + assign out_ep_data_get = out_ep_data_avail; + reg out_ep_data_valid = 0; + always @(posedge clk) out_ep_data_valid <= out_ep_data_avail && out_ep_grant; + + // need to record the setup data + reg [3:0] setup_data_addr = 0; + reg [9:0] raw_setup_data [7:0]; + + wire [7:0] bmRequestType = raw_setup_data[0]; + wire [7:0] bRequest = raw_setup_data[1]; + wire [15:0] wValue = {raw_setup_data[3][7:0], raw_setup_data[2][7:0]}; + wire [15:0] wIndex = {raw_setup_data[5][7:0], raw_setup_data[4][7:0]}; + wire [15:0] wLength = {raw_setup_data[7][7:0], raw_setup_data[6][7:0]}; + + // keep track of new out data start and end + wire pkt_start; + wire pkt_end; + + rising_edge_detector detect_pkt_start ( + .clk(clk), + .in(out_ep_data_avail), + .out(pkt_start) + ); + + falling_edge_detector detect_pkt_end ( + .clk(clk), + .in(out_ep_data_avail), + .out(pkt_end) + ); + + assign out_ep_stall = 1'b0; + + wire setup_pkt_start = pkt_start && out_ep_setup; + + wire has_data_stage = wLength != 16'b0000000000000000; + + wire out_data_stage; + assign out_data_stage = has_data_stage && !bmRequestType[7]; + + wire in_data_stage; + assign in_data_stage = has_data_stage && bmRequestType[7]; + + reg [7:0] bytes_sent = 0; + reg [6:0] rom_length = 0; + + wire all_data_sent = + (bytes_sent >= rom_length) || + (bytes_sent >= wLength); + + wire more_data_to_send = + !all_data_sent; + + wire in_data_transfer_done; + + rising_edge_detector detect_in_data_transfer_done ( + .clk(clk), + .in(all_data_sent), + .out(in_data_transfer_done) + ); + + assign in_ep_data_done = (in_data_transfer_done && ctrl_xfr_state == DATA_IN) || send_zero_length_data_pkt; + + assign in_ep_req = ctrl_xfr_state == DATA_IN && more_data_to_send; + assign in_ep_data_put = ctrl_xfr_state == DATA_IN && more_data_to_send && in_ep_data_free; + + + reg [6:0] rom_addr = 0; + + reg save_dev_addr = 0; + reg [6:0] new_dev_addr = 0; + + //////////////////////////////////////////////////////////////////////////////// + // control transfer state machine + //////////////////////////////////////////////////////////////////////////////// + + + always @* begin + setup_stage_end <= 0; + data_stage_end <= 0; + status_stage_end <= 0; + send_zero_length_data_pkt <= 0; + + case (ctrl_xfr_state) + IDLE : begin + if (setup_pkt_start) begin + ctrl_xfr_state_next <= SETUP; + end else begin + ctrl_xfr_state_next <= IDLE; + end + end + + SETUP : begin + if (pkt_end) begin + setup_stage_end <= 1; + + if (in_data_stage) begin + ctrl_xfr_state_next <= DATA_IN; + + end else if (out_data_stage) begin + ctrl_xfr_state_next <= DATA_OUT; + + end else begin + ctrl_xfr_state_next <= STATUS_IN; + send_zero_length_data_pkt <= 1; + end + + end else begin + ctrl_xfr_state_next <= SETUP; + end + end + + DATA_IN : begin + if (in_ep_stall) begin + ctrl_xfr_state_next <= IDLE; + data_stage_end <= 1; + status_stage_end <= 1; + + end else if (in_ep_acked && all_data_sent) begin + ctrl_xfr_state_next <= STATUS_OUT; + data_stage_end <= 1; + + end else begin + ctrl_xfr_state_next <= DATA_IN; + end + end + + DATA_OUT : begin + if (out_ep_acked) begin + ctrl_xfr_state_next <= STATUS_IN; + send_zero_length_data_pkt <= 1; + data_stage_end <= 1; + + end else begin + ctrl_xfr_state_next <= DATA_OUT; + end + end + + STATUS_IN : begin + if (in_ep_acked) begin + ctrl_xfr_state_next <= IDLE; + status_stage_end <= 1; + + end else begin + ctrl_xfr_state_next <= STATUS_IN; + end + end + + STATUS_OUT: begin + if (out_ep_acked) begin + ctrl_xfr_state_next <= IDLE; + status_stage_end <= 1; + + end else begin + ctrl_xfr_state_next <= STATUS_OUT; + end + end + + default begin + ctrl_xfr_state_next <= IDLE; + end + endcase + end + + always @(posedge clk) begin + if (reset) begin + ctrl_xfr_state <= IDLE; + end else begin + ctrl_xfr_state <= ctrl_xfr_state_next; + end + end + + always @(posedge clk) begin + in_ep_stall <= 0; + + if (out_ep_setup && out_ep_data_valid) begin + raw_setup_data[setup_data_addr] <= out_ep_data; + setup_data_addr <= setup_data_addr + 1; + end + + if (setup_stage_end) begin + case (bmRequestType[6:5]) // 2 bits describing request type + 0 : begin // 0: standard request + case (bRequest) + 'h06 : begin + // GET_DESCRIPTOR + case (wValue[15:8]) + 1 : begin + // DEVICE + rom_addr <= 0; + rom_length <= 18; + debug_led <= 8'b11000011; + end + + 2 : begin + // CONFIGURATION + rom_addr <= 18; + rom_length <= 67; + end + + 6 : begin + // DEVICE_QUALIFIER + in_ep_stall <= 1; + rom_addr <= 0; + rom_length <= 0; + end + + endcase + end + + 'h05 : begin + // SET_ADDRESS + rom_addr <= 0; + rom_length <= 0; + + // we need to save the address after the status stage ends + // this is because the status stage token will still be using + // the old device address + save_dev_addr <= 1; + new_dev_addr <= wValue[6:0]; + end + + 'h09 : begin + // SET_CONFIGURATION + rom_addr <= 0; + rom_length <= 0; + end + + 'h20 : begin + // SET_LINE_CODING + rom_addr <= 0; + rom_length <= 0; + end + + 'h21 : begin + // GET_LINE_CODING + rom_addr <= 85; + rom_length <= 7; + end + + 'h22 : begin + // SET_CONTROL_LINE_STATE + rom_addr <= 0; + rom_length <= 0; + end + + 'h23 : begin + // SEND_BREAK + rom_addr <= 0; + rom_length <= 0; + end + + default begin + rom_addr <= 0; + rom_length <= 0; + end + endcase + end // end 0: standard request + default begin // 2: vendor specific request (also would handle 1 or 3) + debug_led <= wValue[7:0]; + end // end 2: vendor specific request + endcase + end + + if (ctrl_xfr_state == DATA_IN && more_data_to_send && in_ep_grant && in_ep_data_free) begin + rom_addr <= rom_addr + 1; + bytes_sent <= bytes_sent + 1; + end + + if (status_stage_end) begin + setup_data_addr <= 0; + bytes_sent <= 0; + rom_addr <= 0; + rom_length <= 0; + + if (save_dev_addr) begin + save_dev_addr <= 0; + dev_addr_i <= new_dev_addr; + end + end + + if (reset) begin + bytes_sent <= 0; + rom_addr <= 0; + rom_length <= 0; + dev_addr_i <= 0; + setup_data_addr <= 0; + save_dev_addr <= 0; + end + end + + + `define CDC_ACM_ENDPOINT 2 + `define CDC_RX_ENDPOINT 1 + `define CDC_TX_ENDPOINT 1 + + + wire [7:0] descriptor_rom [0:91]; + assign in_ep_data = descriptor_rom[rom_addr]; + + assign descriptor_rom[0] = 18; // bLength + assign descriptor_rom[1] = 1; // bDescriptorType + assign descriptor_rom[2] = 'h00; // bcdUSB[0] + assign descriptor_rom[3] = 'h02; // bcdUSB[1] + assign descriptor_rom[4] = 'hFF; // bDeviceClass (Communications Device Class) + assign descriptor_rom[5] = 'h00; // bDeviceSubClass (Abstract Control Model) + assign descriptor_rom[6] = 'h00; // bDeviceProtocol (No class specific protocol required) + assign descriptor_rom[7] = 32; // bMaxPacketSize0 + + assign descriptor_rom[8] = 'hc0; // idVendor[0] VOTI + assign descriptor_rom[9] = 'h16; // idVendor[1] + assign descriptor_rom[10] = 'hdc; // idProduct[0] + assign descriptor_rom[11] = 'h05; // idProduct[1] + + assign descriptor_rom[12] = 0; // bcdDevice[0] + assign descriptor_rom[13] = 0; // bcdDevice[1] + assign descriptor_rom[14] = 0; // iManufacturer + assign descriptor_rom[15] = 0; // iProduct + assign descriptor_rom[16] = 0; // iSerialNumber + assign descriptor_rom[17] = 1; // bNumConfigurations + + // configuration descriptor + assign descriptor_rom[18] = 9; // bLength + assign descriptor_rom[19] = 2; // bDescriptorType + assign descriptor_rom[20] = (9+9+5+5+4+5+7+9+7+7); // wTotalLength[0] + assign descriptor_rom[21] = 0; // wTotalLength[1] + assign descriptor_rom[22] = 2; // bNumInterfaces + assign descriptor_rom[23] = 1; // bConfigurationValue + assign descriptor_rom[24] = 0; // iConfiguration + assign descriptor_rom[25] = 'hC0; // bmAttributes + assign descriptor_rom[26] = 60; // bMaxPower + + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + assign descriptor_rom[27] = 9; // bLength + assign descriptor_rom[28] = 4; // bDescriptorType + assign descriptor_rom[29] = 0; // bInterfaceNumber + assign descriptor_rom[30] = 0; // bAlternateSetting + assign descriptor_rom[31] = 1; // bNumEndpoints + assign descriptor_rom[32] = 2; // bInterfaceClass (Communications Device Class) + assign descriptor_rom[33] = 2; // bInterfaceSubClass (Abstract Control Model) + assign descriptor_rom[34] = 1; // bInterfaceProtocol (AT Commands: V.250 etc) + assign descriptor_rom[35] = 0; // iInterface + + // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26 + assign descriptor_rom[36] = 5; // bFunctionLength + assign descriptor_rom[37] = 'h24; // bDescriptorType + assign descriptor_rom[38] = 'h00; // bDescriptorSubtype + assign descriptor_rom[39] = 'h10; + assign descriptor_rom[40] = 'h01; // bcdCDC + + // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27 + assign descriptor_rom[41] = 5; // bFunctionLength + assign descriptor_rom[42] = 'h24; // bDescriptorType + assign descriptor_rom[43] = 'h01; // bDescriptorSubtype + assign descriptor_rom[44] = 'h00; // bmCapabilities + assign descriptor_rom[45] = 1; // bDataInterface + + // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28 + assign descriptor_rom[46] = 4; // bFunctionLength + assign descriptor_rom[47] = 'h24; // bDescriptorType + assign descriptor_rom[48] = 'h02; // bDescriptorSubtype + assign descriptor_rom[49] = 'h06; // bmCapabilities + + // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33 + assign descriptor_rom[50] = 5; // bFunctionLength + assign descriptor_rom[51] = 'h24; // bDescriptorType + assign descriptor_rom[52] = 'h06; // bDescriptorSubtype + assign descriptor_rom[53] = 0; // bMasterInterface + assign descriptor_rom[54] = 1; // bSlaveInterface0 + + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + assign descriptor_rom[55] = 7; // bLength + assign descriptor_rom[56] = 5; // bDescriptorType + assign descriptor_rom[57] = `CDC_ACM_ENDPOINT | 'h80; // bEndpointAddress + assign descriptor_rom[58] = 'h03; // bmAttributes (0x03=intr) + assign descriptor_rom[59] = 8; // wMaxPacketSize[0] + assign descriptor_rom[60] = 0; // wMaxPacketSize[1] + assign descriptor_rom[61] = 64; // bInterval + + // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 + assign descriptor_rom[62] = 9; // bLength + assign descriptor_rom[63] = 4; // bDescriptorType + assign descriptor_rom[64] = 1; // bInterfaceNumber + assign descriptor_rom[65] = 0; // bAlternateSetting + assign descriptor_rom[66] = 2; // bNumEndpoints + assign descriptor_rom[67] = 'h0A; // bInterfaceClass + assign descriptor_rom[68] = 'h00; // bInterfaceSubClass + assign descriptor_rom[69] = 'h00; // bInterfaceProtocol + assign descriptor_rom[70] = 0; // iInterface + + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + assign descriptor_rom[71] = 7; // bLength + assign descriptor_rom[72] = 5; // bDescriptorType + assign descriptor_rom[73] = `CDC_RX_ENDPOINT; // bEndpointAddress + assign descriptor_rom[74] = 'h02; // bmAttributes (0x02=bulk) + assign descriptor_rom[75] = 32; // wMaxPacketSize[0] + assign descriptor_rom[76] = 0; // wMaxPacketSize[1] + assign descriptor_rom[77] = 0; // bInterval + + // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 + assign descriptor_rom[78] = 7; // bLength + assign descriptor_rom[79] = 5; // bDescriptorType + assign descriptor_rom[80] = `CDC_TX_ENDPOINT | 'h80; // bEndpointAddress + assign descriptor_rom[81] = 'h02; // bmAttributes (0x02=bulk) + + assign descriptor_rom[82] = 32; // wMaxPacketSize[0] + assign descriptor_rom[83] = 0; // wMaxPacketSize[1] + assign descriptor_rom[84] = 0; // bInterval + + // LINE_CODING + assign descriptor_rom[85] = 'h80; // dwDTERate[0] + assign descriptor_rom[86] = 'h25; // dwDTERate[1] + assign descriptor_rom[87] = 'h00; // dwDTERate[2] + assign descriptor_rom[88] = 'h00; // dwDTERate[3] + assign descriptor_rom[89] = 1; // bCharFormat (1 stop bit) + assign descriptor_rom[90] = 0; // bParityType (None) + assign descriptor_rom[91] = 8; // bDataBits (8 bits) + +endmodule diff --git a/common/usbasp_bootloader.v b/common/usbasp_bootloader.v new file mode 100644 index 0000000..1f28dfd --- /dev/null +++ b/common/usbasp_bootloader.v @@ -0,0 +1,266 @@ +module usbasp_bootloader ( + input clk_48mhz, + input reset, + + // USB lines. Split into input vs. output and oe control signal to maintain + // highest level of compatibility with synthesis tools. + output usb_p_tx, + output usb_n_tx, + + input usb_p_rx, + input usb_n_rx, + + output usb_tx_en, + + // bootloader indicator light, pulses on and off when bootloader is active + output led, + output [7:0] debug_led, + + // connection to SPI flash + output spi_cs, + output spi_sck, + output spi_mosi, + input spi_miso, + + // when asserted it indicates the bootloader is ready for the FPGA to load + // the user config. different FPGAs use different primitives for this + // function. + output boot +); + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// bootloader LED + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg [7:0] led_pwm = 0; + reg [7:0] pwm_cnt = 0; + + reg [5:0] ns_cnt = 0; + wire ns_rst = (ns_cnt == 48); + always @(posedge clk_48mhz) begin + if (ns_rst) begin + ns_cnt <= 0; + end else begin + ns_cnt <= ns_cnt + 1'b1; + end + end + + reg [9:0] us_cnt = 0; + wire us_rst = (us_cnt == 1000); + always @(posedge clk_48mhz) begin + if (us_rst) begin + us_cnt <= 0; + end else if (ns_rst) begin + us_cnt <= us_cnt + 1'b1; + end + end + + reg count_down = 0; + always @(posedge clk_48mhz) begin + if (us_rst) begin + if (count_down) begin + if (led_pwm == 0) begin + count_down <= 0; + end else begin + led_pwm <= led_pwm - 1'b1; + end + end else begin + if (led_pwm == 255) begin + count_down <= 1; + end else begin + led_pwm <= led_pwm + 1'b1; + end + end + end + end + always @(posedge clk_48mhz) + if (reset) + pwm_cnt <= 0; + else + pwm_cnt <= pwm_cnt + 1'b1; + assign led = led_pwm > pwm_cnt; + + + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// usb engine + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + + wire [6:0] dev_addr; + wire [7:0] out_ep_data; + + wire ctrl_out_ep_req; + wire ctrl_out_ep_grant; + wire ctrl_out_ep_data_avail; + wire ctrl_out_ep_setup; + wire ctrl_out_ep_data_get; + wire ctrl_out_ep_stall; + wire ctrl_out_ep_acked; + + wire ctrl_in_ep_req; + wire ctrl_in_ep_grant; + wire ctrl_in_ep_data_free; + wire ctrl_in_ep_data_put; + wire [7:0] ctrl_in_ep_data; + wire ctrl_in_ep_data_done; + wire ctrl_in_ep_stall; + wire ctrl_in_ep_acked; + + + wire serial_out_ep_req; + wire serial_out_ep_grant; + wire serial_out_ep_data_avail; + wire serial_out_ep_setup; + wire serial_out_ep_data_get; + wire serial_out_ep_stall; + wire serial_out_ep_acked; + + wire serial_in_ep_req; + wire serial_in_ep_grant; + wire serial_in_ep_data_free; + wire serial_in_ep_data_put; + wire [7:0] serial_in_ep_data; + wire serial_in_ep_data_done; + wire serial_in_ep_stall; + wire serial_in_ep_acked; + + wire sof_valid; + wire [10:0] frame_index; + + reg [25:0] host_presence_timer = 0; + wire host_presence_timeout; + + wire boot_to_user_design; + + assign boot = host_presence_timeout || boot_to_user_design; + usb_hid_ctrl_ep ctrl_ep_inst ( + .clk(clk_48mhz), + .reset(reset), + .dev_addr(dev_addr), + + // debug led + .debug_led(debug_led), + + // out endpoint interface + .out_ep_req(ctrl_out_ep_req), + .out_ep_grant(ctrl_out_ep_grant), + .out_ep_data_avail(ctrl_out_ep_data_avail), + .out_ep_setup(ctrl_out_ep_setup), + .out_ep_data_get(ctrl_out_ep_data_get), + .out_ep_data(out_ep_data), + .out_ep_stall(ctrl_out_ep_stall), + .out_ep_acked(ctrl_out_ep_acked), + + // in endpoint interface + .in_ep_req(ctrl_in_ep_req), + .in_ep_grant(ctrl_in_ep_grant), + .in_ep_data_free(ctrl_in_ep_data_free), + .in_ep_data_put(ctrl_in_ep_data_put), + .in_ep_data(ctrl_in_ep_data), + .in_ep_data_done(ctrl_in_ep_data_done), + .in_ep_stall(ctrl_in_ep_stall), + .in_ep_acked(ctrl_in_ep_acked) + ); + + usb_spi_bridge_ep usb_spi_bridge_ep_inst ( + .clk(clk_48mhz), + .reset(reset), + + // out endpoint interface + .out_ep_req(serial_out_ep_req), + .out_ep_grant(serial_out_ep_grant), + .out_ep_data_avail(serial_out_ep_data_avail), + .out_ep_setup(serial_out_ep_setup), + .out_ep_data_get(serial_out_ep_data_get), + .out_ep_data(out_ep_data), + .out_ep_stall(serial_out_ep_stall), + .out_ep_acked(serial_out_ep_acked), + + // in endpoint interface + .in_ep_req(serial_in_ep_req), + .in_ep_grant(serial_in_ep_grant), + .in_ep_data_free(serial_in_ep_data_free), + .in_ep_data_put(serial_in_ep_data_put), + .in_ep_data(serial_in_ep_data), + .in_ep_data_done(serial_in_ep_data_done), + .in_ep_stall(serial_in_ep_stall), + .in_ep_acked(serial_in_ep_acked), + + // spi interface + .spi_cs_b(spi_cs), + .spi_sck(spi_sck), + .spi_mosi(spi_mosi), + .spi_miso(spi_miso), + + // warm boot interface + .boot_to_user_design(boot_to_user_design) + ); + + wire nak_in_ep_grant; + wire nak_in_ep_data_free; + wire nak_in_ep_acked; + + usb_fs_pe #( + .NUM_OUT_EPS(5'd2), + .NUM_IN_EPS(5'd3) + ) usb_fs_pe_inst ( + .clk(clk_48mhz), + .reset(reset), + + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + + .dev_addr(dev_addr), + + // out endpoint interfaces + .out_ep_req({serial_out_ep_req, ctrl_out_ep_req}), + .out_ep_grant({serial_out_ep_grant, ctrl_out_ep_grant}), + .out_ep_data_avail({serial_out_ep_data_avail, ctrl_out_ep_data_avail}), + .out_ep_setup({serial_out_ep_setup, ctrl_out_ep_setup}), + .out_ep_data_get({serial_out_ep_data_get, ctrl_out_ep_data_get}), + .out_ep_data(out_ep_data), + .out_ep_stall({serial_out_ep_stall, ctrl_out_ep_stall}), + .out_ep_acked({serial_out_ep_acked, ctrl_out_ep_acked}), + + // in endpoint interfaces + .in_ep_req({1'b0, serial_in_ep_req, ctrl_in_ep_req}), + .in_ep_grant({nak_in_ep_grant, serial_in_ep_grant, ctrl_in_ep_grant}), + .in_ep_data_free({nak_in_ep_data_free, serial_in_ep_data_free, ctrl_in_ep_data_free}), + .in_ep_data_put({1'b0, serial_in_ep_data_put, ctrl_in_ep_data_put}), + .in_ep_data({8'b0, serial_in_ep_data[7:0], ctrl_in_ep_data[7:0]}), + .in_ep_data_done({1'b0, serial_in_ep_data_done, ctrl_in_ep_data_done}), + .in_ep_stall({1'b0, serial_in_ep_stall, ctrl_in_ep_stall}), + .in_ep_acked({nak_in_ep_acked, serial_in_ep_acked, ctrl_in_ep_acked}), + + // sof interface + .sof_valid(sof_valid), + .frame_index(frame_index) + ); + + + + //////////////////////////////////////////////////////////////////////////////// + // host presence detection + //////////////////////////////////////////////////////////////////////////////// + + always @(posedge clk_48mhz) begin + if (sof_valid) begin + host_presence_timer <= 0; + end else begin + if (host_presence_timer[25] == 1'b0) begin + host_presence_timer <= host_presence_timer + 1; + end + end + end + assign host_presence_timeout = host_presence_timer[25]; + +endmodule \ No newline at end of file From fcaadee27e8c4bb9efb34187354884016d211c4e Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 10:08:49 +0200 Subject: [PATCH 07/90] ulx3s board support for future HID --- boards/ulx3s-v1.7-45f-hid/Makefile | 127 +++++ boards/ulx3s-v1.7-45f-hid/bootloader.ldf | 62 +++ .../ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v | 75 +++ .../ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v | 75 +++ .../constraints/ulx3s_v17patch.lpf | 435 ++++++++++++++++++ .../initialize/boardmeta4MB.bin | 119 +++++ .../initialize/boardmeta8MB.bin | 58 +++ .../initialize/initialize4MB.sh | 30 ++ .../initialize/initialize8MB.sh | 31 ++ boards/ulx3s-v1.7-45f-hid/initialize/jump.bin | Bin 0 -> 50 bytes boards/ulx3s-v1.7-45f-hid/initialize/jump.py | 95 ++++ boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit | 1 + ...fpga_45k_multiboot_flash_micron_32mbit.svf | 1 + ...fpga_45k_multiboot_flash_micron_32mbit.vme | 1 + ...ga_45k_multiboot_flash_spansion_64mbit.svf | 1 + ...ga_45k_multiboot_flash_spansion_64mbit.vme | 1 + .../ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf | 1 + .../ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme | 1 + .../top/bootloader_hid_ulx3s.v | 110 +++++ .../ulx3s_45f_flash_micron_32mbit.xcf | 104 +++++ .../ulx3s_45f_flash_spansion_64mbit.xcf | 104 +++++ .../ulx3s_45f_multiboot_micron_32mbit.xcf | 104 +++++ .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 104 +++++ boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf | 48 ++ 24 files changed, 1688 insertions(+) create mode 100644 boards/ulx3s-v1.7-45f-hid/Makefile create mode 100644 boards/ulx3s-v1.7-45f-hid/bootloader.ldf create mode 100644 boards/ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v create mode 100644 boards/ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v create mode 100644 boards/ulx3s-v1.7-45f-hid/constraints/ulx3s_v17patch.lpf create mode 100644 boards/ulx3s-v1.7-45f-hid/initialize/boardmeta4MB.bin create mode 100644 boards/ulx3s-v1.7-45f-hid/initialize/boardmeta8MB.bin create mode 100755 boards/ulx3s-v1.7-45f-hid/initialize/initialize4MB.sh create mode 100755 boards/ulx3s-v1.7-45f-hid/initialize/initialize8MB.sh create mode 100644 boards/ulx3s-v1.7-45f-hid/initialize/jump.bin create mode 100755 boards/ulx3s-v1.7-45f-hid/initialize/jump.py create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.svf create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.vme create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf create mode 120000 boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme create mode 100644 boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v create mode 100644 boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_micron_32mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_micron_32mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf diff --git a/boards/ulx3s-v1.7-45f-hid/Makefile b/boards/ulx3s-v1.7-45f-hid/Makefile new file mode 100644 index 0000000..7990438 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/Makefile @@ -0,0 +1,127 @@ + +PROJ_FILE := $(shell ls *.ldf | head -1) +PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) +IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) +IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) + +DIAMOND_BASE := /usr/local/diamond +DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) +DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) +DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) + +OPENOCD_BASE := ../../programmer/openocd/ulx3s/ + +# name of the project as defined in project file +PROJECT = project + +# FPGA flashing device for programming +FPGA_DEVICE = LFE5U-45F + +JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml +JUNK += dummy_sym.sort project_tcl.html promote.xml +JUNK += generate_core.tcl generate_ngd.tcl msg_file.log +JUNK += project_tcr.dir + +all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf + +$(PROJECT)/$(PROJECT)_$(PROJECT).bit: + echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} + +# same file with different name required for multiboot to work +$(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + cp $< $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_sram.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_sram.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT).mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_flash_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 32 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_micron_32mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + dd if=/dev/zero of=/tmp/zero.bit bs=1k count=300 + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 64 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_spansion_64mbit.xcf -of $@ + +program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + echo pgr_project open ulx3s_45f_sram.xcf \; pgr_program run | ${DIAMONDC} + +program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-45f.ocd + +program_web: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + svfupload.py ulx3s.lan $< + +program_web_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf + svfupload.py ulx3s.lan $< + +program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-45f.ocd + +program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + +program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme + FleaFPGA-JTAG $< + +program_flea_flash_spansion: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme + FleaFPGA-JTAG $< + +#$(PROJECT)/$(PROJECT)_$(PROJECT).jed: +# echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -fullvme -if sparrowhawk_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ + +flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme + ${PROGRAMMERC} $< + # after this, to gain access to serial port on linux + # rmmod ftdi_sio; modprobe ftdi_sio + +# example another project +#%.svf : %.jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ +# mv -f $@ $@.flash +# ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ +# mv -f $@ $@.sram +# ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ + +clean: + rm -rf $(JUNK) *~ diff --git a/boards/ulx3s-v1.7-45f-hid/bootloader.ldf b/boards/ulx3s-v1.7-45f-hid/bootloader.ldf new file mode 100644 index 0000000..99007f6 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/bootloader.ldf @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v b/boards/ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v new file mode 100644 index 0000000..2e9bb80 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_200M_48M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 200.00 -fclkop 48.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_200M_48M/clk_200M_48M.fdc */ +/* Wed Jul 11 00:10:22 2018 */ + + +`timescale 1 ns / 1 ps +module clk_200M_48M (CLKI, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire LOCK; + + wire REFCLK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 11 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 12 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 25 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="48.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="200.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 200.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v b/boards/ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v new file mode 100644 index 0000000..0ce5c18 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_200M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 200.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_25M_200M/clk_25M_200M.fdc */ +/* Wed Jul 11 00:09:44 2018 */ + + +`timescale 1 ns / 1 ps +module clk_25M_200M (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire REFCLK; + wire LOCK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 2 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 3 ; + defparam PLLInst_0.CLKFB_DIV = 8 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="200.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="25.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 200.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v1.7-45f-hid/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v1.7-45f-hid/constraints/ulx3s_v17patch.lpf new file mode 100644 index 0000000..8e0d34c --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/constraints/ulx3s_v17patch.lpf @@ -0,0 +1,435 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v1.7 patched towards v1.8 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "W1"; # UP +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "Y2"; # RIGHT +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "J1"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J3"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "K2"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "K1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "H2"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "H1"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; +LOCATE COMP "wifi_gpio17" SITE "N3"; +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Read + +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_clkp" SITE "A17"; # Clock + +LOCATE COMP "gpdi_clkn" SITE "B18"; # Clock - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "C12"; # I2C shared with RTC +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "D15"; # J2_25+ GP22 +LOCATE COMP "gn[22]" SITE "E15"; # J2_25- GN22 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "B15"; # J2_31+ GP25 +LOCATE COMP "gn[25]" SITE "C15"; # J2_31- GN25 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta4MB.bin b/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta4MB.bin new file mode 100644 index 0000000..7a525c7 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta4MB.bin @@ -0,0 +1,119 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x2FFFFF", + "userdata": "0x300000-0x3FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta8MB.bin b/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta8MB.bin new file mode 100644 index 0000000..89be03c --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta8MB.bin @@ -0,0 +1,58 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x3FFFFF", + "userdata": "0x500000-0x7FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/initialize4MB.sh b/boards/ulx3s-v1.7-45f-hid/initialize/initialize4MB.sh new file mode 100755 index 0000000..3d67d93 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/initialize/initialize4MB.sh @@ -0,0 +1,30 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x3FF000) # flash size - 0x1000 +jump_command_address=$(printf "%d" 0x3FFF00) # flash size - 0x100 + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta4MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/initialize8MB.sh b/boards/ulx3s-v1.7-45f-hid/initialize/initialize8MB.sh new file mode 100755 index 0000000..b127f53 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/initialize/initialize8MB.sh @@ -0,0 +1,31 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 8 Mbit = 1 MB = 0x100000 +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x7FF000) # flash size - 0x1000 (-4KB) +jump_command_address=$(printf "%d" 0x7FFF00) # flash size - 0x100 (-256) + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta8MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/jump.bin b/boards/ulx3s-v1.7-45f-hid/initialize/jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..d39691f0cc8e593945579b840fe60410bede6a07 GIT binary patch literal 50 bcmezWA06!73=*khU|?VtU|>L({r?{TKoKe0 literal 0 HcmV?d00001 diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/jump.py b/boards/ulx3s-v1.7-45f-hid/initialize/jump.py new file mode 100755 index 0000000..b1ff948 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/initialize/jump.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# Lattice ECP5 jump command generator +# TN1216 p.23 describes the jump command syntax which does not work. +# The syntax has been fixed by looking at dual boot intel hex file +# generated by diamond, this actually works. + +import struct +import sys + +# write output of this funtion at FLASH address: +# jump_command_address = 0x3FFF00 = 4194048 + +# write "golden" bitstream at FLASH address: +golden_image_address = 0x140000 +golden_image_address = int(sys.argv[1]) + +# normally both 0 +reverse_bytes = 0 +reverse_bits = 0 + +# to compare with intel HEX file generated by diamond: +# (not for normal use) +# reverse_bytes = 1 +# reverse_bits = 1 +# ./jump.py | hexdump -C + +def reverse_Bits(n, no_of_bits): + result = 0 + for i in range(no_of_bits): + result <<= 1 + result |= n & 1 + n >>= 1 + return result + +def uint8(n): + if reverse_bits: + n = reverse_Bits(n, 8) + return struct.pack(">B", n) + +def uint16(n): + if reverse_bits: + n = reverse_Bits(n, 16) + if reverse_bytes: + return struct.pack("H", n) + +def uint24(n): + if reverse_bits: + n = reverse_Bits(n, 24) + if reverse_bytes: + return struct.pack("> 8 ) + else: + return struct.pack(">HB", n >> 8, n & 0xFF ) + +def uint32(n): + if reverse_bits: + n = reverse_Bits(n, 32) + if reverse_bytes: + return struct.pack("L", n) + +packet = b'' +# Frame (START) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) +# Preamble +packet += uint16(0xBDB3) # Preamble +# Frame (Control Register 0) commented out, diamond doesn't output this +# if uncommented, jump won't work: +#packet += uint8(0xC4) # Write control register 0 command +#packet += uint24(0) # 24-bit Command Information +#packet += uint32(0) # Control Register 0 data +# This is generated by diamond: +packet += uint32(0xFFFFFFFF) # I don't know what it does but it works +# Framme (Jump Command) +#packet += uint8(0xFE) # Jump command Wrong noted in TN1216 +packet += uint8(0x7E) # Jump command generated by diamond +packet += uint24(0) # 24-bit Command Information +packet += uint8(0x03) # SPI Flash Read opcode (0x03 = regular read, 0x0B = fast read) +packet += uint24(golden_image_address) # 24-bit SPI Flash Sector X address +# Frame (END) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) + +sys.stdout.write(packet) +# print([elem.encode("hex") for elem in packet]) diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit new file mode 120000 index 0000000..59e9556 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit @@ -0,0 +1 @@ +project/project_project.bit \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.svf new file mode 120000 index 0000000..623c0d8 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.vme new file mode 120000 index 0000000..bc0382a --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf new file mode 120000 index 0000000..2c6afa4 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme new file mode 120000 index 0000000..9e1e580 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf new file mode 120000 index 0000000..bb7617d --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf @@ -0,0 +1 @@ +project/project_project_sram.svf \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme new file mode 120000 index 0000000..d098048 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme @@ -0,0 +1 @@ +project/project_project_sram.vme \ No newline at end of file diff --git a/boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v b/boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v new file mode 100644 index 0000000..dd86b6a --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v @@ -0,0 +1,110 @@ +module bootloader_hid_ulx3s ( + input clk_25mhz, + + inout usb_fpga_dp, + inout usb_fpga_dn, + + output [7:0] led, + + input flash_miso, + output flash_mosi, + output flash_clk, + output flash_csn, + + input [6:0] btn, + output wifi_gpio0 +); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// generate 48 mhz clock + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + wire clk_200mhz; + clk_25M_200M clk_200M_inst ( + .CLKI(clk_25mhz), + .CLKOP(clk_200mhz) + ); + + wire clk_48mhz; + wire clk_ready; + clk_200M_48M clk_48M_inst ( + .CLKI(clk_200mhz), + .CLKOP(clk_48mhz), + .LOCK(clk_ready) + ); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// instantiate tinyfpga bootloader + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg reset = 1'b1; + wire usb_p_tx; + wire usb_n_tx; + wire usb_p_rx; + wire usb_n_rx; + wire usb_tx_en; + wire pin_led; + wire [7:0] debug_led; + wire boot; + wire S_flash_clk; + wire S_flash_csn; + + usbasp_bootloader usbasp_bootloader_inst ( + .clk_48mhz(clk_48mhz), + .reset(reset), + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + .led(pin_led), + .debug_led(debug_led), + .spi_miso(flash_miso), + .spi_mosi(flash_mosi), + .spi_sck(S_flash_clk), + .spi_cs(S_flash_csn), + .boot(boot) + ); + + assign usb_fpga_dp = reset ? 1'b0 : (usb_tx_en ? usb_p_tx : 1'bz); + assign usb_fpga_dn = reset ? 1'b0 : (usb_tx_en ? usb_n_tx : 1'bz); + assign usb_p_rx = usb_tx_en ? 1'b1 : usb_fpga_dp; + assign usb_n_rx = usb_tx_en ? 1'b0 : usb_fpga_dn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Vendor-specific clock output to SPI config flash + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + USRMCLK usrmclk_inst ( + .USRMCLKI(S_flash_clk), + .USRMCLKTS(S_flash_csn) + ) /* synthesis syn_noprune=1 */; + assign flash_clk = S_flash_clk; + assign flash_csn = S_flash_csn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// ULX3S board buttons and LEDs + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + assign wifi_gpio0 = btn[0]; + //assign led[5] = boot; + assign led = debug_led; + + always @(posedge clk_48mhz) + begin + reset <= btn[1] | ~clk_ready; + end + +endmodule diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_micron_32mbit.xcf new file mode 100644 index 0000000..8bde416 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P32 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x00080000 + 32 + 4194304 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_spansion_64mbit.xcf new file mode 100644 index 0000000..5ab9626 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x00100000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_micron_32mbit.xcf new file mode 100644 index 0000000..f20aa77 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_32mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_32mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_32mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_spansion_64mbit.xcf new file mode 100644 index 0000000..8ccb7e7 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_spansion_64mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf new file mode 100644 index 0000000..b11ed78 --- /dev/null +++ b/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf @@ -0,0 +1,48 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5UM + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + project/project_project.bit + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A + + From 35533d39be64d7c0213a9cada273e14b15c8d452 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 11:16:21 +0200 Subject: [PATCH 08/90] DATA_OUT accepted and shown on debug LED --- common/usb_hid_ctrl_ep.v | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/common/usb_hid_ctrl_ep.v b/common/usb_hid_ctrl_ep.v index 1551878..b0860ec 100644 --- a/common/usb_hid_ctrl_ep.v +++ b/common/usb_hid_ctrl_ep.v @@ -124,6 +124,9 @@ module usb_hid_ctrl_ep ( reg [6:0] rom_addr = 0; + reg [3:0] out_addr = 0; + reg [7:0] out_buf [0:15]; // PC out transfer should be received here + reg save_dev_addr = 0; reg [6:0] new_dev_addr = 0; @@ -183,11 +186,12 @@ module usb_hid_ctrl_ep ( end DATA_OUT : begin - if (out_ep_acked) begin + // if (out_ep_acked) begin + if (pkt_end) begin ctrl_xfr_state_next <= STATUS_IN; send_zero_length_data_pkt <= 1; data_stage_end <= 1; - + end else begin ctrl_xfr_state_next <= DATA_OUT; end @@ -246,7 +250,6 @@ module usb_hid_ctrl_ep ( // DEVICE rom_addr <= 0; rom_length <= 18; - debug_led <= 8'b11000011; end 2 : begin @@ -315,6 +318,7 @@ module usb_hid_ctrl_ep ( end // end 0: standard request default begin // 2: vendor specific request (also would handle 1 or 3) debug_led <= wValue[7:0]; + out_addr <= 0; end // end 2: vendor specific request endcase end @@ -324,6 +328,13 @@ module usb_hid_ctrl_ep ( bytes_sent <= bytes_sent + 1; end + if (ctrl_xfr_state == DATA_OUT && out_ep_data_valid && ~out_ep_setup) begin + if (out_addr == 0) begin + debug_led <= out_ep_data; + end + out_addr <= out_addr + 1; + end + if (status_stage_end) begin setup_data_addr <= 0; bytes_sent <= 0; From 75bc3c3b01b49dad6acb2fd1350a3af0c984e9b4 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 11:57:16 +0200 Subject: [PATCH 09/90] simplified vendor-specific descriptor --- common/usb_hid_ctrl_ep.v | 103 ++++++--------------------------------- 1 file changed, 14 insertions(+), 89 deletions(-) diff --git a/common/usb_hid_ctrl_ep.v b/common/usb_hid_ctrl_ep.v index b0860ec..cda1b22 100644 --- a/common/usb_hid_ctrl_ep.v +++ b/common/usb_hid_ctrl_ep.v @@ -255,16 +255,16 @@ module usb_hid_ctrl_ep ( 2 : begin // CONFIGURATION rom_addr <= 18; - rom_length <= 67; + rom_length <= 18; end - + 6 : begin // DEVICE_QUALIFIER in_ep_stall <= 1; rom_addr <= 0; rom_length <= 0; end - + endcase end @@ -317,7 +317,7 @@ module usb_hid_ctrl_ep ( endcase end // end 0: standard request default begin // 2: vendor specific request (also would handle 1 or 3) - debug_led <= wValue[7:0]; + // debug_led <= wValue[7:0]; out_addr <= 0; end // end 2: vendor specific request endcase @@ -363,7 +363,7 @@ module usb_hid_ctrl_ep ( `define CDC_TX_ENDPOINT 1 - wire [7:0] descriptor_rom [0:91]; + wire [7:0] descriptor_rom [0:35]; assign in_ep_data = descriptor_rom[rom_addr]; assign descriptor_rom[0] = 18; // bLength @@ -380,8 +380,8 @@ module usb_hid_ctrl_ep ( assign descriptor_rom[10] = 'hdc; // idProduct[0] assign descriptor_rom[11] = 'h05; // idProduct[1] - assign descriptor_rom[12] = 0; // bcdDevice[0] - assign descriptor_rom[13] = 0; // bcdDevice[1] + assign descriptor_rom[12] = 0; // bcdDevice[0] version minor + assign descriptor_rom[13] = 0; // bcdDevice[1] version major assign descriptor_rom[14] = 0; // iManufacturer assign descriptor_rom[15] = 0; // iProduct assign descriptor_rom[16] = 0; // iSerialNumber @@ -390,98 +390,23 @@ module usb_hid_ctrl_ep ( // configuration descriptor assign descriptor_rom[18] = 9; // bLength assign descriptor_rom[19] = 2; // bDescriptorType - assign descriptor_rom[20] = (9+9+5+5+4+5+7+9+7+7); // wTotalLength[0] + assign descriptor_rom[20] = 18; // wTotalLength[0] assign descriptor_rom[21] = 0; // wTotalLength[1] - assign descriptor_rom[22] = 2; // bNumInterfaces + assign descriptor_rom[22] = 1; // bNumInterfaces (must have at least 1 interface) assign descriptor_rom[23] = 1; // bConfigurationValue assign descriptor_rom[24] = 0; // iConfiguration assign descriptor_rom[25] = 'hC0; // bmAttributes - assign descriptor_rom[26] = 60; // bMaxPower + assign descriptor_rom[26] = 250; // bMaxPower // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 assign descriptor_rom[27] = 9; // bLength assign descriptor_rom[28] = 4; // bDescriptorType assign descriptor_rom[29] = 0; // bInterfaceNumber assign descriptor_rom[30] = 0; // bAlternateSetting - assign descriptor_rom[31] = 1; // bNumEndpoints - assign descriptor_rom[32] = 2; // bInterfaceClass (Communications Device Class) - assign descriptor_rom[33] = 2; // bInterfaceSubClass (Abstract Control Model) - assign descriptor_rom[34] = 1; // bInterfaceProtocol (AT Commands: V.250 etc) + assign descriptor_rom[31] = 0; // bNumEndpoints + assign descriptor_rom[32] = 0; // bInterfaceClass + assign descriptor_rom[33] = 0; // bInterfaceSubClass + assign descriptor_rom[34] = 0; // bInterfaceProtocol assign descriptor_rom[35] = 0; // iInterface - // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26 - assign descriptor_rom[36] = 5; // bFunctionLength - assign descriptor_rom[37] = 'h24; // bDescriptorType - assign descriptor_rom[38] = 'h00; // bDescriptorSubtype - assign descriptor_rom[39] = 'h10; - assign descriptor_rom[40] = 'h01; // bcdCDC - - // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27 - assign descriptor_rom[41] = 5; // bFunctionLength - assign descriptor_rom[42] = 'h24; // bDescriptorType - assign descriptor_rom[43] = 'h01; // bDescriptorSubtype - assign descriptor_rom[44] = 'h00; // bmCapabilities - assign descriptor_rom[45] = 1; // bDataInterface - - // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28 - assign descriptor_rom[46] = 4; // bFunctionLength - assign descriptor_rom[47] = 'h24; // bDescriptorType - assign descriptor_rom[48] = 'h02; // bDescriptorSubtype - assign descriptor_rom[49] = 'h06; // bmCapabilities - - // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33 - assign descriptor_rom[50] = 5; // bFunctionLength - assign descriptor_rom[51] = 'h24; // bDescriptorType - assign descriptor_rom[52] = 'h06; // bDescriptorSubtype - assign descriptor_rom[53] = 0; // bMasterInterface - assign descriptor_rom[54] = 1; // bSlaveInterface0 - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - assign descriptor_rom[55] = 7; // bLength - assign descriptor_rom[56] = 5; // bDescriptorType - assign descriptor_rom[57] = `CDC_ACM_ENDPOINT | 'h80; // bEndpointAddress - assign descriptor_rom[58] = 'h03; // bmAttributes (0x03=intr) - assign descriptor_rom[59] = 8; // wMaxPacketSize[0] - assign descriptor_rom[60] = 0; // wMaxPacketSize[1] - assign descriptor_rom[61] = 64; // bInterval - - // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12 - assign descriptor_rom[62] = 9; // bLength - assign descriptor_rom[63] = 4; // bDescriptorType - assign descriptor_rom[64] = 1; // bInterfaceNumber - assign descriptor_rom[65] = 0; // bAlternateSetting - assign descriptor_rom[66] = 2; // bNumEndpoints - assign descriptor_rom[67] = 'h0A; // bInterfaceClass - assign descriptor_rom[68] = 'h00; // bInterfaceSubClass - assign descriptor_rom[69] = 'h00; // bInterfaceProtocol - assign descriptor_rom[70] = 0; // iInterface - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - assign descriptor_rom[71] = 7; // bLength - assign descriptor_rom[72] = 5; // bDescriptorType - assign descriptor_rom[73] = `CDC_RX_ENDPOINT; // bEndpointAddress - assign descriptor_rom[74] = 'h02; // bmAttributes (0x02=bulk) - assign descriptor_rom[75] = 32; // wMaxPacketSize[0] - assign descriptor_rom[76] = 0; // wMaxPacketSize[1] - assign descriptor_rom[77] = 0; // bInterval - - // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13 - assign descriptor_rom[78] = 7; // bLength - assign descriptor_rom[79] = 5; // bDescriptorType - assign descriptor_rom[80] = `CDC_TX_ENDPOINT | 'h80; // bEndpointAddress - assign descriptor_rom[81] = 'h02; // bmAttributes (0x02=bulk) - - assign descriptor_rom[82] = 32; // wMaxPacketSize[0] - assign descriptor_rom[83] = 0; // wMaxPacketSize[1] - assign descriptor_rom[84] = 0; // bInterval - - // LINE_CODING - assign descriptor_rom[85] = 'h80; // dwDTERate[0] - assign descriptor_rom[86] = 'h25; // dwDTERate[1] - assign descriptor_rom[87] = 'h00; // dwDTERate[2] - assign descriptor_rom[88] = 'h00; // dwDTERate[3] - assign descriptor_rom[89] = 1; // bCharFormat (1 stop bit) - assign descriptor_rom[90] = 0; // bParityType (None) - assign descriptor_rom[91] = 8; // bDataBits (8 bits) - endmodule From bf3124111c7979187c30a12da2b6e88c95cd19de Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 12:08:57 +0200 Subject: [PATCH 10/90] increase packet size to 64, which is max for endpoint0 --- common/usb_fs_in_pe.v | 2 +- common/usb_fs_out_pe.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_fs_in_pe.v b/common/usb_fs_in_pe.v index d999de4..de03561 100644 --- a/common/usb_fs_in_pe.v +++ b/common/usb_fs_in_pe.v @@ -1,7 +1,7 @@ // The IN Protocol Engine sends data to the host. module usb_fs_in_pe #( parameter NUM_IN_EPS = 11, - parameter MAX_IN_PACKET_SIZE = 32 + parameter MAX_IN_PACKET_SIZE = 64 ) ( input clk, input reset, diff --git a/common/usb_fs_out_pe.v b/common/usb_fs_out_pe.v index 2e43be5..5e4c358 100644 --- a/common/usb_fs_out_pe.v +++ b/common/usb_fs_out_pe.v @@ -1,7 +1,7 @@ // The OUT Protocol Engine receives data from the host. module usb_fs_out_pe #( parameter NUM_OUT_EPS = 1, - parameter MAX_OUT_PACKET_SIZE = 32 + parameter MAX_OUT_PACKET_SIZE = 64 ) ( input clk, input reset, From 32506fa7f5875a2100cdc5914a10740e679de469 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 12:09:39 +0200 Subject: [PATCH 11/90] descriptor: increase endpoint 0 max packet size and cleanup --- common/usb_hid_ctrl_ep.v | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/common/usb_hid_ctrl_ep.v b/common/usb_hid_ctrl_ep.v index cda1b22..59e93d1 100644 --- a/common/usb_hid_ctrl_ep.v +++ b/common/usb_hid_ctrl_ep.v @@ -357,12 +357,6 @@ module usb_hid_ctrl_ep ( end end - - `define CDC_ACM_ENDPOINT 2 - `define CDC_RX_ENDPOINT 1 - `define CDC_TX_ENDPOINT 1 - - wire [7:0] descriptor_rom [0:35]; assign in_ep_data = descriptor_rom[rom_addr]; @@ -373,14 +367,14 @@ module usb_hid_ctrl_ep ( assign descriptor_rom[4] = 'hFF; // bDeviceClass (Communications Device Class) assign descriptor_rom[5] = 'h00; // bDeviceSubClass (Abstract Control Model) assign descriptor_rom[6] = 'h00; // bDeviceProtocol (No class specific protocol required) - assign descriptor_rom[7] = 32; // bMaxPacketSize0 + assign descriptor_rom[7] = 64; // bMaxPacketSize0 assign descriptor_rom[8] = 'hc0; // idVendor[0] VOTI assign descriptor_rom[9] = 'h16; // idVendor[1] assign descriptor_rom[10] = 'hdc; // idProduct[0] assign descriptor_rom[11] = 'h05; // idProduct[1] - assign descriptor_rom[12] = 0; // bcdDevice[0] version minor + assign descriptor_rom[12] = 1; // bcdDevice[0] version minor assign descriptor_rom[13] = 0; // bcdDevice[1] version major assign descriptor_rom[14] = 0; // iManufacturer assign descriptor_rom[15] = 0; // iProduct From 73933b9d499fa53b69f0eda78b65d3a71adb992b Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 12:16:20 +0200 Subject: [PATCH 12/90] rename hid to asp (usbasp) --- .../Makefile | 0 .../bootloader.ldf | 8 ++++---- .../clocks/clk_200M_48M.v | 0 .../clocks/clk_25M_200M.v | 0 .../constraints/ulx3s_v17patch.lpf | 0 .../initialize/boardmeta4MB.bin | 0 .../initialize/boardmeta8MB.bin | 0 .../initialize/initialize4MB.sh | 0 .../initialize/initialize8MB.sh | 0 .../initialize/jump.bin | Bin .../initialize/jump.py | 0 .../tinyfpga_45k.bit | 0 .../tinyfpga_45k_multiboot_flash_micron_32mbit.svf | 0 .../tinyfpga_45k_multiboot_flash_micron_32mbit.vme | 0 ...tinyfpga_45k_multiboot_flash_spansion_64mbit.svf | 0 ...tinyfpga_45k_multiboot_flash_spansion_64mbit.vme | 0 .../tinyfpga_45k_sram.svf | 0 .../tinyfpga_45k_sram.vme | 0 .../top/bootloader_asp_ulx3s.v} | 2 +- .../ulx3s_45f_flash_micron_32mbit.xcf | 0 .../ulx3s_45f_flash_spansion_64mbit.xcf | 0 .../ulx3s_45f_multiboot_micron_32mbit.xcf | 0 .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 0 .../ulx3s_45f_sram.xcf | 0 common/{usb_hid_ctrl_ep.v => usb_asp_ctrl_ep.v} | 2 +- common/usbasp_bootloader.v | 2 +- 26 files changed, 7 insertions(+), 7 deletions(-) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/Makefile (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/bootloader.ldf (90%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/clocks/clk_200M_48M.v (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/clocks/clk_25M_200M.v (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/constraints/ulx3s_v17patch.lpf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/initialize/boardmeta4MB.bin (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/initialize/boardmeta8MB.bin (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/initialize/initialize4MB.sh (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/initialize/initialize8MB.sh (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/initialize/jump.bin (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/initialize/jump.py (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k.bit (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k_multiboot_flash_micron_32mbit.svf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k_multiboot_flash_micron_32mbit.vme (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k_sram.svf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/tinyfpga_45k_sram.vme (100%) rename boards/{ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v => ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v} (95%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/ulx3s_45f_flash_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/ulx3s_45f_flash_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/ulx3s_45f_multiboot_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/ulx3s_45f_multiboot_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-hid => ulx3s-v1.7-45f-usbasp}/ulx3s_45f_sram.xcf (100%) rename common/{usb_hid_ctrl_ep.v => usb_asp_ctrl_ep.v} (96%) diff --git a/boards/ulx3s-v1.7-45f-hid/Makefile b/boards/ulx3s-v1.7-45f-usbasp/Makefile similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/Makefile rename to boards/ulx3s-v1.7-45f-usbasp/Makefile diff --git a/boards/ulx3s-v1.7-45f-hid/bootloader.ldf b/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf similarity index 90% rename from boards/ulx3s-v1.7-45f-hid/bootloader.ldf rename to boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf index 99007f6..5267722 100644 --- a/boards/ulx3s-v1.7-45f-hid/bootloader.ldf +++ b/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf @@ -2,9 +2,9 @@ - - - + + + @@ -51,7 +51,7 @@ - + diff --git a/boards/ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v b/boards/ulx3s-v1.7-45f-usbasp/clocks/clk_200M_48M.v similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/clocks/clk_200M_48M.v rename to boards/ulx3s-v1.7-45f-usbasp/clocks/clk_200M_48M.v diff --git a/boards/ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v b/boards/ulx3s-v1.7-45f-usbasp/clocks/clk_25M_200M.v similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/clocks/clk_25M_200M.v rename to boards/ulx3s-v1.7-45f-usbasp/clocks/clk_25M_200M.v diff --git a/boards/ulx3s-v1.7-45f-hid/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v1.7-45f-usbasp/constraints/ulx3s_v17patch.lpf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/constraints/ulx3s_v17patch.lpf rename to boards/ulx3s-v1.7-45f-usbasp/constraints/ulx3s_v17patch.lpf diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta4MB.bin b/boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta4MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/initialize/boardmeta4MB.bin rename to boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta4MB.bin diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/boardmeta8MB.bin b/boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta8MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/initialize/boardmeta8MB.bin rename to boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta8MB.bin diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/initialize4MB.sh b/boards/ulx3s-v1.7-45f-usbasp/initialize/initialize4MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/initialize/initialize4MB.sh rename to boards/ulx3s-v1.7-45f-usbasp/initialize/initialize4MB.sh diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/initialize8MB.sh b/boards/ulx3s-v1.7-45f-usbasp/initialize/initialize8MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/initialize/initialize8MB.sh rename to boards/ulx3s-v1.7-45f-usbasp/initialize/initialize8MB.sh diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/jump.bin b/boards/ulx3s-v1.7-45f-usbasp/initialize/jump.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/initialize/jump.bin rename to boards/ulx3s-v1.7-45f-usbasp/initialize/jump.bin diff --git a/boards/ulx3s-v1.7-45f-hid/initialize/jump.py b/boards/ulx3s-v1.7-45f-usbasp/initialize/jump.py similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/initialize/jump.py rename to boards/ulx3s-v1.7-45f-usbasp/initialize/jump.py diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k.bit similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k.bit rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k.bit diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.svf rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_micron_32mbit.vme rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.svf rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.svf diff --git a/boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme b/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/tinyfpga_45k_sram.vme rename to boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.vme diff --git a/boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v similarity index 95% rename from boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v rename to boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v index dd86b6a..17ede86 100644 --- a/boards/ulx3s-v1.7-45f-hid/top/bootloader_hid_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v @@ -1,4 +1,4 @@ -module bootloader_hid_ulx3s ( +module bootloader_asp_ulx3s ( input clk_25mhz, inout usb_fpga_dp, diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/ulx3s_45f_flash_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/ulx3s_45f_multiboot_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf b/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_sram.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-hid/ulx3s_45f_sram.xcf rename to boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_sram.xcf diff --git a/common/usb_hid_ctrl_ep.v b/common/usb_asp_ctrl_ep.v similarity index 96% rename from common/usb_hid_ctrl_ep.v rename to common/usb_asp_ctrl_ep.v index 59e93d1..5b2dd52 100644 --- a/common/usb_hid_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -1,4 +1,4 @@ -module usb_hid_ctrl_ep ( +module usb_asp_ctrl_ep ( input clk, input reset, output [6:0] dev_addr, diff --git a/common/usbasp_bootloader.v b/common/usbasp_bootloader.v index 1f28dfd..986fdd3 100644 --- a/common/usbasp_bootloader.v +++ b/common/usbasp_bootloader.v @@ -139,7 +139,7 @@ module usbasp_bootloader ( wire boot_to_user_design; assign boot = host_presence_timeout || boot_to_user_design; - usb_hid_ctrl_ep ctrl_ep_inst ( + usb_asp_ctrl_ep ctrl_ep_inst ( .clk(clk_48mhz), .reset(reset), .dev_addr(dev_addr), From 9df3a11284a8060f126d1fe9a0fa29f72c8a176b Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 12:24:40 +0200 Subject: [PATCH 13/90] remove usbserial from usbasp project --- boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf | 6 -- common/usbasp_bootloader.v | 71 ++++++--------------- 2 files changed, 18 insertions(+), 59 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf b/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf index 5267722..b94bc9d 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf +++ b/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf @@ -21,9 +21,6 @@ - - - @@ -54,9 +51,6 @@ - - - diff --git a/common/usbasp_bootloader.v b/common/usbasp_bootloader.v index 986fdd3..63e75c4 100644 --- a/common/usbasp_bootloader.v +++ b/common/usbasp_bootloader.v @@ -168,47 +168,13 @@ module usbasp_bootloader ( .in_ep_acked(ctrl_in_ep_acked) ); - usb_spi_bridge_ep usb_spi_bridge_ep_inst ( - .clk(clk_48mhz), - .reset(reset), - - // out endpoint interface - .out_ep_req(serial_out_ep_req), - .out_ep_grant(serial_out_ep_grant), - .out_ep_data_avail(serial_out_ep_data_avail), - .out_ep_setup(serial_out_ep_setup), - .out_ep_data_get(serial_out_ep_data_get), - .out_ep_data(out_ep_data), - .out_ep_stall(serial_out_ep_stall), - .out_ep_acked(serial_out_ep_acked), - - // in endpoint interface - .in_ep_req(serial_in_ep_req), - .in_ep_grant(serial_in_ep_grant), - .in_ep_data_free(serial_in_ep_data_free), - .in_ep_data_put(serial_in_ep_data_put), - .in_ep_data(serial_in_ep_data), - .in_ep_data_done(serial_in_ep_data_done), - .in_ep_stall(serial_in_ep_stall), - .in_ep_acked(serial_in_ep_acked), - - // spi interface - .spi_cs_b(spi_cs), - .spi_sck(spi_sck), - .spi_mosi(spi_mosi), - .spi_miso(spi_miso), - - // warm boot interface - .boot_to_user_design(boot_to_user_design) - ); - wire nak_in_ep_grant; wire nak_in_ep_data_free; wire nak_in_ep_acked; usb_fs_pe #( - .NUM_OUT_EPS(5'd2), - .NUM_IN_EPS(5'd3) + .NUM_OUT_EPS(5'd1), + .NUM_IN_EPS(5'd2) ) usb_fs_pe_inst ( .clk(clk_48mhz), .reset(reset), @@ -222,31 +188,30 @@ module usbasp_bootloader ( .dev_addr(dev_addr), // out endpoint interfaces - .out_ep_req({serial_out_ep_req, ctrl_out_ep_req}), - .out_ep_grant({serial_out_ep_grant, ctrl_out_ep_grant}), - .out_ep_data_avail({serial_out_ep_data_avail, ctrl_out_ep_data_avail}), - .out_ep_setup({serial_out_ep_setup, ctrl_out_ep_setup}), - .out_ep_data_get({serial_out_ep_data_get, ctrl_out_ep_data_get}), + .out_ep_req({ctrl_out_ep_req}), + .out_ep_grant({ctrl_out_ep_grant}), + .out_ep_data_avail({ctrl_out_ep_data_avail}), + .out_ep_setup({ctrl_out_ep_setup}), + .out_ep_data_get({ctrl_out_ep_data_get}), .out_ep_data(out_ep_data), - .out_ep_stall({serial_out_ep_stall, ctrl_out_ep_stall}), - .out_ep_acked({serial_out_ep_acked, ctrl_out_ep_acked}), + .out_ep_stall({ctrl_out_ep_stall}), + .out_ep_acked({ctrl_out_ep_acked}), // in endpoint interfaces - .in_ep_req({1'b0, serial_in_ep_req, ctrl_in_ep_req}), - .in_ep_grant({nak_in_ep_grant, serial_in_ep_grant, ctrl_in_ep_grant}), - .in_ep_data_free({nak_in_ep_data_free, serial_in_ep_data_free, ctrl_in_ep_data_free}), - .in_ep_data_put({1'b0, serial_in_ep_data_put, ctrl_in_ep_data_put}), - .in_ep_data({8'b0, serial_in_ep_data[7:0], ctrl_in_ep_data[7:0]}), - .in_ep_data_done({1'b0, serial_in_ep_data_done, ctrl_in_ep_data_done}), - .in_ep_stall({1'b0, serial_in_ep_stall, ctrl_in_ep_stall}), - .in_ep_acked({nak_in_ep_acked, serial_in_ep_acked, ctrl_in_ep_acked}), + .in_ep_req({1'b0, ctrl_in_ep_req}), + .in_ep_grant({nak_in_ep_grant, ctrl_in_ep_grant}), + .in_ep_data_free({nak_in_ep_data_free, ctrl_in_ep_data_free}), + .in_ep_data_put({1'b0, ctrl_in_ep_data_put}), + .in_ep_data({8'b0, ctrl_in_ep_data[7:0]}), + .in_ep_data_done({1'b0, ctrl_in_ep_data_done}), + .in_ep_stall({1'b0, ctrl_in_ep_stall}), + .in_ep_acked({nak_in_ep_acked, ctrl_in_ep_acked}), // sof interface .sof_valid(sof_valid), .frame_index(frame_index) ); - //////////////////////////////////////////////////////////////////////////////// // host presence detection @@ -263,4 +228,4 @@ module usbasp_bootloader ( end assign host_presence_timeout = host_presence_timer[25]; -endmodule \ No newline at end of file +endmodule From ec3713fbb626bafc3129a2a1b2e7e229f44c0edd Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 12:56:44 +0200 Subject: [PATCH 14/90] return max endpoint size to 32 bytes, looks like max that works --- common/usb_asp_ctrl_ep.v | 8 ++++---- common/usb_fs_in_pe.v | 2 +- common/usb_fs_out_pe.v | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 5b2dd52..9d2eaed 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -124,8 +124,8 @@ module usb_asp_ctrl_ep ( reg [6:0] rom_addr = 0; - reg [3:0] out_addr = 0; - reg [7:0] out_buf [0:15]; // PC out transfer should be received here + reg [5:0] out_addr = 0; + reg [7:0] out_buf [0:63]; // PC out transfer should be received here reg save_dev_addr = 0; reg [6:0] new_dev_addr = 0; @@ -329,7 +329,7 @@ module usb_asp_ctrl_ep ( end if (ctrl_xfr_state == DATA_OUT && out_ep_data_valid && ~out_ep_setup) begin - if (out_addr == 0) begin + if (out_addr == 31) begin debug_led <= out_ep_data; end out_addr <= out_addr + 1; @@ -367,7 +367,7 @@ module usb_asp_ctrl_ep ( assign descriptor_rom[4] = 'hFF; // bDeviceClass (Communications Device Class) assign descriptor_rom[5] = 'h00; // bDeviceSubClass (Abstract Control Model) assign descriptor_rom[6] = 'h00; // bDeviceProtocol (No class specific protocol required) - assign descriptor_rom[7] = 64; // bMaxPacketSize0 + assign descriptor_rom[7] = 32; // bMaxPacketSize0 assign descriptor_rom[8] = 'hc0; // idVendor[0] VOTI assign descriptor_rom[9] = 'h16; // idVendor[1] diff --git a/common/usb_fs_in_pe.v b/common/usb_fs_in_pe.v index de03561..d999de4 100644 --- a/common/usb_fs_in_pe.v +++ b/common/usb_fs_in_pe.v @@ -1,7 +1,7 @@ // The IN Protocol Engine sends data to the host. module usb_fs_in_pe #( parameter NUM_IN_EPS = 11, - parameter MAX_IN_PACKET_SIZE = 64 + parameter MAX_IN_PACKET_SIZE = 32 ) ( input clk, input reset, diff --git a/common/usb_fs_out_pe.v b/common/usb_fs_out_pe.v index 5e4c358..2e43be5 100644 --- a/common/usb_fs_out_pe.v +++ b/common/usb_fs_out_pe.v @@ -1,7 +1,7 @@ // The OUT Protocol Engine receives data from the host. module usb_fs_out_pe #( parameter NUM_OUT_EPS = 1, - parameter MAX_OUT_PACKET_SIZE = 64 + parameter MAX_OUT_PACKET_SIZE = 32 ) ( input clk, input reset, From 6757d15d8fcc56f3556692d4967b639f9f981a67 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 14:15:56 +0200 Subject: [PATCH 15/90] reading works (vendorspec DATA_IN) --- common/usb_asp_ctrl_ep.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 9d2eaed..ca7ce9a 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -318,6 +318,9 @@ module usb_asp_ctrl_ep ( end // end 0: standard request default begin // 2: vendor specific request (also would handle 1 or 3) // debug_led <= wValue[7:0]; + rom_addr <= 0; + rom_length <= wLength; + bytes_sent <= 0; out_addr <= 0; end // end 2: vendor specific request endcase From 8789907c7ebffb546b1ebcd8c4b215505f795285 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 14:21:10 +0200 Subject: [PATCH 16/90] cleanup --- common/usb_asp_ctrl_ep.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index ca7ce9a..894ae21 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -124,8 +124,8 @@ module usb_asp_ctrl_ep ( reg [6:0] rom_addr = 0; - reg [5:0] out_addr = 0; - reg [7:0] out_buf [0:63]; // PC out transfer should be received here + reg [4:0] out_addr = 0; // 5 bits -> range 0-31 + reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) reg save_dev_addr = 0; reg [6:0] new_dev_addr = 0; From e813363cfbeea528fa3174e3b6876330335e441a Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 15:51:32 +0200 Subject: [PATCH 17/90] in/out buffering works --- common/usb_asp_ctrl_ep.v | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 894ae21..299fac6 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -124,8 +124,8 @@ module usb_asp_ctrl_ep ( reg [6:0] rom_addr = 0; - reg [4:0] out_addr = 0; // 5 bits -> range 0-31 reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) + reg vendorspec = 1'b0; reg save_dev_addr = 0; reg [6:0] new_dev_addr = 0; @@ -242,6 +242,7 @@ module usb_asp_ctrl_ep ( if (setup_stage_end) begin case (bmRequestType[6:5]) // 2 bits describing request type 0 : begin // 0: standard request + vendorspec <= 1'b0; // not vendor-specific case (bRequest) 'h06 : begin // GET_DESCRIPTOR @@ -317,25 +318,26 @@ module usb_asp_ctrl_ep ( endcase end // end 0: standard request default begin // 2: vendor specific request (also would handle 1 or 3) + vendorspec <= 1'b1; // this is vendor-specific request // debug_led <= wValue[7:0]; rom_addr <= 0; rom_length <= wLength; bytes_sent <= 0; - out_addr <= 0; end // end 2: vendor specific request endcase end - if (ctrl_xfr_state == DATA_IN && more_data_to_send && in_ep_grant && in_ep_data_free) begin + if ( (ctrl_xfr_state == DATA_IN) && more_data_to_send && in_ep_grant && in_ep_data_free) begin rom_addr <= rom_addr + 1; bytes_sent <= bytes_sent + 1; end - if (ctrl_xfr_state == DATA_OUT && out_ep_data_valid && ~out_ep_setup) begin - if (out_addr == 31) begin + if ( (ctrl_xfr_state == DATA_OUT) && out_ep_data_valid && ~out_ep_setup) begin + if (rom_addr == 31) begin debug_led <= out_ep_data; end - out_addr <= out_addr + 1; + out_buf[rom_addr] <= out_ep_data; + rom_addr <= rom_addr + 1; end if (status_stage_end) begin @@ -360,9 +362,9 @@ module usb_asp_ctrl_ep ( end end - wire [7:0] descriptor_rom [0:35]; - assign in_ep_data = descriptor_rom[rom_addr]; + assign in_ep_data = (vendorspec ? out_buf[rom_addr[4:0]] : descriptor_rom[rom_addr]); + wire [7:0] descriptor_rom [0:35]; assign descriptor_rom[0] = 18; // bLength assign descriptor_rom[1] = 1; // bDescriptorType assign descriptor_rom[2] = 'h00; // bcdUSB[0] From 3f84bf7a7e8fd26f41292412d3abc54c6fd674f2 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 19:44:17 +0200 Subject: [PATCH 18/90] host to device (direction out) buffering works --- common/usb_asp_ctrl_ep.v | 45 ++++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 6 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 299fac6..a9f8e25 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -50,6 +50,16 @@ module usb_asp_ctrl_ep ( reg send_zero_length_data_pkt = 0; + ///////////////////////// + /// SPI BUFFERING + ///////////////////////// + reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) + reg [7:0] in_buf [0:31]; // PC in transfer when PC reads back buffered SPI response (32 byte max) + reg [5:0] out_buf_addr, spi_length, spi_bytes_sent; // 0-32 bit address for the buffer + reg [3:0] spi_bit_counter = 8; // 0-8 + reg vendorspec = 1'b0; + + // the default control endpoint gets assigned the device address reg [6:0] dev_addr_i = 0; @@ -124,9 +134,6 @@ module usb_asp_ctrl_ep ( reg [6:0] rom_addr = 0; - reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) - reg vendorspec = 1'b0; - reg save_dev_addr = 0; reg [6:0] new_dev_addr = 0; @@ -323,6 +330,10 @@ module usb_asp_ctrl_ep ( rom_addr <= 0; rom_length <= wLength; bytes_sent <= 0; + // for OUT + spi_length <= wLength; + spi_bytes_sent <= 0; + out_buf_addr <= 0; end // end 2: vendor specific request endcase end @@ -336,9 +347,31 @@ module usb_asp_ctrl_ep ( if (rom_addr == 31) begin debug_led <= out_ep_data; end - out_buf[rom_addr] <= out_ep_data; - rom_addr <= rom_addr + 1; + out_buf[out_buf_addr] <= out_ep_data; + out_buf_addr <= out_buf_addr + 1; + end + + // as out_buf_addr > spi_length + if (spi_bytes_sent < spi_length) + begin + if (out_buf_addr > spi_bytes_sent && spi_bit_counter[3] == 1'b1) + begin + spi_bit_counter <= 0; + end + else + begin + if (spi_bit_counter[3] == 0) + begin + if (spi_bit_counter == 7) + begin + in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; + spi_bytes_sent <= spi_bytes_sent+1; + end + spi_bit_counter <= spi_bit_counter + 1; + end + end end + if (status_stage_end) begin setup_data_addr <= 0; @@ -362,7 +395,7 @@ module usb_asp_ctrl_ep ( end end - assign in_ep_data = (vendorspec ? out_buf[rom_addr[4:0]] : descriptor_rom[rom_addr]); + assign in_ep_data = (vendorspec ? in_buf[rom_addr[4:0]] : descriptor_rom[rom_addr]); wire [7:0] descriptor_rom [0:35]; assign descriptor_rom[0] = 18; // bLength From ff5ccbcf2585f1320d4b6a1daf68c70d3870db4d Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 19:48:45 +0200 Subject: [PATCH 19/90] cleanup, simplify --- common/usb_asp_ctrl_ep.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index a9f8e25..e2670fe 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -352,20 +352,20 @@ module usb_asp_ctrl_ep ( end // as out_buf_addr > spi_length - if (spi_bytes_sent < spi_length) + if (spi_bytes_sent != spi_length) begin - if (out_buf_addr > spi_bytes_sent && spi_bit_counter[3] == 1'b1) + if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 1) begin spi_bit_counter <= 0; end else begin - if (spi_bit_counter[3] == 0) + if (spi_bit_counter[3] == 0) // spi_bit_counter < 8 begin - if (spi_bit_counter == 7) + if (spi_bit_counter == 7) // byte completed begin in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; - spi_bytes_sent <= spi_bytes_sent+1; + spi_bytes_sent <= spi_bytes_sent + 1; end spi_bit_counter <= spi_bit_counter + 1; end From 426c8eb4366c71b7817939f391b9adc533e7e2a4 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 20:11:52 +0200 Subject: [PATCH 20/90] added spi shifting but not yet used --- common/usb_asp_ctrl_ep.v | 47 +++++++++++++++++++++++++++++++++++----- 1 file changed, 41 insertions(+), 6 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index e2670fe..e92fd47 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -4,6 +4,14 @@ module usb_asp_ctrl_ep ( output [6:0] dev_addr, output reg [7:0] debug_led, + + //////////////////// + // spi chip + //////////////////// + output spi_miso, + input spi_mosi, + output reg spi_clk = 1, + output reg spi_csn = 1, //////////////////// // out endpoint interface @@ -58,7 +66,14 @@ module usb_asp_ctrl_ep ( reg [5:0] out_buf_addr, spi_length, spi_bytes_sent; // 0-32 bit address for the buffer reg [3:0] spi_bit_counter = 8; // 0-8 reg vendorspec = 1'b0; - + // help with assembling the SPI byte + reg [7:0] spi_miso_byte; // SPI output buffer circular-shifted (same as input?) + wire [7:0] spi_miso_byte_next; + assign spi_miso_byte_next = {spi_miso_byte[6:0], spi_miso}; // input with shifting, MSB enters shift-register first + assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first + reg [7:0] spi_mosi_byte; // SPI output buffer circular-shifted (same as input?) + wire [7:0] spi_mosi_byte_next; + assign spi_mosi_byte_next = {spi_mosi_byte[6:0], 1'b0}; // input with shifting, MSB enters shift-register first // the default control endpoint gets assigned the device address @@ -352,25 +367,45 @@ module usb_asp_ctrl_ep ( end // as out_buf_addr > spi_length + + if (spi_bytes_sent != spi_length) begin + spi_csn <= 0; // enable chip if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 1) begin + spi_mosi_byte <= out_buf[spi_bytes_sent]; spi_bit_counter <= 0; + spi_clk <= 1; end else begin if (spi_bit_counter[3] == 0) // spi_bit_counter < 8 begin - if (spi_bit_counter == 7) // byte completed - begin - in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; - spi_bytes_sent <= spi_bytes_sent + 1; + if (spi_clk) + begin // clock=1: send data to SPI chip + spi_mosi_byte <= spi_mosi_byte_next; // shift output to SPI chip + end + else + begin // clock=0: read data from SPI chip + if (spi_bit_counter == 7) // byte completed + begin + spi_miso_byte <= spi_miso_byte_next; + in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; // debug: invert all what we received + // in_buf[spi_bytes_sent] <= spi_miso_byte_next; + spi_bytes_sent <= spi_bytes_sent + 1; + end + spi_bit_counter <= spi_bit_counter + 1; end - spi_bit_counter <= spi_bit_counter + 1; + spi_clk <= ~spi_clk; end end end + else // nothing to send: spi_bytes_sent != spi_length + spi_clk <= 1; // clock inactive + spi_csn <= 1; // disable chip + begin + end if (status_stage_end) begin From a46cb5128180f8733d75e3540a50a221b3f57742 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 20:21:02 +0200 Subject: [PATCH 21/90] connecting SPI chip --- common/usb_asp_ctrl_ep.v | 8 ++++---- common/usbasp_bootloader.v | 6 ++++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index e92fd47..03e5190 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -8,8 +8,8 @@ module usb_asp_ctrl_ep ( //////////////////// // spi chip //////////////////// - output spi_miso, - input spi_mosi, + input spi_miso, + output spi_mosi, output reg spi_clk = 1, output reg spi_csn = 1, @@ -391,8 +391,8 @@ module usb_asp_ctrl_ep ( if (spi_bit_counter == 7) // byte completed begin spi_miso_byte <= spi_miso_byte_next; - in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; // debug: invert all what we received - // in_buf[spi_bytes_sent] <= spi_miso_byte_next; + // in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; // debug: invert all what we received + in_buf[spi_bytes_sent] <= spi_miso_byte_next; spi_bytes_sent <= spi_bytes_sent + 1; end spi_bit_counter <= spi_bit_counter + 1; diff --git a/common/usbasp_bootloader.v b/common/usbasp_bootloader.v index 63e75c4..e5da122 100644 --- a/common/usbasp_bootloader.v +++ b/common/usbasp_bootloader.v @@ -146,6 +146,12 @@ module usbasp_bootloader ( // debug led .debug_led(debug_led), + + // SPI chip interface + .spi_csn(spi_cs), + .spi_clk(spi_sck), + .spi_mosi(spi_mosi), + .spi_miso(spi_miso), // out endpoint interface .out_ep_req(ctrl_out_ep_req), From 9768e7fac4400092b4adf32a46bf92935b65c0a6 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 20:35:02 +0200 Subject: [PATCH 22/90] SPI cleanup but it doesn't work (0xff returned) --- common/usb_asp_ctrl_ep.v | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 03e5190..1774939 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -366,17 +366,19 @@ module usb_asp_ctrl_ep ( out_buf_addr <= out_buf_addr + 1; end - // as out_buf_addr > spi_length - - - if (spi_bytes_sent != spi_length) + if (spi_bytes_sent == spi_length) + begin // nothing to send + spi_clk <= 1; // clock inactive + spi_csn <= 1; // disable chip + end + else // spi_bytes_sent != spi_length begin spi_csn <= 0; // enable chip if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 1) begin spi_mosi_byte <= out_buf[spi_bytes_sent]; spi_bit_counter <= 0; - spi_clk <= 1; + // spi_clk <= 1; end else begin @@ -388,9 +390,9 @@ module usb_asp_ctrl_ep ( end else begin // clock=0: read data from SPI chip + spi_miso_byte <= spi_miso_byte_next; // shift input from SPI chip if (spi_bit_counter == 7) // byte completed begin - spi_miso_byte <= spi_miso_byte_next; // in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; // debug: invert all what we received in_buf[spi_bytes_sent] <= spi_miso_byte_next; spi_bytes_sent <= spi_bytes_sent + 1; @@ -401,11 +403,6 @@ module usb_asp_ctrl_ep ( end end end - else // nothing to send: spi_bytes_sent != spi_length - spi_clk <= 1; // clock inactive - spi_csn <= 1; // disable chip - begin - end if (status_stage_end) begin From 98b21a5569a287d7944adfea7ce2e0386d0c29aa Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 29 Jul 2018 23:30:59 +0200 Subject: [PATCH 23/90] spi flash started to respond to read command 0x03 --- .../top/bootloader_asp_ulx3s.v | 3 +- common/usb_asp_ctrl_ep.v | 60 +++++++++++++------ 2 files changed, 44 insertions(+), 19 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v index 17ede86..857af7a 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v @@ -100,7 +100,8 @@ module bootloader_asp_ulx3s ( //////////////////////////////////////////////////////////////////////////////// assign wifi_gpio0 = btn[0]; //assign led[5] = boot; - assign led = debug_led; + // assign led = debug_led; + assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; always @(posedge clk_48mhz) begin diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 1774939..34e58f7 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -67,13 +67,16 @@ module usb_asp_ctrl_ep ( reg [3:0] spi_bit_counter = 8; // 0-8 reg vendorspec = 1'b0; // help with assembling the SPI byte - reg [7:0] spi_miso_byte; // SPI output buffer circular-shifted (same as input?) + reg [7:0] spi_miso_byte; // host input, device output wire [7:0] spi_miso_byte_next; assign spi_miso_byte_next = {spi_miso_byte[6:0], spi_miso}; // input with shifting, MSB enters shift-register first - assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first - reg [7:0] spi_mosi_byte; // SPI output buffer circular-shifted (same as input?) + reg [7:0] spi_mosi_byte; // host output, device input wire [7:0] spi_mosi_byte_next; assign spi_mosi_byte_next = {spi_mosi_byte[6:0], 1'b0}; // input with shifting, MSB enters shift-register first + assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first + + + reg [20:0] superslow; // the default control endpoint gets assigned the device address @@ -342,13 +345,19 @@ module usb_asp_ctrl_ep ( default begin // 2: vendor specific request (also would handle 1 or 3) vendorspec <= 1'b1; // this is vendor-specific request // debug_led <= wValue[7:0]; - rom_addr <= 0; - rom_length <= wLength; - bytes_sent <= 0; + if (in_data_stage) + begin + rom_addr <= 0; + rom_length <= wLength; + bytes_sent <= 0; + end // for OUT - spi_length <= wLength; - spi_bytes_sent <= 0; - out_buf_addr <= 0; + if (out_data_stage) + begin + out_buf_addr <= 0; + spi_length <= wLength; + spi_bytes_sent <= 0; + end end // end 2: vendor specific request endcase end @@ -366,6 +375,8 @@ module usb_asp_ctrl_ep ( out_buf_addr <= out_buf_addr + 1; end + superslow <= superslow + 1; + if (superslow == 0) if (spi_bytes_sent == spi_length) begin // nothing to send spi_clk <= 1; // clock inactive @@ -374,22 +385,35 @@ module usb_asp_ctrl_ep ( else // spi_bytes_sent != spi_length begin spi_csn <= 0; // enable chip - if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 1) + if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 1 && spi_bit_counter != 15) begin - spi_mosi_byte <= out_buf[spi_bytes_sent]; - spi_bit_counter <= 0; - // spi_clk <= 1; + spi_mosi_byte[7:0] <= out_buf[spi_bytes_sent]; + spi_bit_counter <= 15; + spi_clk <= 1; end else begin + if (spi_bit_counter == 15) + begin // initial dummy clock cycle + if (spi_clk == 1) + begin + spi_clk <= 0; + end + if (spi_clk == 0) + begin + spi_bit_counter <= 0; + spi_clk <= 1; + end + end if (spi_bit_counter[3] == 0) // spi_bit_counter < 8 begin - if (spi_clk) - begin // clock=1: send data to SPI chip + if (spi_clk == 1) + begin // clock=0: send data to SPI chip spi_mosi_byte <= spi_mosi_byte_next; // shift output to SPI chip + spi_clk <= 0; end - else - begin // clock=0: read data from SPI chip + if (spi_clk == 0) + begin // clock=1: read data from SPI chip spi_miso_byte <= spi_miso_byte_next; // shift input from SPI chip if (spi_bit_counter == 7) // byte completed begin @@ -398,8 +422,8 @@ module usb_asp_ctrl_ep ( spi_bytes_sent <= spi_bytes_sent + 1; end spi_bit_counter <= spi_bit_counter + 1; + spi_clk <= 1; end - spi_clk <= ~spi_clk; end end end From b9c8d4e86e0608e5fd53729031851babd5ea16af Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 01:33:27 +0200 Subject: [PATCH 24/90] starts to read correct value, slowed down for blink leds to be visible --- common/usb_asp_ctrl_ep.v | 42 ++++++++++++++-------------------------- 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 34e58f7..63d3063 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -64,7 +64,7 @@ module usb_asp_ctrl_ep ( reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) reg [7:0] in_buf [0:31]; // PC in transfer when PC reads back buffered SPI response (32 byte max) reg [5:0] out_buf_addr, spi_length, spi_bytes_sent; // 0-32 bit address for the buffer - reg [3:0] spi_bit_counter = 8; // 0-8 + reg [3:0] spi_bit_counter = 15; // 0-15 reg vendorspec = 1'b0; // help with assembling the SPI byte reg [7:0] spi_miso_byte; // host input, device output @@ -76,7 +76,7 @@ module usb_asp_ctrl_ep ( assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first - reg [20:0] superslow; + reg [15:0] superslow; // the default control endpoint gets assigned the device address @@ -381,52 +381,40 @@ module usb_asp_ctrl_ep ( begin // nothing to send spi_clk <= 1; // clock inactive spi_csn <= 1; // disable chip + spi_bit_counter <= 15; end else // spi_bytes_sent != spi_length begin spi_csn <= 0; // enable chip - if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 1 && spi_bit_counter != 15) + if (spi_bit_counter == 15 && out_buf_addr != spi_bytes_sent) begin - spi_mosi_byte[7:0] <= out_buf[spi_bytes_sent]; - spi_bit_counter <= 15; - spi_clk <= 1; + spi_bit_counter <= 0; end - else - begin - if (spi_bit_counter == 15) - begin // initial dummy clock cycle - if (spi_clk == 1) - begin - spi_clk <= 0; - end - if (spi_clk == 0) - begin - spi_bit_counter <= 0; - spi_clk <= 1; - end - end - if (spi_bit_counter[3] == 0) // spi_bit_counter < 8 + + if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 0) begin if (spi_clk == 1) begin // clock=0: send data to SPI chip - spi_mosi_byte <= spi_mosi_byte_next; // shift output to SPI chip + if (spi_bit_counter[2:0] == 0) + spi_mosi_byte <= out_buf[spi_bytes_sent]; + else + spi_mosi_byte <= spi_mosi_byte_next; // shift output to SPI chip spi_clk <= 0; end if (spi_clk == 0) begin // clock=1: read data from SPI chip spi_miso_byte <= spi_miso_byte_next; // shift input from SPI chip - if (spi_bit_counter == 7) // byte completed + if (spi_bit_counter[2:0] == 7) // byte completed begin // in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; // debug: invert all what we received in_buf[spi_bytes_sent] <= spi_miso_byte_next; spi_bytes_sent <= spi_bytes_sent + 1; end - spi_bit_counter <= spi_bit_counter + 1; + spi_bit_counter[2:0] <= spi_bit_counter[2:0] + 1; spi_clk <= 1; end - end - end - end + end // spi bit counter < 8 + end // spi_bytes_sent != spi_length if (status_stage_end) begin From ceb2dde0f97cf4dfa5dbe2a4010140ec47220313 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 01:39:35 +0200 Subject: [PATCH 25/90] works fast, remoove SPI slowdown --- common/usb_asp_ctrl_ep.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 63d3063..a9590db 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -76,7 +76,7 @@ module usb_asp_ctrl_ep ( assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first - reg [15:0] superslow; + reg [1:0] superslow; // the default control endpoint gets assigned the device address @@ -375,8 +375,8 @@ module usb_asp_ctrl_ep ( out_buf_addr <= out_buf_addr + 1; end - superslow <= superslow + 1; - if (superslow == 0) + //superslow <= superslow + 1; + //if (superslow == 0) if (spi_bytes_sent == spi_length) begin // nothing to send spi_clk <= 1; // clock inactive From 6159aa8eb719610c3fa3771b819097203e26a077 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 02:23:33 +0200 Subject: [PATCH 26/90] cleanup and spi_continue added --- common/usb_asp_ctrl_ep.v | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index a9590db..e79ccda 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -66,6 +66,8 @@ module usb_asp_ctrl_ep ( reg [5:0] out_buf_addr, spi_length, spi_bytes_sent; // 0-32 bit address for the buffer reg [3:0] spi_bit_counter = 15; // 0-15 reg vendorspec = 1'b0; + reg spi_continue = 0; // 0:normal packet (reset start, closed end) 1:packet continued (open start, open end) + // help with assembling the SPI byte reg [7:0] spi_miso_byte; // host input, device output wire [7:0] spi_miso_byte_next; @@ -75,6 +77,7 @@ module usb_asp_ctrl_ep ( assign spi_mosi_byte_next = {spi_mosi_byte[6:0], 1'b0}; // input with shifting, MSB enters shift-register first assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first + wire more_data_out; reg [1:0] superslow; @@ -351,9 +354,9 @@ module usb_asp_ctrl_ep ( rom_length <= wLength; bytes_sent <= 0; end - // for OUT if (out_data_stage) begin + spi_continue <= wValue[0]; out_buf_addr <= 0; spi_length <= wLength; spi_bytes_sent <= 0; @@ -374,24 +377,29 @@ module usb_asp_ctrl_ep ( out_buf[out_buf_addr] <= out_ep_data; out_buf_addr <= out_buf_addr + 1; end - + //superslow <= superslow + 1; //if (superslow == 0) if (spi_bytes_sent == spi_length) begin // nothing to send - spi_clk <= 1; // clock inactive - spi_csn <= 1; // disable chip - spi_bit_counter <= 15; + if (spi_continue == 0) + begin + spi_clk <= 1; // clock inactive + spi_csn <= 1; // disable chip + spi_bit_counter <= 15; + end end else // spi_bytes_sent != spi_length begin spi_csn <= 0; // enable chip - if (spi_bit_counter == 15 && out_buf_addr != spi_bytes_sent) + if(out_buf_addr != spi_bytes_sent) // more spi data begin - spi_bit_counter <= 0; - end + if (spi_bit_counter == 15) + begin + spi_bit_counter <= 0; // skip one cycle + end - if (out_buf_addr != spi_bytes_sent && spi_bit_counter[3] == 0) + if (spi_bit_counter[3] == 0) begin if (spi_clk == 1) begin // clock=0: send data to SPI chip @@ -399,7 +407,7 @@ module usb_asp_ctrl_ep ( spi_mosi_byte <= out_buf[spi_bytes_sent]; else spi_mosi_byte <= spi_mosi_byte_next; // shift output to SPI chip - spi_clk <= 0; + // spi_clk <= 0; end if (spi_clk == 0) begin // clock=1: read data from SPI chip @@ -411,9 +419,11 @@ module usb_asp_ctrl_ep ( spi_bytes_sent <= spi_bytes_sent + 1; end spi_bit_counter[2:0] <= spi_bit_counter[2:0] + 1; - spi_clk <= 1; + // spi_clk <= 1; end + spi_clk <= ~spi_clk; end // spi bit counter < 8 + end // more_spi_data end // spi_bytes_sent != spi_length From eb66269b1ebfb6c03b80fc8c83da0a0b3cb0f5c1 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 02:46:51 +0200 Subject: [PATCH 27/90] continue fix, seems to work although I'm not 100% shure is continue really done correctly --- common/usb_asp_ctrl_ep.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index e79ccda..6abff10 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -348,6 +348,7 @@ module usb_asp_ctrl_ep ( default begin // 2: vendor specific request (also would handle 1 or 3) vendorspec <= 1'b1; // this is vendor-specific request // debug_led <= wValue[7:0]; + spi_continue <= wValue[0]; if (in_data_stage) begin rom_addr <= 0; @@ -356,7 +357,6 @@ module usb_asp_ctrl_ep ( end if (out_data_stage) begin - spi_continue <= wValue[0]; out_buf_addr <= 0; spi_length <= wLength; spi_bytes_sent <= 0; From 1c0682402a009572776bc807af7f5fc5689846b4 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 16:41:05 +0200 Subject: [PATCH 28/90] small todo --- common/usb_asp_ctrl_ep.v | 44 +++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 6abff10..c009c28 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -347,20 +347,30 @@ module usb_asp_ctrl_ep ( end // end 0: standard request default begin // 2: vendor specific request (also would handle 1 or 3) vendorspec <= 1'b1; // this is vendor-specific request - // debug_led <= wValue[7:0]; - spi_continue <= wValue[0]; - if (in_data_stage) - begin - rom_addr <= 0; - rom_length <= wLength; - bytes_sent <= 0; - end - if (out_data_stage) - begin - out_buf_addr <= 0; - spi_length <= wLength; - spi_bytes_sent <= 0; - end + case (bRequest) + 0: begin // write or read block + // debug_led <= wValue[7:0]; + spi_continue <= wValue[0]; + if (in_data_stage) + begin + rom_addr <= 0; + rom_length <= wLength; + bytes_sent <= 0; + end + if (out_data_stage) + begin + out_buf_addr <= 0; + spi_length <= wLength; + spi_bytes_sent <= 0; + end + end // end bRequest 0 + + 1: begin // read SPI state (did it finish?) + end + + default begin // catch all other bRequest != 0 + end + endcase end // end 2: vendor specific request endcase end @@ -496,3 +506,9 @@ module usb_asp_ctrl_ep ( assign descriptor_rom[35] = 0; // iInterface endmodule + +/* TODO +[ ] duplicate packets sometimes recived (did SPI finish before new packet came') +[ ] lsusb -vvv -d shows descriptor and vailts, try to dump traffic with wireshark +[ ] overrun signal +*/ \ No newline at end of file From 6bca77ebe611c5dc7319bbbf33d25ae8e49394fb Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 16:41:16 +0200 Subject: [PATCH 29/90] remove nak interface --- common/usbasp_bootloader.v | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/common/usbasp_bootloader.v b/common/usbasp_bootloader.v index e5da122..3c0e887 100644 --- a/common/usbasp_bootloader.v +++ b/common/usbasp_bootloader.v @@ -82,8 +82,6 @@ module usbasp_bootloader ( pwm_cnt <= pwm_cnt + 1'b1; assign led = led_pwm > pwm_cnt; - - //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////// @@ -174,13 +172,9 @@ module usbasp_bootloader ( .in_ep_acked(ctrl_in_ep_acked) ); - wire nak_in_ep_grant; - wire nak_in_ep_data_free; - wire nak_in_ep_acked; - usb_fs_pe #( .NUM_OUT_EPS(5'd1), - .NUM_IN_EPS(5'd2) + .NUM_IN_EPS(5'd1) ) usb_fs_pe_inst ( .clk(clk_48mhz), .reset(reset), @@ -204,14 +198,14 @@ module usbasp_bootloader ( .out_ep_acked({ctrl_out_ep_acked}), // in endpoint interfaces - .in_ep_req({1'b0, ctrl_in_ep_req}), - .in_ep_grant({nak_in_ep_grant, ctrl_in_ep_grant}), - .in_ep_data_free({nak_in_ep_data_free, ctrl_in_ep_data_free}), - .in_ep_data_put({1'b0, ctrl_in_ep_data_put}), - .in_ep_data({8'b0, ctrl_in_ep_data[7:0]}), - .in_ep_data_done({1'b0, ctrl_in_ep_data_done}), - .in_ep_stall({1'b0, ctrl_in_ep_stall}), - .in_ep_acked({nak_in_ep_acked, ctrl_in_ep_acked}), + .in_ep_req({ctrl_in_ep_req}), + .in_ep_grant({ctrl_in_ep_grant}), + .in_ep_data_free({ctrl_in_ep_data_free}), + .in_ep_data_put({ctrl_in_ep_data_put}), + .in_ep_data({ctrl_in_ep_data[7:0]}), + .in_ep_data_done({ctrl_in_ep_data_done}), + .in_ep_stall({ctrl_in_ep_stall}), + .in_ep_acked({ctrl_in_ep_acked}), // sof interface .sof_valid(sof_valid), From 2271867f771a439881a38b4a9ca550b96fab192e Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 16:52:00 +0200 Subject: [PATCH 30/90] debounce and prolong reset, after programming board is normally recognized --- .../top/bootloader_asp_ulx3s.v | 25 +++++++++++++++---- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v index 857af7a..6b957fd 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v @@ -43,7 +43,9 @@ module bootloader_asp_ulx3s ( //////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// - reg reset = 1'b1; + reg [15:0] reset_counter = 0; // counter for debouce and prolong reset + wire reset; + assign reset = ~reset_counter[15]; wire usb_p_tx; wire usb_n_tx; wire usb_p_rx; @@ -91,6 +93,23 @@ module bootloader_asp_ulx3s ( assign flash_clk = S_flash_clk; assign flash_csn = S_flash_csn; + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Debonuce and prolong RESET + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + always @(posedge clk_48mhz) + begin + if (btn[1] | ~clk_ready) + reset_counter <= 0; + else + if (reset_counter[15] == 0) + reset_counter <= reset_counter + 1; + end + + //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////// @@ -103,9 +122,5 @@ module bootloader_asp_ulx3s ( // assign led = debug_led; assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; - always @(posedge clk_48mhz) - begin - reset <= btn[1] | ~clk_ready; - end endmodule From ce6c01a00d3e80d0775a301db980ca837f1ee202 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 17:17:04 +0200 Subject: [PATCH 31/90] blink debug LED on spi overruns --- .../top/bootloader_asp_ulx3s.v | 4 ++-- common/usb_asp_ctrl_ep.v | 20 ++++++++++--------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v index 6b957fd..f3aa79e 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v @@ -119,8 +119,8 @@ module bootloader_asp_ulx3s ( //////////////////////////////////////////////////////////////////////////////// assign wifi_gpio0 = btn[0]; //assign led[5] = boot; - // assign led = debug_led; - assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + assign led = debug_led; + // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; endmodule diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index c009c28..99870f9 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -63,7 +63,9 @@ module usb_asp_ctrl_ep ( ///////////////////////// reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) reg [7:0] in_buf [0:31]; // PC in transfer when PC reads back buffered SPI response (32 byte max) - reg [5:0] out_buf_addr, spi_length, spi_bytes_sent; // 0-32 bit address for the buffer + reg [5:0] out_buf_addr; // 0-32 address for the buffer + reg [5:0] spi_length = 0; // 0-32 number of bytes to be sent by OUT + reg [5:0] spi_bytes_sent = 0; // 0-32 bit current number of bytes sent by OUT reg [3:0] spi_bit_counter = 15; // 0-15 reg vendorspec = 1'b0; reg spi_continue = 0; // 0:normal packet (reset start, closed end) 1:packet continued (open start, open end) @@ -269,7 +271,7 @@ module usb_asp_ctrl_ep ( if (setup_stage_end) begin case (bmRequestType[6:5]) // 2 bits describing request type - 0 : begin // 0: standard request + 0: begin // 0: standard request vendorspec <= 1'b0; // not vendor-specific case (bRequest) 'h06 : begin @@ -345,11 +347,10 @@ module usb_asp_ctrl_ep ( end endcase end // end 0: standard request - default begin // 2: vendor specific request (also would handle 1 or 3) + 2: begin // 2: vendor specific request (also would handle 1 or 3) vendorspec <= 1'b1; // this is vendor-specific request case (bRequest) - 0: begin // write or read block - // debug_led <= wValue[7:0]; + 0: begin // write or read SPI data block spi_continue <= wValue[0]; if (in_data_stage) begin @@ -362,6 +363,8 @@ module usb_asp_ctrl_ep ( out_buf_addr <= 0; spi_length <= wLength; spi_bytes_sent <= 0; + if (spi_bytes_sent != spi_length) + debug_led[7] <= ~debug_led[7]; // indicate overrun, new packet arrived before SPI finished end end // end bRequest 0 @@ -372,6 +375,8 @@ module usb_asp_ctrl_ep ( end endcase end // end 2: vendor specific request + default begin // default 1,3: unhandled + end // end defaul endcase end @@ -381,9 +386,6 @@ module usb_asp_ctrl_ep ( end if ( (ctrl_xfr_state == DATA_OUT) && out_ep_data_valid && ~out_ep_setup) begin - if (rom_addr == 31) begin - debug_led <= out_ep_data; - end out_buf[out_buf_addr] <= out_ep_data; out_buf_addr <= out_buf_addr + 1; end @@ -406,7 +408,7 @@ module usb_asp_ctrl_ep ( begin if (spi_bit_counter == 15) begin - spi_bit_counter <= 0; // skip one cycle + spi_bit_counter <= 0; // skip one cycle, flash needs small delay to start listening end if (spi_bit_counter[3] == 0) From 1f3d48baf8a53eb4d109632ae400debfa45bfb5b Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 19:46:25 +0200 Subject: [PATCH 32/90] cleanup, add state to read SPI status --- common/usb_asp_ctrl_ep.v | 62 +++++++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 99870f9..48f4f18 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -63,11 +63,11 @@ module usb_asp_ctrl_ep ( ///////////////////////// reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) reg [7:0] in_buf [0:31]; // PC in transfer when PC reads back buffered SPI response (32 byte max) - reg [5:0] out_buf_addr; // 0-32 address for the buffer + reg [5:0] out_buf_addr = 0; // 0-32 address for the buffer reg [5:0] spi_length = 0; // 0-32 number of bytes to be sent by OUT reg [5:0] spi_bytes_sent = 0; // 0-32 bit current number of bytes sent by OUT reg [3:0] spi_bit_counter = 15; // 0-15 - reg vendorspec = 1'b0; + reg send_in_buf = 0; reg spi_continue = 0; // 0:normal packet (reset start, closed end) 1:packet continued (open start, open end) // help with assembling the SPI byte @@ -272,7 +272,7 @@ module usb_asp_ctrl_ep ( if (setup_stage_end) begin case (bmRequestType[6:5]) // 2 bits describing request type 0: begin // 0: standard request - vendorspec <= 1'b0; // not vendor-specific + send_in_buf <= 0; // not vendor-specific case (bRequest) 'h06 : begin // GET_DESCRIPTOR @@ -347,28 +347,39 @@ module usb_asp_ctrl_ep ( end endcase end // end 0: standard request + 2: begin // 2: vendor specific request (also would handle 1 or 3) - vendorspec <= 1'b1; // this is vendor-specific request case (bRequest) 0: begin // write or read SPI data block spi_continue <= wValue[0]; if (in_data_stage) begin - rom_addr <= 0; - rom_length <= wLength; + send_in_buf <= 1; // this is vendor-specific request, send data from RAM buffer, not descriptor ROM + rom_addr <= 0; // misnomer: rom_addr here addresses RAM buffer actually + rom_length <= wLength; // misnomer: rom_length is actually RAM bytes to be sent bytes_sent <= 0; end if (out_data_stage) begin + send_in_buf <= 0; out_buf_addr <= 0; spi_length <= wLength; spi_bytes_sent <= 0; if (spi_bytes_sent != spi_length) - debug_led[7] <= ~debug_led[7]; // indicate overrun, new packet arrived before SPI finished + debug_led <= debug_led + 1; // indicate overrun, new packet arrived before SPI finished end end // end bRequest 0 - 1: begin // read SPI state (did it finish?) + 1: begin // read SPI state (0:free 1:busy) IN request + // choose ROM location which is not likely to change + // because it will send data from ROM, not buffer + send_in_buf <= 0; + if (spi_bytes_sent == spi_length) + rom_addr <= 5; // must point to 0 in ROM descriptor + else + rom_addr <= 1; // must point to 1 in ROM descriptor + rom_length <= 1; + bytes_sent <= 0; end default begin // catch all other bRequest != 0 @@ -398,7 +409,7 @@ module usb_asp_ctrl_ep ( begin spi_clk <= 1; // clock inactive spi_csn <= 1; // disable chip - spi_bit_counter <= 15; + spi_bit_counter <= 15; // skip first clock cycle end end else // spi_bytes_sent != spi_length @@ -406,32 +417,26 @@ module usb_asp_ctrl_ep ( spi_csn <= 0; // enable chip if(out_buf_addr != spi_bytes_sent) // more spi data begin - if (spi_bit_counter == 15) - begin - spi_bit_counter <= 0; // skip one cycle, flash needs small delay to start listening - end - - if (spi_bit_counter[3] == 0) + if (spi_bit_counter[3]) + spi_bit_counter <= 0; // skip one cycle, flash needs small delay from csn=0 to clk + else // spi_bit_counter < 8 begin if (spi_clk == 1) begin // clock=0: send data to SPI chip if (spi_bit_counter[2:0] == 0) - spi_mosi_byte <= out_buf[spi_bytes_sent]; + spi_mosi_byte <= out_buf[spi_bytes_sent]; // new byte from buffer else - spi_mosi_byte <= spi_mosi_byte_next; // shift output to SPI chip - // spi_clk <= 0; + spi_mosi_byte <= spi_mosi_byte_next; // shift bit output to SPI chip end if (spi_clk == 0) begin // clock=1: read data from SPI chip spi_miso_byte <= spi_miso_byte_next; // shift input from SPI chip if (spi_bit_counter[2:0] == 7) // byte completed begin - // in_buf[spi_bytes_sent] <= ~out_buf[spi_bytes_sent]; // debug: invert all what we received - in_buf[spi_bytes_sent] <= spi_miso_byte_next; + in_buf[spi_bytes_sent] <= spi_miso_byte_next; // complete byte to IN buffer, later sent spi_bytes_sent <= spi_bytes_sent + 1; end spi_bit_counter[2:0] <= spi_bit_counter[2:0] + 1; - // spi_clk <= 1; end spi_clk <= ~spi_clk; end // spi bit counter < 8 @@ -458,19 +463,24 @@ module usb_asp_ctrl_ep ( dev_addr_i <= 0; setup_data_addr <= 0; save_dev_addr <= 0; - end + send_in_buf <= 0; + out_buf_addr <= 0; + spi_length <= 0; + spi_bytes_sent <= 0; + debug_led <= 0; + end end - assign in_ep_data = (vendorspec ? in_buf[rom_addr[4:0]] : descriptor_rom[rom_addr]); + assign in_ep_data = (send_in_buf ? in_buf[rom_addr[4:0]] : descriptor_rom[rom_addr]); wire [7:0] descriptor_rom [0:35]; assign descriptor_rom[0] = 18; // bLength assign descriptor_rom[1] = 1; // bDescriptorType assign descriptor_rom[2] = 'h00; // bcdUSB[0] assign descriptor_rom[3] = 'h02; // bcdUSB[1] - assign descriptor_rom[4] = 'hFF; // bDeviceClass (Communications Device Class) - assign descriptor_rom[5] = 'h00; // bDeviceSubClass (Abstract Control Model) - assign descriptor_rom[6] = 'h00; // bDeviceProtocol (No class specific protocol required) + assign descriptor_rom[4] = 'hFF; // bDeviceClass + assign descriptor_rom[5] = 'h00; // bDeviceSubClass + assign descriptor_rom[6] = 'h00; // bDeviceProtocol assign descriptor_rom[7] = 32; // bMaxPacketSize0 assign descriptor_rom[8] = 'hc0; // idVendor[0] VOTI From eeccbfe89c361c98af1093174c631c9a15f35264 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 19:47:12 +0200 Subject: [PATCH 33/90] todo update --- common/usb_asp_ctrl_ep.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 48f4f18..50a99a4 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -522,5 +522,5 @@ endmodule /* TODO [ ] duplicate packets sometimes recived (did SPI finish before new packet came') [ ] lsusb -vvv -d shows descriptor and vailts, try to dump traffic with wireshark -[ ] overrun signal -*/ \ No newline at end of file +[ ] overrun signal - problem: SPI often stalls +*/ From d442907f3610e953977883a09967f826324bfa88 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 21:01:12 +0200 Subject: [PATCH 34/90] change to circular spi out buffering, slowed down works It didn't help much and when intterrupted the spi read buffer is left out of sync from spi write buffer. Maybe this should be reverted to non-circular (buffer reset at each usb packet) --- common/usb_asp_ctrl_ep.v | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 50a99a4..a35ab1e 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -61,12 +61,13 @@ module usb_asp_ctrl_ep ( ///////////////////////// /// SPI BUFFERING ///////////////////////// - reg [7:0] out_buf [0:31]; // PC out transfer should be received here (32 byte max) + reg [7:0] out_buf [0:63]; // PC out transfer should be received here (64 byte max) reg [7:0] in_buf [0:31]; // PC in transfer when PC reads back buffered SPI response (32 byte max) - reg [5:0] out_buf_addr = 0; // 0-32 address for the buffer + reg [5:0] out_buf_addr_usb = 0; // 0-32 address for the buffer + reg [5:0] out_buf_addr_spi = 0; // 0-32 address for the buffer for SPI sender reg [5:0] spi_length = 0; // 0-32 number of bytes to be sent by OUT reg [5:0] spi_bytes_sent = 0; // 0-32 bit current number of bytes sent by OUT - reg [3:0] spi_bit_counter = 15; // 0-15 + reg [3:0] spi_bit_counter = 10; // 0-15 reg send_in_buf = 0; reg spi_continue = 0; // 0:normal packet (reset start, closed end) 1:packet continued (open start, open end) @@ -81,7 +82,7 @@ module usb_asp_ctrl_ep ( wire more_data_out; - reg [1:0] superslow; + reg [15:0] superslow; // the default control endpoint gets assigned the device address @@ -362,7 +363,7 @@ module usb_asp_ctrl_ep ( if (out_data_stage) begin send_in_buf <= 0; - out_buf_addr <= 0; + // out_buf_addr_usb <= 0; spi_length <= wLength; spi_bytes_sent <= 0; if (spi_bytes_sent != spi_length) @@ -397,34 +398,34 @@ module usb_asp_ctrl_ep ( end if ( (ctrl_xfr_state == DATA_OUT) && out_ep_data_valid && ~out_ep_setup) begin - out_buf[out_buf_addr] <= out_ep_data; - out_buf_addr <= out_buf_addr + 1; + out_buf[out_buf_addr_usb] <= out_ep_data; + out_buf_addr_usb <= out_buf_addr_usb + 1; end - //superslow <= superslow + 1; - //if (superslow == 0) + superslow <= superslow + 1; + if (superslow == 0) if (spi_bytes_sent == spi_length) begin // nothing to send if (spi_continue == 0) begin spi_clk <= 1; // clock inactive spi_csn <= 1; // disable chip - spi_bit_counter <= 15; // skip first clock cycle + spi_bit_counter <= 10; // skip first few clock cycle end end else // spi_bytes_sent != spi_length begin spi_csn <= 0; // enable chip - if(out_buf_addr != spi_bytes_sent) // more spi data + if(out_buf_addr_usb != out_buf_addr_spi) // more spi data begin if (spi_bit_counter[3]) - spi_bit_counter <= 0; // skip one cycle, flash needs small delay from csn=0 to clk + spi_bit_counter <= spi_bit_counter + 1; // skip some cycles, flash needs small delay from csn=0 to clk else // spi_bit_counter < 8 begin if (spi_clk == 1) begin // clock=0: send data to SPI chip if (spi_bit_counter[2:0] == 0) - spi_mosi_byte <= out_buf[spi_bytes_sent]; // new byte from buffer + spi_mosi_byte <= out_buf[out_buf_addr_spi]; // new byte from buffer else spi_mosi_byte <= spi_mosi_byte_next; // shift bit output to SPI chip end @@ -435,6 +436,7 @@ module usb_asp_ctrl_ep ( begin in_buf[spi_bytes_sent] <= spi_miso_byte_next; // complete byte to IN buffer, later sent spi_bytes_sent <= spi_bytes_sent + 1; + out_buf_addr_spi <= out_buf_addr_spi + 1; // catch up end spi_bit_counter[2:0] <= spi_bit_counter[2:0] + 1; end @@ -442,7 +444,7 @@ module usb_asp_ctrl_ep ( end // spi bit counter < 8 end // more_spi_data end // spi_bytes_sent != spi_length - + if (status_stage_end) begin setup_data_addr <= 0; @@ -464,7 +466,6 @@ module usb_asp_ctrl_ep ( setup_data_addr <= 0; save_dev_addr <= 0; send_in_buf <= 0; - out_buf_addr <= 0; spi_length <= 0; spi_bytes_sent <= 0; debug_led <= 0; From cc3bfd5d74d49d69f01f6175b98cd3a0fbae1149 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 21:04:10 +0200 Subject: [PATCH 35/90] circular spi buffering works at full speed --- boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v | 4 ++-- common/usb_asp_ctrl_ep.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v index f3aa79e..6b957fd 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v @@ -119,8 +119,8 @@ module bootloader_asp_ulx3s ( //////////////////////////////////////////////////////////////////////////////// assign wifi_gpio0 = btn[0]; //assign led[5] = boot; - assign led = debug_led; - // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + // assign led = debug_led; + assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; endmodule diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index a35ab1e..a7b6ed8 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -402,8 +402,8 @@ module usb_asp_ctrl_ep ( out_buf_addr_usb <= out_buf_addr_usb + 1; end - superslow <= superslow + 1; - if (superslow == 0) + //superslow <= superslow + 1; + //if (superslow == 0) if (spi_bytes_sent == spi_length) begin // nothing to send if (spi_continue == 0) From 5db407ef23d33fbd4790a0a8bb5411d19bdf6640 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 21:11:08 +0200 Subject: [PATCH 36/90] debug led counts spi overruns if SPI is currently sending buffered data, don't accept any new OUT packet (drop them if they come too fast) It didn't help much... --- .../ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v | 4 ++-- common/usb_asp_ctrl_ep.v | 10 ++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v index 6b957fd..f3aa79e 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v @@ -119,8 +119,8 @@ module bootloader_asp_ulx3s ( //////////////////////////////////////////////////////////////////////////////// assign wifi_gpio0 = btn[0]; //assign led[5] = boot; - // assign led = debug_led; - assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + assign led = debug_led; + // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; endmodule diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index a7b6ed8..5852bf7 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -362,12 +362,14 @@ module usb_asp_ctrl_ep ( end if (out_data_stage) begin - send_in_buf <= 0; - // out_buf_addr_usb <= 0; - spi_length <= wLength; - spi_bytes_sent <= 0; if (spi_bytes_sent != spi_length) debug_led <= debug_led + 1; // indicate overrun, new packet arrived before SPI finished + else + begin + send_in_buf <= 0; + spi_length <= wLength; + spi_bytes_sent <= 0; + end end end // end bRequest 0 From 0889fecd09e9674d815128e363dd5df460635e65 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 21:44:45 +0200 Subject: [PATCH 37/90] check for IN data stage when reading SPI status --- common/usb_asp_ctrl_ep.v | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index 5852bf7..c498dba 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -124,7 +124,7 @@ module usb_asp_ctrl_ep ( wire setup_pkt_start = pkt_start && out_ep_setup; - wire has_data_stage = wLength != 16'b0000000000000000; + wire has_data_stage = wLength != 0; wire out_data_stage; assign out_data_stage = has_data_stage && !bmRequestType[7]; @@ -376,13 +376,16 @@ module usb_asp_ctrl_ep ( 1: begin // read SPI state (0:free 1:busy) IN request // choose ROM location which is not likely to change // because it will send data from ROM, not buffer - send_in_buf <= 0; - if (spi_bytes_sent == spi_length) - rom_addr <= 5; // must point to 0 in ROM descriptor - else - rom_addr <= 1; // must point to 1 in ROM descriptor - rom_length <= 1; - bytes_sent <= 0; + if (in_data_stage) + begin + send_in_buf <= 0; + if (spi_bytes_sent == spi_length) + rom_addr <= 5; // must point to 0 in ROM descriptor + else + rom_addr <= 1; // must point to 1 in ROM descriptor + rom_length <= 1; + bytes_sent <= 0; + end end default begin // catch all other bRequest != 0 From 3fc933a20ecfc851146669326eda2f0f5f7b549d Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 22:40:48 +0200 Subject: [PATCH 38/90] descriptor USB version 2.0 -> 1.10 --- common/usb_asp_ctrl_ep.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index c498dba..f999e7e 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -349,7 +349,7 @@ module usb_asp_ctrl_ep ( endcase end // end 0: standard request - 2: begin // 2: vendor specific request (also would handle 1 or 3) + 2: begin // 2: vendor specific request case (bRequest) 0: begin // write or read SPI data block spi_continue <= wValue[0]; @@ -415,7 +415,7 @@ module usb_asp_ctrl_ep ( begin spi_clk <= 1; // clock inactive spi_csn <= 1; // disable chip - spi_bit_counter <= 10; // skip first few clock cycle + spi_bit_counter <= 10; // skip first few clock cycles end end else // spi_bytes_sent != spi_length @@ -482,8 +482,8 @@ module usb_asp_ctrl_ep ( wire [7:0] descriptor_rom [0:35]; assign descriptor_rom[0] = 18; // bLength assign descriptor_rom[1] = 1; // bDescriptorType - assign descriptor_rom[2] = 'h00; // bcdUSB[0] - assign descriptor_rom[3] = 'h02; // bcdUSB[1] + assign descriptor_rom[2] = 'h10; // bcdUSB[0] + assign descriptor_rom[3] = 'h01; // bcdUSB[1] assign descriptor_rom[4] = 'hFF; // bDeviceClass assign descriptor_rom[5] = 'h00; // bDeviceSubClass assign descriptor_rom[6] = 'h00; // bDeviceProtocol @@ -528,5 +528,6 @@ endmodule /* TODO [ ] duplicate packets sometimes recived (did SPI finish before new packet came') [ ] lsusb -vvv -d shows descriptor and vailts, try to dump traffic with wireshark +[ ] lsusb -vvv -d will make lisbusb fail [ ] overrun signal - problem: SPI often stalls */ From 20ada1a10d8f4f6d574208c4dfe4a9249149f4e5 Mon Sep 17 00:00:00 2001 From: Emard Date: Mon, 30 Jul 2018 23:50:11 +0200 Subject: [PATCH 39/90] cleanup from serial code, change always @* -> @(negedge clk) and it still works --- common/usb_asp_ctrl_ep.v | 45 +++++++--------------------------------- 1 file changed, 7 insertions(+), 38 deletions(-) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index f999e7e..cb31cf4 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -63,13 +63,15 @@ module usb_asp_ctrl_ep ( ///////////////////////// reg [7:0] out_buf [0:63]; // PC out transfer should be received here (64 byte max) reg [7:0] in_buf [0:31]; // PC in transfer when PC reads back buffered SPI response (32 byte max) - reg [5:0] out_buf_addr_usb = 0; // 0-32 address for the buffer - reg [5:0] out_buf_addr_spi = 0; // 0-32 address for the buffer for SPI sender + reg [5:0] out_buf_addr_usb = 0; // 0-63 address for the buffer for USB acceptor + reg [5:0] out_buf_addr_spi = 0; // 0-63 address for the buffer for SPI sender reg [5:0] spi_length = 0; // 0-32 number of bytes to be sent by OUT reg [5:0] spi_bytes_sent = 0; // 0-32 bit current number of bytes sent by OUT reg [3:0] spi_bit_counter = 10; // 0-15 reg send_in_buf = 0; reg spi_continue = 0; // 0:normal packet (reset start, closed end) 1:packet continued (open start, open end) + + reg [25:0] superslow; // so slow that LEDs are visible // help with assembling the SPI byte reg [7:0] spi_miso_byte; // host input, device output @@ -81,9 +83,6 @@ module usb_asp_ctrl_ep ( assign spi_mosi = spi_mosi_byte[7]; // output: MSB SPI bit gets shifted out first wire more_data_out; - - reg [15:0] superslow; - // the default control endpoint gets assigned the device address reg [6:0] dev_addr_i = 0; @@ -166,7 +165,7 @@ module usb_asp_ctrl_ep ( //////////////////////////////////////////////////////////////////////////////// - always @* begin + always @(negedge clk) begin setup_stage_end <= 0; data_stage_end <= 0; status_stage_end <= 0; @@ -293,7 +292,6 @@ module usb_asp_ctrl_ep ( 6 : begin // DEVICE_QUALIFIER in_ep_stall <= 1; - rom_addr <= 0; rom_length <= 0; end @@ -302,7 +300,6 @@ module usb_asp_ctrl_ep ( 'h05 : begin // SET_ADDRESS - rom_addr <= 0; rom_length <= 0; // we need to save the address after the status stage ends @@ -314,36 +311,10 @@ module usb_asp_ctrl_ep ( 'h09 : begin // SET_CONFIGURATION - rom_addr <= 0; - rom_length <= 0; - end - - 'h20 : begin - // SET_LINE_CODING - rom_addr <= 0; - rom_length <= 0; - end - - 'h21 : begin - // GET_LINE_CODING - rom_addr <= 85; - rom_length <= 7; - end - - 'h22 : begin - // SET_CONTROL_LINE_STATE - rom_addr <= 0; - rom_length <= 0; - end - - 'h23 : begin - // SEND_BREAK - rom_addr <= 0; rom_length <= 0; end default begin - rom_addr <= 0; rom_length <= 0; end endcase @@ -415,7 +386,7 @@ module usb_asp_ctrl_ep ( begin spi_clk <= 1; // clock inactive spi_csn <= 1; // disable chip - spi_bit_counter <= 10; // skip first few clock cycles + spi_bit_counter <= 12; // skip first few clock cycles end end else // spi_bytes_sent != spi_length @@ -454,7 +425,6 @@ module usb_asp_ctrl_ep ( if (status_stage_end) begin setup_data_addr <= 0; bytes_sent <= 0; - rom_addr <= 0; rom_length <= 0; if (save_dev_addr) begin @@ -465,7 +435,6 @@ module usb_asp_ctrl_ep ( if (reset) begin bytes_sent <= 0; - rom_addr <= 0; rom_length <= 0; dev_addr_i <= 0; setup_data_addr <= 0; @@ -474,7 +443,7 @@ module usb_asp_ctrl_ep ( spi_length <= 0; spi_bytes_sent <= 0; debug_led <= 0; - end + end end assign in_ep_data = (send_in_buf ? in_buf[rom_addr[4:0]] : descriptor_rom[rom_addr]); From 4afd87092fb8ab06cfc0b8ef48a815203c8f5d50 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 00:11:23 +0200 Subject: [PATCH 40/90] sample libusb application "usbasp", currently only reads flash --- usbasp/makefile | 7 + usbasp/spiflashtest.c | 299 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 306 insertions(+) create mode 100644 usbasp/makefile create mode 100644 usbasp/spiflashtest.c diff --git a/usbasp/makefile b/usbasp/makefile new file mode 100644 index 0000000..9fcba8f --- /dev/null +++ b/usbasp/makefile @@ -0,0 +1,7 @@ + + +spiflashtest: spiflashtest.c + gcc -lusb-1.0 $< -o $@ + +clean: + rm -f spiflashtest *~ diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c new file mode 100644 index 0000000..f30fb5a --- /dev/null +++ b/usbasp/spiflashtest.c @@ -0,0 +1,299 @@ + +#include + +// uint types +#include + +// memcpy +#include + +// file handling +#include +#include +#include + +// USB +#include + +static struct libusb_device_handle *device_handle = NULL; +uint8_t libusb_initialized = 0, interface_claimed = 0; + +int flash_read(uint8_t *data, size_t addr, size_t length) +{ + uint8_t buf[32]; // USB I/O buffer + size_t accumulated_read = 0; // accumulate total read + size_t payload_start = 4; // initial payload starts at byte 4 without continuation + uint8_t data1 = 0; // currently no use + uint8_t bRequest = 0; // currently no use + uint16_t wIndex = 0; // currently no use + uint16_t wValue = length <= sizeof(buf)-payload_start ? 0 : 1; // wValue: 0-no continuation, 1-continuation + uint16_t timeout_ms = 10; // 10 ms waiting for response + + buf[0] = 0x03; // FLASH normal (slow) read + buf[1] = (addr >> 16) & 0xFF; // MSB start address + buf[2] = (addr >> 8) & 0xFF; // start address + buf[3] = addr & 0xFF; // LSB start address + + while(accumulated_read < length) + { + int response; + + #if 0 + // IN request - wait for SPI to finish its transmission + buf[0] = 1; + while(buf[0] == 1) + { + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), + 1, 0, 0, buf, 1, timeout_ms); + if(buf[0]) + printf("spi busy before out %d\n", buf[0]); + } + #endif + + // write to USB read command followed with dummy bytes + // in order to read, we must first write command and the + // contiue writing anything to SPI + // every written byte will also result in reading a byte. + // up to 32 read bytes are buffered inside of the USB device. + // this USB buffer can be retrieved by subsequent IN command later. + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, sizeof(buf), timeout_ms); + if(response < 0) + { + fprintf(stderr, "OUT: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } + // calculate next request length (how much to read from USB) + size_t request_size; + if(accumulated_read + sizeof(buf) - payload_start >= length) + { + // printf("last packet\n"); + // end packet, trim request size to how much we really need + request_size = length + payload_start - accumulated_read; + wValue = 0; // terminate continuation + } + else + request_size = sizeof(buf); + + #if 0 + // IN request - wait for SPI to finish its transmission + buf[0] = 1; + while(buf[0] == 1) + { + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), + 1, 0, 0, buf, 1, timeout_ms); + if(buf[0]) + printf("spi busy before in %d\n", buf[0]); + } + #endif + + //usleep(1000000); + // usleep(11); // sleep 11us for SPI to tranfer (usually not needed) + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, request_size, timeout_ms); + if(response != request_size) + { + fprintf(stderr, "IN: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } + size_t response_size = response - payload_start; + memcpy(data, buf+payload_start, response_size); + data += response_size; + accumulated_read += response_size; + if(payload_start) // contination will result in full 32-byte payload + payload_start = 0; + } + return 0; // 0 on success +} + +// read from addr, length bytes and write to file +int read_to_file(char *filename, size_t addr, size_t length) +{ + // printf("reading\n"); + const int bufsize = 28; // not much speed improvement in increasing this + uint8_t buf[2][bufsize]; // 2 buffers, both must match + size_t accumulated_read = 0; + int file_descriptor = open(filename, O_CREAT | O_TRUNC | O_RDWR, S_IRUSR | S_IWUSR); + const int retry = 1000; + while(accumulated_read < length) + { + int match; // repeat reading until 2 subsequent readings match + int ib = 0; // buffer index 0/1 to match + size_t requested_size = accumulated_read + bufsize >= length ? length - accumulated_read : bufsize; + match = 0; + const int match_required = 2; + // printf("accumulated_read %d\n", accumulated_read); + for(int i = 0; i < retry && match < match_required; i++) + { + buf[ib][0] = ~buf[ib^1][0]; // damage first byte for the match to initially fail unless read correct + buf[ib][requested_size-1] = ~buf[ib^1][requested_size-1]; // damage first byte for the match to initially fail unless read correct + int rc = flash_read(buf[ib], addr, requested_size); + if(rc == 0 && memcmp(buf[ib], buf[ib^1], requested_size) == 0) + match++; + else + { + match = 0; + if(i > 0) + printf("read verify error %d\n", i); + } + ib ^= 1; // switch buffer + } + if(match < match_required) + { + fprintf(stderr, "failure after %d retries\n", retry); + return -1; + } + write(file_descriptor, buf[0], requested_size); + accumulated_read += requested_size; + addr += requested_size; + } + close(file_descriptor); + return 0; +} + + +static void print_devs(libusb_device **devs) +{ + libusb_device *dev; + int i = 0, j = 0; + uint8_t path[8]; + + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int r = libusb_get_device_descriptor(dev, &desc); + if (r < 0) { + fprintf(stderr, "failed to get device descriptor"); + return; + } + + printf("%04x:%04x (bus %d, device %d)", + desc.idVendor, desc.idProduct, + libusb_get_bus_number(dev), libusb_get_device_address(dev)); + + r = libusb_get_port_numbers(dev, path, sizeof(path)); + if (r > 0) { + printf(" path: %d", path[0]); + for (j = 1; j < r; j++) + printf(".%d", path[j]); + } + printf("\n"); +// if(desc.idVendor == 0x16C0 && desc.idProduct == 0x05DC) +// vendorspecific(); + } +} + +void close_usb_device(void) +{ + printf("aaaa\n"); + if(interface_claimed) + { + libusb_release_interface(device_handle, 0); + interface_claimed = 0; + } + if(libusb_initialized) + { + libusb_exit(NULL); + libusb_initialized = 0; + } +} + +int open_usb_device(uint16_t vid, uint16_t pid) +{ + int r = libusb_init(NULL); + if (r < 0) + { + fprintf(stderr, "Cannot init libusb\n"); + close_usb_device(); + return -1; + } + libusb_initialized = 1; + + device_handle = libusb_open_device_with_vid_pid(NULL, 0x16C0, 0x05DC); + if (!device_handle) + { + fprintf(stderr, "Error finding USB device\n"); + return -1; + } + +#if 1 + int rc; + rc = libusb_claim_interface(device_handle, 0); + if (rc < 0) + { + fprintf(stderr, "Error claiming interface: %s\n", libusb_error_name(rc)); + return -1; + } + interface_claimed = 1; +#endif + return 0; +} + +void print_hex_buf(uint8_t *buf, size_t len) +{ + for(int i = 0; i < len; i++) + { + if(i % 32 == 0 && i != 0) + printf("\n"); + printf("%02x ", buf[i]); + } + printf("\n"); +} + +int send_one_packet() +{ + uint8_t buf[32]; + buf[0] = 0xAB; // 1010 1011 + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + for(int i = 4; i < 32; i++) + buf[i] = 0x00; + uint16_t datalen = 32; + uint8_t data1 = 0; // currently no use + uint8_t bRequest = 0; // currently no use + uint16_t wIndex = 0; // currently no use + uint16_t wValue = 0; // wValue: 0-no continuation, 1-continuation + uint16_t timeout_ms = 100; // 10 ms waiting for response + + int response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, datalen, timeout_ms); + +#if 1 + //usleep(1000000); + + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, datalen, timeout_ms); + + print_hex_buf(buf, datalen); +#endif + return response; +} + + +int test_read(void) +{ + uint8_t buf[0x40]; // buffer 64K + + flash_read(buf, 0x300000, sizeof(buf)); // read complete buffer from flash address 0 + + // print start of the buffer + print_hex_buf(buf, sizeof(buf)); + return 0; +} + +int main(void) +{ + // vendorspecific(); + + if(open_usb_device(0x16C0, 0x05DC) < 0) + return -1; + + send_one_packet(); + send_one_packet(); + //usleep(1000000); + test_read(); + + read_to_file("/tmp/flashcontent.bin", 0, 0x400000); + + return 0; +} From f1d5265b688a7aea81b8f73d6f21bd31f8a97991 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 01:08:33 +0200 Subject: [PATCH 41/90] read flash id --- usbasp/spiflashtest.c | 44 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index f30fb5a..1411824 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -106,6 +106,8 @@ int flash_read(uint8_t *data, size_t addr, size_t length) return 0; // 0 on success } + + // read from addr, length bytes and write to file int read_to_file(char *filename, size_t addr, size_t length) { @@ -152,6 +154,36 @@ int read_to_file(char *filename, size_t addr, size_t length) } +int read_flash_id(uint8_t *id, size_t len) +{ + uint8_t buf[32]; + buf[0] = 0xAB; + buf[1] = 0x00; + buf[2] = 0x00; + buf[3] = 0x00; + for(int i = 4; i < 32; i++) + buf[i] = 0x00; + uint16_t datalen = 32; + uint8_t data1 = 0; // currently no use + uint8_t bRequest = 0; // currently no use + uint16_t wIndex = 0; // currently no use + uint16_t wValue = 0; // wValue: 0-no continuation, 1-continuation + uint16_t timeout_ms = 100; // 10 ms waiting for response + + int response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, datalen, timeout_ms); + if(response < 0) + return response; + + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, datalen, timeout_ms); + + memcpy(id, buf+4, len); // copy buffer + + return response; +} + + static void print_devs(libusb_device **devs) { libusb_device *dev; @@ -287,9 +319,15 @@ int main(void) if(open_usb_device(0x16C0, 0x05DC) < 0) return -1; - - send_one_packet(); - send_one_packet(); + + //send_one_packet(); + //send_one_packet(); + + uint8_t id[1]; + for(int i = 0; i < 3; i++) + read_flash_id(id, 1); + printf("FLASH ID: 0x%02X\n", id[0]); + //usleep(1000000); test_read(); From a0c87098bb0229ce5732c1a02d8dfe0cafd74574 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 02:20:05 +0200 Subject: [PATCH 42/90] sector erase works --- usbasp/spiflashtest.c | 152 ++++++++++++++++++++++++++++++++---------- 1 file changed, 115 insertions(+), 37 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 1411824..9118bf9 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -4,6 +4,9 @@ // uint types #include +// malloc +#include + // memcpy #include @@ -18,6 +21,15 @@ static struct libusb_device_handle *device_handle = NULL; uint8_t libusb_initialized = 0, interface_claimed = 0; + +void cmd_addr(uint8_t *buf, uint8_t cmd, uint32_t addr) +{ + buf[0] = cmd; + buf[1] = 0xFF & (addr >> 16); + buf[2] = 0xFF & (addr >> 8); + buf[3] = 0XFF & addr; +} + int flash_read(uint8_t *data, size_t addr, size_t length) { uint8_t buf[32]; // USB I/O buffer @@ -29,10 +41,7 @@ int flash_read(uint8_t *data, size_t addr, size_t length) uint16_t wValue = length <= sizeof(buf)-payload_start ? 0 : 1; // wValue: 0-no continuation, 1-continuation uint16_t timeout_ms = 10; // 10 ms waiting for response - buf[0] = 0x03; // FLASH normal (slow) read - buf[1] = (addr >> 16) & 0xFF; // MSB start address - buf[2] = (addr >> 8) & 0xFF; // start address - buf[3] = addr & 0xFF; // LSB start address + cmd_addr(buf, 0x03, addr); // FLASH normal (slow) read while(accumulated_read < length) { @@ -107,7 +116,6 @@ int flash_read(uint8_t *data, size_t addr, size_t length) } - // read from addr, length bytes and write to file int read_to_file(char *filename, size_t addr, size_t length) { @@ -153,36 +161,99 @@ int read_to_file(char *filename, size_t addr, size_t length) return 0; } - -int read_flash_id(uint8_t *id, size_t len) +// up to 32 byte single packet in/out exchange +int txrx(uint8_t *out_data, size_t out_len, uint8_t *in_data, size_t in_len) { - uint8_t buf[32]; - buf[0] = 0xAB; - buf[1] = 0x00; - buf[2] = 0x00; - buf[3] = 0x00; - for(int i = 4; i < 32; i++) - buf[i] = 0x00; - uint16_t datalen = 32; - uint8_t data1 = 0; // currently no use uint8_t bRequest = 0; // currently no use uint16_t wIndex = 0; // currently no use uint16_t wValue = 0; // wValue: 0-no continuation, 1-continuation - uint16_t timeout_ms = 100; // 10 ms waiting for response + uint16_t timeout_ms = 10; // 10 ms waiting for response + int response; - int response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR|data1), - bRequest, wValue, wIndex, buf, datalen, timeout_ms); + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR), + bRequest, wValue, wIndex, out_data, out_len, timeout_ms); if(response < 0) - return response; + { + fprintf(stderr, "txrx OUT: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } - response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR|data1), - bRequest, wValue, wIndex, buf, datalen, timeout_ms); + if(in_data == NULL || in_len == 0) + return 0; - memcpy(id, buf+4, len); // copy buffer - - return response; + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), + bRequest, wValue, wIndex, in_data, in_len, timeout_ms); + if(response < 0) + { + fprintf(stderr, "txrx IN: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } + + return 0; +} + +int flash_read_id() +{ + uint8_t buf[5]; + cmd_addr(buf, 0xAB, 0); + int rc = txrx(buf, sizeof(buf), buf, sizeof(buf)); + if(rc < 0) + return rc; + return buf[4]; +} + +int flash_read_status() +{ + uint8_t buf[2]; + buf[0] = 0x05; + int rc = txrx(buf, sizeof(buf), buf, sizeof(buf)); + if(rc < 0) + return rc; + return buf[1]; +} + +int flash_wait_while_busy() +{ + while(flash_read_status() & 1); +} + +int flash_write_enable() +{ + uint8_t buf[1]; + buf[0] = 0x06; + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return rc; + return 0; } +int flash_write_disable() +{ + uint8_t buf[1]; + buf[0] = 0x04; + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return rc; + return 0; +} + +// only 3 selected sector lengths are possible +int flash_erase_sector(size_t addr, size_t len) +{ + uint8_t opcode = 0; // null-opcode is NOP + if(len == 4*1024) opcode = 0x20; + if(len == 32*1024) opcode = 0x52; + if(len == 64*1024) opcode = 0xd8; + if(opcode == 0) + return -1; // unsupported length + flash_write_enable(); + uint8_t buf[4]; + cmd_addr(buf, opcode, addr); + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return -1; // error in txrx + flash_wait_while_busy(); +} static void print_devs(libusb_device **devs) { @@ -302,14 +373,16 @@ int send_one_packet() } -int test_read(void) +int test_read(size_t addr, size_t len) { - uint8_t buf[0x40]; // buffer 64K - - flash_read(buf, 0x300000, sizeof(buf)); // read complete buffer from flash address 0 + uint8_t *buf; // buffer 64K + buf = (uint8_t *)malloc(len); + flash_read(buf, addr, len); // read complete buffer from flash address 0 // print start of the buffer - print_hex_buf(buf, sizeof(buf)); + printf("address 0x%06X length %d\n", addr, len); + print_hex_buf(buf, len); + free(buf); return 0; } @@ -323,15 +396,20 @@ int main(void) //send_one_packet(); //send_one_packet(); - uint8_t id[1]; + uint8_t flash_id; for(int i = 0; i < 3; i++) - read_flash_id(id, 1); - printf("FLASH ID: 0x%02X\n", id[0]); - - //usleep(1000000); - test_read(); + flash_id = flash_read_id(0xAB); + printf("FLASH ID: 0x%02X\n", flash_id); + + uint8_t flash_status = flash_read_status(0x05); + printf("FLASH STATUS: 0x%02X\n", flash_status); - read_to_file("/tmp/flashcontent.bin", 0, 0x400000); + //usleep(1000000); + // test_read(0x300000); // alphabet + test_read(0x200000+64*1024-64, 128); // alphabet + // flash_erase_sector(0x200000, 64*1024); + test_read(0x200000+64*1024-64, 128); // alphabet + // read_to_file("/tmp/flashcontent.bin", 0, 0x400000); return 0; } From 32415505305a3fefab9121b75c8a2a9bb745ecf9 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 02:45:19 +0200 Subject: [PATCH 43/90] flash write --- usbasp/spiflashtest.c | 278 +++++++++++++++++++++++++++--------------- 1 file changed, 181 insertions(+), 97 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 9118bf9..1bff21c 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -30,6 +30,100 @@ void cmd_addr(uint8_t *buf, uint8_t cmd, uint32_t addr) buf[3] = 0XFF & addr; } +// up to 32 byte single packet in/out exchange +int txrx(uint8_t *out_data, size_t out_len, uint8_t *in_data, size_t in_len) +{ + uint8_t bRequest = 0; // currently no use + uint16_t wIndex = 0; // currently no use + uint16_t wValue = 0; // wValue: 0-no continuation, 1-continuation + uint16_t timeout_ms = 10; // 10 ms waiting for response + int response; + + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR), + bRequest, wValue, wIndex, out_data, out_len, timeout_ms); + if(response < 0) + { + fprintf(stderr, "txrx OUT: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } + + if(in_data == NULL || in_len == 0) + return 0; + + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), + bRequest, wValue, wIndex, in_data, in_len, timeout_ms); + if(response < 0) + { + fprintf(stderr, "txrx IN: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } + + return 0; +} + +int flash_read_id() +{ + uint8_t buf[5]; + cmd_addr(buf, 0xAB, 0); + int rc = txrx(buf, sizeof(buf), buf, sizeof(buf)); + if(rc < 0) + return rc; + return buf[4]; +} + +int flash_read_status() +{ + uint8_t buf[2]; + buf[0] = 0x05; + int rc = txrx(buf, sizeof(buf), buf, sizeof(buf)); + if(rc < 0) + return rc; + return buf[1]; +} + +int flash_wait_while_busy() +{ + while(flash_read_status() & 1); +} + +int flash_write_enable() +{ + uint8_t buf[1]; + buf[0] = 0x06; + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return rc; + return 0; +} + +int flash_write_disable() +{ + uint8_t buf[1]; + buf[0] = 0x04; + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return rc; + return 0; +} + +// only 3 selected sector lengths are possible +int flash_erase_sector(size_t addr, size_t len) +{ + uint8_t opcode = 0; // null-opcode is NOP + if(len == 4*1024) opcode = 0x20; + if(len == 32*1024) opcode = 0x52; + if(len == 64*1024) opcode = 0xd8; + if(opcode == 0) + return -1; // unsupported length + flash_write_enable(); + uint8_t buf[4]; + cmd_addr(buf, opcode, addr); + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return -1; // error in txrx + flash_wait_while_busy(); +} + int flash_read(uint8_t *data, size_t addr, size_t length) { uint8_t buf[32]; // USB I/O buffer @@ -115,6 +209,80 @@ int flash_read(uint8_t *data, size_t addr, size_t length) return 0; // 0 on success } +int flash_write(uint8_t *data, size_t addr, size_t length) +{ + uint8_t buf[32]; // USB I/O buffer + size_t accumulated_read = 0; // accumulate total read + size_t payload_start = 4; // initial payload starts at byte 4 without continuation + uint8_t data1 = 0; // currently no use + uint8_t bRequest = 0; // currently no use + uint16_t wIndex = 0; // currently no use + uint16_t wValue = length <= sizeof(buf)-payload_start ? 0 : 1; // wValue: 0-no continuation, 1-continuation + uint16_t timeout_ms = 10; // 10 ms waiting for response + + cmd_addr(buf, 0x02, addr); // FLASH write (should be previous erased to 0xFF) + + while(accumulated_read < length) + { + int response; + + #if 0 + // IN request - wait for SPI to finish its transmission + buf[0] = 1; + while(buf[0] == 1) + { + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), + 1, 0, 0, buf, 1, timeout_ms); + if(buf[0]) + printf("spi busy before out %d\n", buf[0]); + } + #endif + + // calculate next request length (how much to read from USB) + size_t request_size; + if(accumulated_read + sizeof(buf) - payload_start >= length) + { + // printf("last packet\n"); + // end packet, trim request size to how much we really need + request_size = length + payload_start - accumulated_read; + wValue = 0; // terminate continuation + } + else + request_size = sizeof(buf); + size_t response_size = sizeof(buf) - payload_start; + printf("paystart %d, response_size %d\n", payload_start, response_size); + memcpy(buf+payload_start, data, response_size); + + // write to USB the flash write command followed with data + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR|data1), + bRequest, wValue, wIndex, buf, request_size, timeout_ms); + if(response < 0) + { + fprintf(stderr, "OUT: %s\n", libusb_error_name(response)); + return -1; // something went wrong with USB + } + + #if 0 + // IN request - wait for SPI to finish its transmission + buf[0] = 1; + while(buf[0] == 1) + { + response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), + 1, 0, 0, buf, 1, timeout_ms); + if(buf[0]) + printf("spi busy before in %d\n", buf[0]); + } + #endif + + data += response_size; + accumulated_read += response_size; + if(payload_start) // contination will result in full 32-byte payload + payload_start = 0; + + } + return 0; // 0 on success +} + // read from addr, length bytes and write to file int read_to_file(char *filename, size_t addr, size_t length) @@ -161,99 +329,6 @@ int read_to_file(char *filename, size_t addr, size_t length) return 0; } -// up to 32 byte single packet in/out exchange -int txrx(uint8_t *out_data, size_t out_len, uint8_t *in_data, size_t in_len) -{ - uint8_t bRequest = 0; // currently no use - uint16_t wIndex = 0; // currently no use - uint16_t wValue = 0; // wValue: 0-no continuation, 1-continuation - uint16_t timeout_ms = 10; // 10 ms waiting for response - int response; - - response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR), - bRequest, wValue, wIndex, out_data, out_len, timeout_ms); - if(response < 0) - { - fprintf(stderr, "txrx OUT: %s\n", libusb_error_name(response)); - return -1; // something went wrong with USB - } - - if(in_data == NULL || in_len == 0) - return 0; - - response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_IN|LIBUSB_REQUEST_TYPE_VENDOR), - bRequest, wValue, wIndex, in_data, in_len, timeout_ms); - if(response < 0) - { - fprintf(stderr, "txrx IN: %s\n", libusb_error_name(response)); - return -1; // something went wrong with USB - } - - return 0; -} - -int flash_read_id() -{ - uint8_t buf[5]; - cmd_addr(buf, 0xAB, 0); - int rc = txrx(buf, sizeof(buf), buf, sizeof(buf)); - if(rc < 0) - return rc; - return buf[4]; -} - -int flash_read_status() -{ - uint8_t buf[2]; - buf[0] = 0x05; - int rc = txrx(buf, sizeof(buf), buf, sizeof(buf)); - if(rc < 0) - return rc; - return buf[1]; -} - -int flash_wait_while_busy() -{ - while(flash_read_status() & 1); -} - -int flash_write_enable() -{ - uint8_t buf[1]; - buf[0] = 0x06; - int rc = txrx(buf, sizeof(buf), NULL, 0); - if(rc < 0) - return rc; - return 0; -} - -int flash_write_disable() -{ - uint8_t buf[1]; - buf[0] = 0x04; - int rc = txrx(buf, sizeof(buf), NULL, 0); - if(rc < 0) - return rc; - return 0; -} - -// only 3 selected sector lengths are possible -int flash_erase_sector(size_t addr, size_t len) -{ - uint8_t opcode = 0; // null-opcode is NOP - if(len == 4*1024) opcode = 0x20; - if(len == 32*1024) opcode = 0x52; - if(len == 64*1024) opcode = 0xd8; - if(opcode == 0) - return -1; // unsupported length - flash_write_enable(); - uint8_t buf[4]; - cmd_addr(buf, opcode, addr); - int rc = txrx(buf, sizeof(buf), NULL, 0); - if(rc < 0) - return -1; // error in txrx - flash_wait_while_busy(); -} static void print_devs(libusb_device **devs) { @@ -376,7 +451,7 @@ int send_one_packet() int test_read(size_t addr, size_t len) { uint8_t *buf; // buffer 64K - buf = (uint8_t *)malloc(len); + buf = (uint8_t *)malloc(len * sizeof(uint8_t)); flash_read(buf, addr, len); // read complete buffer from flash address 0 // print start of the buffer @@ -406,9 +481,18 @@ int main(void) //usleep(1000000); // test_read(0x300000); // alphabet - test_read(0x200000+64*1024-64, 128); // alphabet - // flash_erase_sector(0x200000, 64*1024); - test_read(0x200000+64*1024-64, 128); // alphabet + test_read(0x200000+32*1024-64, 128); // alphabet + + //flash_erase_sector(0x200000, 64*1024); + size_t length = 100; + uint8_t *data = (uint8_t *)malloc(length * sizeof(uint8_t)); + for(int i = 0; i < length; i++) + data[i] = 0xFF & i; + //flash_write_enable(); + //flash_write(data, 0x208000, 100); + //flash_write_disable(); + free(data); + test_read(0x200000+32*1024-64, 256); // alphabet // read_to_file("/tmp/flashcontent.bin", 0, 0x400000); return 0; From 81c14d0be993ffb678ee57e061f1b7e7b897a915 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 02:50:41 +0200 Subject: [PATCH 44/90] cleanup --- usbasp/spiflashtest.c | 66 +++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 1bff21c..d021388 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -106,24 +106,6 @@ int flash_write_disable() return 0; } -// only 3 selected sector lengths are possible -int flash_erase_sector(size_t addr, size_t len) -{ - uint8_t opcode = 0; // null-opcode is NOP - if(len == 4*1024) opcode = 0x20; - if(len == 32*1024) opcode = 0x52; - if(len == 64*1024) opcode = 0xd8; - if(opcode == 0) - return -1; // unsupported length - flash_write_enable(); - uint8_t buf[4]; - cmd_addr(buf, opcode, addr); - int rc = txrx(buf, sizeof(buf), NULL, 0); - if(rc < 0) - return -1; // error in txrx - flash_wait_while_busy(); -} - int flash_read(uint8_t *data, size_t addr, size_t length) { uint8_t buf[32]; // USB I/O buffer @@ -209,10 +191,28 @@ int flash_read(uint8_t *data, size_t addr, size_t length) return 0; // 0 on success } +// only 3 selected sector lengths are possible +int flash_erase_sector(size_t addr, size_t len) +{ + uint8_t opcode = 0; // null-opcode is NOP + if(len == 4*1024) opcode = 0x20; + if(len == 32*1024) opcode = 0x52; + if(len == 64*1024) opcode = 0xd8; + if(opcode == 0) + return -1; // unsupported length + flash_write_enable(); + uint8_t buf[4]; + cmd_addr(buf, opcode, addr); + int rc = txrx(buf, sizeof(buf), NULL, 0); + if(rc < 0) + return -1; // error in txrx + flash_wait_while_busy(); +} + int flash_write(uint8_t *data, size_t addr, size_t length) { uint8_t buf[32]; // USB I/O buffer - size_t accumulated_read = 0; // accumulate total read + size_t accumulated_write = 0; // accumulate total read size_t payload_start = 4; // initial payload starts at byte 4 without continuation uint8_t data1 = 0; // currently no use uint8_t bRequest = 0; // currently no use @@ -220,9 +220,10 @@ int flash_write(uint8_t *data, size_t addr, size_t length) uint16_t wValue = length <= sizeof(buf)-payload_start ? 0 : 1; // wValue: 0-no continuation, 1-continuation uint16_t timeout_ms = 10; // 10 ms waiting for response + flash_write_enable(); + cmd_addr(buf, 0x02, addr); // FLASH write (should be previous erased to 0xFF) - - while(accumulated_read < length) + while(accumulated_write < length) { int response; @@ -240,18 +241,18 @@ int flash_write(uint8_t *data, size_t addr, size_t length) // calculate next request length (how much to read from USB) size_t request_size; - if(accumulated_read + sizeof(buf) - payload_start >= length) + if(accumulated_write + sizeof(buf) - payload_start >= length) { // printf("last packet\n"); // end packet, trim request size to how much we really need - request_size = length + payload_start - accumulated_read; + request_size = length + payload_start - accumulated_write; wValue = 0; // terminate continuation } else request_size = sizeof(buf); - size_t response_size = sizeof(buf) - payload_start; - printf("paystart %d, response_size %d\n", payload_start, response_size); - memcpy(buf+payload_start, data, response_size); + size_t payload_size = sizeof(buf) - payload_start; + // printf("paystart %d, payload_size %d\n", payload_start, payload_size); + memcpy(buf+payload_start, data, payload_size); // write to USB the flash write command followed with data response = libusb_control_transfer(device_handle, (uint8_t)(LIBUSB_ENDPOINT_OUT|LIBUSB_REQUEST_TYPE_VENDOR|data1), @@ -274,12 +275,13 @@ int flash_write(uint8_t *data, size_t addr, size_t length) } #endif - data += response_size; - accumulated_read += response_size; + data += payload_size; + accumulated_write += payload_size; if(payload_start) // contination will result in full 32-byte payload payload_start = 0; } + flash_wait_while_busy(); return 0; // 0 on success } @@ -481,18 +483,16 @@ int main(void) //usleep(1000000); // test_read(0x300000); // alphabet - test_read(0x200000+32*1024-64, 128); // alphabet + test_read(0x200000+33*1024-64, 128); // alphabet //flash_erase_sector(0x200000, 64*1024); size_t length = 100; uint8_t *data = (uint8_t *)malloc(length * sizeof(uint8_t)); for(int i = 0; i < length; i++) data[i] = 0xFF & i; - //flash_write_enable(); - //flash_write(data, 0x208000, 100); - //flash_write_disable(); + // flash_write(data, 0x200000+33*1024, 100); free(data); - test_read(0x200000+32*1024-64, 256); // alphabet + test_read(0x200000+33*1024-64, 256); // alphabet // read_to_file("/tmp/flashcontent.bin", 0, 0x400000); return 0; From 191049b7715dce5473450fd91e07787b50c2d6fe Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 10:04:07 +0200 Subject: [PATCH 45/90] simple progress bar --- usbasp/spiflashtest.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index d021388..bf93440 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -21,6 +21,18 @@ static struct libusb_device_handle *device_handle = NULL; uint8_t libusb_initialized = 0, interface_claimed = 0; +void print_progress_bar (size_t done, size_t total) +{ + const char *PBSTR = "#################################################"; + if(total == 0 || done > total) + done = total = 1; // avoid division by zero + const size_t PBWIDTH = strlen(PBSTR); + int percent = (int) (100 * done / total); + int lpad = (int) (PBWIDTH * done / total); + int rpad = PBWIDTH - lpad; + printf("\r%3d%% [%.*s%*s]", percent, lpad, PBSTR, rpad, ""); + fflush(stdout); +} void cmd_addr(uint8_t *buf, uint8_t cmd, uint32_t addr) { @@ -493,7 +505,16 @@ int main(void) // flash_write(data, 0x200000+33*1024, 100); free(data); test_read(0x200000+33*1024-64, 256); // alphabet - // read_to_file("/tmp/flashcontent.bin", 0, 0x400000); + // read_to_file("/tmp/flashcontent.bin", 0, 0x400000); + + int i, pbarmax = 300000; + for(i = 0; i < pbarmax; i += 1024) + { + print_progress_bar(i, pbarmax); + usleep(100000); + } + print_progress_bar(i, pbarmax); + printf("\n"); return 0; } From ae1eb225d8af4ec1da9d6cb05d346b33412a8b0b Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 10:15:21 +0200 Subject: [PATCH 46/90] progress bar cleanup and use for flash read to file --- usbasp/spiflashtest.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index bf93440..7c8585e 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -30,8 +30,8 @@ void print_progress_bar (size_t done, size_t total) int percent = (int) (100 * done / total); int lpad = (int) (PBWIDTH * done / total); int rpad = PBWIDTH - lpad; - printf("\r%3d%% [%.*s%*s]", percent, lpad, PBSTR, rpad, ""); - fflush(stdout); + fprintf(stderr, "\r%3d%% [%.*s%*s]", percent, lpad, PBSTR, rpad, ""); + fflush(stderr); } void cmd_addr(uint8_t *buf, uint8_t cmd, uint32_t addr) @@ -307,6 +307,7 @@ int read_to_file(char *filename, size_t addr, size_t length) size_t accumulated_read = 0; int file_descriptor = open(filename, O_CREAT | O_TRUNC | O_RDWR, S_IRUSR | S_IWUSR); const int retry = 1000; + size_t next_progress = 0, progress_step = length / 100; while(accumulated_read < length) { int match; // repeat reading until 2 subsequent readings match @@ -316,7 +317,7 @@ int read_to_file(char *filename, size_t addr, size_t length) const int match_required = 2; // printf("accumulated_read %d\n", accumulated_read); for(int i = 0; i < retry && match < match_required; i++) - { + { buf[ib][0] = ~buf[ib^1][0]; // damage first byte for the match to initially fail unless read correct buf[ib][requested_size-1] = ~buf[ib^1][requested_size-1]; // damage first byte for the match to initially fail unless read correct int rc = flash_read(buf[ib], addr, requested_size); @@ -338,7 +339,14 @@ int read_to_file(char *filename, size_t addr, size_t length) write(file_descriptor, buf[0], requested_size); accumulated_read += requested_size; addr += requested_size; + if(accumulated_read > next_progress) + { + print_progress_bar(accumulated_read, length); + next_progress += progress_step; + } } + print_progress_bar(accumulated_read, length); + fprintf(stderr, "\n"); close(file_descriptor); return 0; } @@ -505,8 +513,9 @@ int main(void) // flash_write(data, 0x200000+33*1024, 100); free(data); test_read(0x200000+33*1024-64, 256); // alphabet - // read_to_file("/tmp/flashcontent.bin", 0, 0x400000); + read_to_file("/tmp/flashcontent.bin", 0, 0x400000); +#if 0 int i, pbarmax = 300000; for(i = 0; i < pbarmax; i += 1024) { @@ -515,6 +524,6 @@ int main(void) } print_progress_bar(i, pbarmax); printf("\n"); - +#endif return 0; } From 522f788286a01ecf9d9502bf0107cac0174a2aa9 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 10:31:57 +0200 Subject: [PATCH 47/90] small todo --- common/usb_asp_ctrl_ep.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_asp_ctrl_ep.v index cb31cf4..c7cf9b8 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_asp_ctrl_ep.v @@ -499,4 +499,6 @@ endmodule [ ] lsusb -vvv -d shows descriptor and vailts, try to dump traffic with wireshark [ ] lsusb -vvv -d will make lisbusb fail [ ] overrun signal - problem: SPI often stalls +[ ] wValue OUT: append dummy bytes after end of SPI data (after last byte, add to addr) +[ ] wIndex OUT: set index to skip first N bytes for next IN */ From 242c1b815ece7de9333412b8cc6dbae83f405fba Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 12:11:19 +0200 Subject: [PATCH 48/90] erase sector size calculation --- usbasp/spiflashtest.c | 69 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 57 insertions(+), 12 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 7c8585e..f4c0676 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -299,7 +299,7 @@ int flash_write(uint8_t *data, size_t addr, size_t length) // read from addr, length bytes and write to file -int read_to_file(char *filename, size_t addr, size_t length) +int read_flash_write_file(char *filename, size_t addr, size_t length) { // printf("reading\n"); const int bufsize = 28; // not much speed improvement in increasing this @@ -352,6 +352,60 @@ int read_to_file(char *filename, size_t addr, size_t length) } +// write that many bytes found or file or if file is larger, limit by length +int read_file_write_flash(char *filename, size_t addr, size_t length) +{ + const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; + const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); + int file_descriptor = open(filename, O_RDONLY, S_IRUSR | S_IWUSR); + size_t file_length = lseek(file_descriptor, 0, SEEK_END); + lseek(file_descriptor, 0, SEEK_SET); // rewind + printf("file length %d\n", file_length); + if(file_length < length) + length = file_length; + + // **** sector logic ***** + // we need to interated over flash sectors + // if writing to partial sector we first read old data from the sector, + // erase whole sector, write from file and write old data, then verify and retry + const int retry = 10; + size_t bytes_written = 0; + int retries_remaining = retry; + + printf("writing range 0x%06X-0x%06X\n", addr, addr+length-1); + + while(bytes_written < length) + { + size_t length_remaining = length - bytes_written; + // find suitable sector to erase + // 1. priority is to minimize easeing part of data we don't have to erase + // 2. maximize sector size + size_t sector_size = available_sector_size[0]; // minimal sector size + size_t sector_part_before_data = addr % sector_size; // start as minimal sector + // find do we have any larger + for(int i = 1; i < num_available_sector_size; i++) + { + if( addr % available_sector_size[i] == sector_part_before_data // if part before is the same + && (length_remaining >= available_sector_size[i]-available_sector_size[0])) // and we have enough data + sector_size = available_sector_size[i]; // accept new sector size + } + size_t data_bytes_to_write = sector_size - sector_part_before_data; + if(bytes_written + data_bytes_to_write >= length) + data_bytes_to_write = length - bytes_written; // last sector, clamp size + size_t erase_sector_addr = addr-sector_part_before_data; + int restore_sector = addr != erase_sector_addr || erase_sector_addr+sector_size != addr+data_bytes_to_write; + printf("erase sector 0x%06X-0x%06X (size %d, restore %d) data 0x%06X-0x%06X\n", + erase_sector_addr, + erase_sector_addr+sector_size-1, + sector_size, restore_sector, + addr, addr+data_bytes_to_write-1); + + bytes_written += data_bytes_to_write; // not correct but OK for now + addr += data_bytes_to_write; + } +} + + static void print_devs(libusb_device **devs) { libusb_device *dev; @@ -513,17 +567,8 @@ int main(void) // flash_write(data, 0x200000+33*1024, 100); free(data); test_read(0x200000+33*1024-64, 256); // alphabet - read_to_file("/tmp/flashcontent.bin", 0, 0x400000); + // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); + read_file_write_flash("/tmp/flashcontent.bin", 5155, 548000); -#if 0 - int i, pbarmax = 300000; - for(i = 0; i < pbarmax; i += 1024) - { - print_progress_bar(i, pbarmax); - usleep(100000); - } - print_progress_bar(i, pbarmax); - printf("\n"); -#endif return 0; } From 45967bf28c81bcf4783d74ca5c4e99c0ecd5d267 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 12:32:05 +0200 Subject: [PATCH 49/90] calculate restore begin/end --- usbasp/spiflashtest.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index f4c0676..d81f161 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -393,12 +393,18 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) if(bytes_written + data_bytes_to_write >= length) data_bytes_to_write = length - bytes_written; // last sector, clamp size size_t erase_sector_addr = addr-sector_part_before_data; - int restore_sector = addr != erase_sector_addr || erase_sector_addr+sector_size != addr+data_bytes_to_write; - printf("erase sector 0x%06X-0x%06X (size %d, restore %d) data 0x%06X-0x%06X\n", + size_t restore_begin_len = addr - erase_sector_addr; + size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); + printf("erase sector 0x%06X-0x%06X (size %d, restore begin %d, restore end %d) data 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+sector_size-1, - sector_size, restore_sector, + sector_size, restore_begin_len, restore_end_len, addr, addr+data_bytes_to_write-1); + size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; + if(restore_begin_len > 0) + printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); + if(restore_end_len > 0) + printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; @@ -569,6 +575,7 @@ int main(void) test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); read_file_write_flash("/tmp/flashcontent.bin", 5155, 548000); + read_file_write_flash("/tmp/flashcontent.bin", 5155, 20); return 0; } From d968fcd247c0c0357f9532bfe893dcd2b7bac96b Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 13:17:56 +0200 Subject: [PATCH 50/90] programming - reading file --- usbasp/spiflashtest.c | 54 ++++++++++++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 16 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index d81f161..54baf95 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -34,6 +34,18 @@ void print_progress_bar (size_t done, size_t total) fflush(stderr); } +void print_hex_buf(uint8_t *buf, size_t len) +{ + for(int i = 0; i < len; i++) + { + if(i % 32 == 0 && i != 0) + printf("\n"); + printf("%02x ", buf[i]); + } + printf("\n"); +} + + void cmd_addr(uint8_t *buf, uint8_t cmd, uint32_t addr) { buf[0] = cmd; @@ -203,6 +215,11 @@ int flash_read(uint8_t *data, size_t addr, size_t length) return 0; // 0 on success } +// retry max "retry" times until 'match' of consecutive identical readings appear +int flash_read_retry(uint8_t *data, size_t addr, size_t length, int retry, int match) +{ +} + // only 3 selected sector lengths are possible int flash_erase_sector(size_t addr, size_t len) { @@ -355,8 +372,9 @@ int read_flash_write_file(char *filename, size_t addr, size_t length) // write that many bytes found or file or if file is larger, limit by length int read_file_write_flash(char *filename, size_t addr, size_t length) { - const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; + const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); + uint8_t sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size int file_descriptor = open(filename, O_RDONLY, S_IRUSR | S_IWUSR); size_t file_length = lseek(file_descriptor, 0, SEEK_END); lseek(file_descriptor, 0, SEEK_SET); // rewind @@ -395,20 +413,35 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) size_t erase_sector_addr = addr-sector_part_before_data; size_t restore_begin_len = addr - erase_sector_addr; size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); + size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; printf("erase sector 0x%06X-0x%06X (size %d, restore begin %d, restore end %d) data 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+sector_size-1, sector_size, restore_begin_len, restore_end_len, addr, addr+data_bytes_to_write-1); - size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; if(restore_begin_len > 0) + { printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); + // TODO read with retry-verify + flash_read(sector_buf, erase_sector_addr, restore_begin_len); + // print_hex_buf(sector_buf, restore_begin_len); + } if(restore_end_len > 0) + { printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); - + // TODO read with retry-verify + flash_read(sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); + // print_hex_buf(sector_buf+sector_size-restore_end_len, restore_end_len); + } + // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) + // read data from file and write to buffer (sector_buf + addr - erase_sector_addr, data_bytes_to_write); + read(file_descriptor, sector_buf + addr - erase_sector_addr, data_bytes_to_write); + print_hex_buf(sector_buf + addr - erase_sector_addr, 100); + // write sector with retry-verify (addr, sector_size) bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; } + printf("bytes from file %d\n", lseek(file_descriptor, 0, SEEK_CUR)); } @@ -488,17 +521,6 @@ int open_usb_device(uint16_t vid, uint16_t pid) return 0; } -void print_hex_buf(uint8_t *buf, size_t len) -{ - for(int i = 0; i < len; i++) - { - if(i % 32 == 0 && i != 0) - printf("\n"); - printf("%02x ", buf[i]); - } - printf("\n"); -} - int send_one_packet() { uint8_t buf[32]; @@ -574,8 +596,8 @@ int main(void) free(data); test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); - read_file_write_flash("/tmp/flashcontent.bin", 5155, 548000); - read_file_write_flash("/tmp/flashcontent.bin", 5155, 20); + read_file_write_flash("/tmp/flashcontent.bin", 5155, 160000); + // read_file_write_flash("/tmp/flashcontent.bin", 5155, 20); return 0; } From a581e5755c548b6ace7f3d7afd06a41bdf301a62 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 13:22:30 +0200 Subject: [PATCH 51/90] sector to write assembled, not yet erased, not yet written --- usbasp/spiflashtest.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 54baf95..57d36e6 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -424,19 +424,20 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); // TODO read with retry-verify flash_read(sector_buf, erase_sector_addr, restore_begin_len); - // print_hex_buf(sector_buf, restore_begin_len); + print_hex_buf(sector_buf, restore_begin_len); } if(restore_end_len > 0) { printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); // TODO read with retry-verify flash_read(sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); - // print_hex_buf(sector_buf+sector_size-restore_end_len, restore_end_len); + print_hex_buf(sector_buf+sector_size-restore_end_len, restore_end_len); } // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) // read data from file and write to buffer (sector_buf + addr - erase_sector_addr, data_bytes_to_write); read(file_descriptor, sector_buf + addr - erase_sector_addr, data_bytes_to_write); - print_hex_buf(sector_buf + addr - erase_sector_addr, 100); + printf("sector to write\n"); + print_hex_buf(sector_buf, sector_size); // write sector with retry-verify (addr, sector_size) bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; From 8b1bf7a572459e49a8b9a1cc2e3f1e369f2ca3ca Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 15:26:31 +0200 Subject: [PATCH 52/90] starting with mapping of sectors --- usbasp/spiflashtest.c | 51 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 57d36e6..506dc42 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -369,7 +369,14 @@ int read_flash_write_file(char *filename, size_t addr, size_t length) } + // write that many bytes found or file or if file is larger, limit by length +// construct a map of sectors, each byte represents one 4k sector +// map byte value represents erase size in KB 4,32,64 +// compare map with file data to find which sector must be erased +// sector must be erased if any bit changes from 0 to 1 set erase value to 4KB +// collect multiple 4K erase sectors into 32K or 64K + int read_file_write_flash(char *filename, size_t addr, size_t length) { const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order @@ -381,6 +388,33 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("file length %d\n", file_length); if(file_length < length) length = file_length; + size_t sector_map_len = length/available_sector_size[0]+1; // max number of sectors + uint8_t *sector_map = (uint8_t *) malloc(sector_map_len * sizeof(uint8_t)); // sector erase map + memset(sector_map, 0, sector_map_len); + size_t sector_map_base = addr - (addr % available_sector_size[0]); + printf("sector map base 0x%06X\n", sector_map_base); + print_hex_buf(sector_map, sector_map_len); + + // compare flash to file, set sector erase map + size_t accumulated_read = 0; + size_t read_addr = addr; + // calculate how much to read until next sector + size_t read_to_end_of_sector = sector_map_base + available_sector_size[0] - addr; + // printf("read_to_end_of_sector 0x%06x-0x%06x, size %d\n", addr, addr+read_to_end_of_sector-1, read_to_end_of_sector); + if(1) + while(accumulated_read < length) + { + if(accumulated_read + read_to_end_of_sector >= length) + read_to_end_of_sector = length - accumulated_read; + printf("read_to_end_of_sector 0x%06X-0x%06X, size %d\n", + read_addr, read_addr+read_to_end_of_sector-1, read_to_end_of_sector); + // determine how much bytes to read to complete current sector + // sector index to which this byte belongs + read_addr += read_to_end_of_sector; + accumulated_read += read_to_end_of_sector; + read_to_end_of_sector = available_sector_size[0]; + } + // **** sector logic ***** // we need to interated over flash sectors @@ -421,28 +455,29 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) addr, addr+data_bytes_to_write-1); if(restore_begin_len > 0) { - printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); + // printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); // TODO read with retry-verify flash_read(sector_buf, erase_sector_addr, restore_begin_len); - print_hex_buf(sector_buf, restore_begin_len); + // print_hex_buf(sector_buf, restore_begin_len); } if(restore_end_len > 0) { - printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); + // printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); // TODO read with retry-verify flash_read(sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); - print_hex_buf(sector_buf+sector_size-restore_end_len, restore_end_len); + // print_hex_buf(sector_buf+sector_size-restore_end_len, restore_end_len); } // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) // read data from file and write to buffer (sector_buf + addr - erase_sector_addr, data_bytes_to_write); read(file_descriptor, sector_buf + addr - erase_sector_addr, data_bytes_to_write); - printf("sector to write\n"); - print_hex_buf(sector_buf, sector_size); + // printf("sector to write\n"); + // print_hex_buf(sector_buf, sector_size); // write sector with retry-verify (addr, sector_size) bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; } printf("bytes from file %d\n", lseek(file_descriptor, 0, SEEK_CUR)); + free(sector_map); } @@ -597,8 +632,8 @@ int main(void) free(data); test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); - read_file_write_flash("/tmp/flashcontent.bin", 5155, 160000); - // read_file_write_flash("/tmp/flashcontent.bin", 5155, 20); + // read_file_write_flash("/tmp/flashcontent.bin", 5155, 160000); + read_file_write_flash("/tmp/flashcontent.bin", 5155, 100000); return 0; } From dd702edfbe2aa31ac7d427398c45687a922e14d7 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 31 Jul 2018 20:35:17 +0200 Subject: [PATCH 53/90] hopfully creating sector map, erase, write or leave as-is --- usbasp/spiflashtest.c | 82 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 72 insertions(+), 10 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 506dc42..ab70980 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -388,12 +388,17 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("file length %d\n", file_length); if(file_length < length) length = file_length; - size_t sector_map_len = length/available_sector_size[0]+1; // max number of sectors + int sector_map_len = length/available_sector_size[0]+1; // max number of sectors uint8_t *sector_map = (uint8_t *) malloc(sector_map_len * sizeof(uint8_t)); // sector erase map memset(sector_map, 0, sector_map_len); size_t sector_map_base = addr - (addr % available_sector_size[0]); - printf("sector map base 0x%06X\n", sector_map_base); - print_hex_buf(sector_map, sector_map_len); + // 0 - skip this sector, correct data already there + // 1 - sector doesn't have to be erased but has to be written + // 4,32,64 - sector has to be erased but not written + // 5,33,65 - sector has to be erased and written + + //printf("sector map base 0x%06X\n", sector_map_base); + //print_hex_buf(sector_map, sector_map_len); // compare flash to file, set sector erase map size_t accumulated_read = 0; @@ -401,22 +406,79 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) // calculate how much to read until next sector size_t read_to_end_of_sector = sector_map_base + available_sector_size[0] - addr; // printf("read_to_end_of_sector 0x%06x-0x%06x, size %d\n", addr, addr+read_to_end_of_sector-1, read_to_end_of_sector); + int sector_num = 0; if(1) while(accumulated_read < length) { if(accumulated_read + read_to_end_of_sector >= length) read_to_end_of_sector = length - accumulated_read; - printf("read_to_end_of_sector 0x%06X-0x%06X, size %d\n", - read_addr, read_addr+read_to_end_of_sector-1, read_to_end_of_sector); - // determine how much bytes to read to complete current sector - // sector index to which this byte belongs + printf("read_to_end_of_sector 0x%06X-0x%06X, size %d sector %d/%d\n", + read_addr, read_addr+read_to_end_of_sector-1, read_to_end_of_sector, sector_num, sector_map_len); + uint8_t *file_byte = sector_buf; + read(file_descriptor, file_byte, read_to_end_of_sector); + uint8_t *flash_byte = sector_buf+available_sector_size[0]; + flash_read(flash_byte, read_addr, read_to_end_of_sector); + for(int i = 0; i < read_to_end_of_sector; i++) // compare every byte + { + if( (*flash_byte & *file_byte) != *file_byte) + sector_map[sector_num] |= 4; // must erase 4K (will become 0xFF after erase) + if( *flash_byte != *file_byte && *file_byte != 0xFF) + sector_map[sector_num] |= 1; // must write data + flash_byte++; + file_byte++; + } read_addr += read_to_end_of_sector; accumulated_read += read_to_end_of_sector; read_to_end_of_sector = available_sector_size[0]; + sector_num++; } + lseek(file_descriptor, 0, SEEK_SET); // rewind + printf("sector map base 0x%06X\n", sector_map_base); + print_hex_buf(sector_map, sector_map_len); + // join consecutive 4K sectors into 32K or 64K + // calculate which small sector relate to larger sector boundary + size_t sector_32K_map_base = sector_map_base - (sector_map_base % available_sector_size[1]); + int first_32K_sector = (sector_32K_map_base - sector_map_base) / available_sector_size[0]; + size_t sector_64K_map_base = sector_map_base - (sector_map_base % available_sector_size[2]); + int first_64K_sector = (sector_64K_map_base - sector_map_base) / available_sector_size[0]; + printf("first 32K sector %d 0x%06X\n", first_32K_sector, sector_32K_map_base); + printf("first 64K sector %d 0x%06X\n", first_64K_sector, sector_64K_map_base); + // join 8 sectors of 4K to 1 of 32K + int num_sectors_to_join = 8; + for(int i = first_32K_sector; i < sector_map_len-num_sectors_to_join; i += num_sectors_to_join) + { + if(i >= 0) + { + int consecutive_sector_count = 0; + for(int j = 0; j < num_sectors_to_join; j++) + if((sector_map[i+j] & 4) == 4) + consecutive_sector_count++; + if(consecutive_sector_count == num_sectors_to_join) + { + sector_map[i] |= 32; // set 32K erase + for(int j = 0; j < num_sectors_to_join; j++) + sector_map[i+j] &= ~4; // remove 4K erase + } + } + } + // join 2 sectors of 32K to 1 of 64K + num_sectors_to_join = available_sector_size[2]/available_sector_size[0]; + for(int i = first_64K_sector; i < sector_map_len-num_sectors_to_join; i += num_sectors_to_join) + { + if(i >= 0) + { + if(sector_map[i] == 32 && sector_map[i+num_sectors_to_join/2] == 32) + { + sector_map[i] |= 64; // set 64K erase + sector_map[i] &= ~32; // remove 32K erase + sector_map[i+num_sectors_to_join/2] &= ~32; // remove 32K erase + } + } + } + printf("sector map base 0x%06X\n", sector_map_base); + print_hex_buf(sector_map, sector_map_len); - - // **** sector logic ***** + // **** sector logic **** // we need to interated over flash sectors // if writing to partial sector we first read old data from the sector, // erase whole sector, write from file and write old data, then verify and retry @@ -633,7 +695,7 @@ int main(void) test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); // read_file_write_flash("/tmp/flashcontent.bin", 5155, 160000); - read_file_write_flash("/tmp/flashcontent.bin", 5155, 100000); + read_file_write_flash("/tmp/flashcontent.bin", 0x100000, 500000); return 0; } From f06e8f2fd82500c4ad654193f08ce94c1da9e431 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 00:26:37 +0200 Subject: [PATCH 54/90] disable sector erase logic --- usbasp/spiflashtest.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index ab70980..289891b 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -388,6 +388,8 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("file length %d\n", file_length); if(file_length < length) length = file_length; + + #if 0 int sector_map_len = length/available_sector_size[0]+1; // max number of sectors uint8_t *sector_map = (uint8_t *) malloc(sector_map_len * sizeof(uint8_t)); // sector erase map memset(sector_map, 0, sector_map_len); @@ -477,7 +479,8 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) } printf("sector map base 0x%06X\n", sector_map_base); print_hex_buf(sector_map, sector_map_len); - + free(sector_map); + #endif // **** sector logic **** // we need to interated over flash sectors // if writing to partial sector we first read old data from the sector, @@ -497,6 +500,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) size_t sector_size = available_sector_size[0]; // minimal sector size size_t sector_part_before_data = addr % sector_size; // start as minimal sector // find do we have any larger + if(0) for(int i = 1; i < num_available_sector_size; i++) { if( addr % available_sector_size[i] == sector_part_before_data // if part before is the same @@ -539,7 +543,6 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) addr += data_bytes_to_write; } printf("bytes from file %d\n", lseek(file_descriptor, 0, SEEK_CUR)); - free(sector_map); } @@ -694,8 +697,8 @@ int main(void) free(data); test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); - // read_file_write_flash("/tmp/flashcontent.bin", 5155, 160000); - read_file_write_flash("/tmp/flashcontent.bin", 0x100000, 500000); + read_file_write_flash("/tmp/flashcontent.bin", 5155, 16000); + // read_file_write_flash("/tmp/flashcontent.bin", 0x100000, 50000); return 0; } From ead87ca202a5054e5c63cbe07312f3a4c69d6056 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 01:03:04 +0200 Subject: [PATCH 55/90] prepare for sequential file read --- usbasp/spiflashtest.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 289891b..40a420c 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -382,12 +382,16 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); uint8_t sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size - int file_descriptor = open(filename, O_RDONLY, S_IRUSR | S_IWUSR); + int file_descriptor = open(filename, O_RDONLY); + + #if 0 + // PIPE: file length is not known in advance size_t file_length = lseek(file_descriptor, 0, SEEK_END); lseek(file_descriptor, 0, SEEK_SET); // rewind printf("file length %d\n", file_length); if(file_length < length) length = file_length; + #endif #if 0 int sector_map_len = length/available_sector_size[0]+1; // max number of sectors @@ -481,6 +485,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) print_hex_buf(sector_map, sector_map_len); free(sector_map); #endif + // **** sector logic **** // we need to interated over flash sectors // if writing to partial sector we first read old data from the sector, @@ -491,7 +496,10 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("writing range 0x%06X-0x%06X\n", addr, addr+length-1); - while(bytes_written < length) + // TODO: file sequential read (from stdio) when length is not known in advance + + size_t last_read_from_file = 1; + while(bytes_written < length && last_read_from_file > 0) { size_t length_remaining = length - bytes_written; // find suitable sector to erase @@ -511,6 +519,27 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) if(bytes_written + data_bytes_to_write >= length) data_bytes_to_write = length - bytes_written; // last sector, clamp size size_t erase_sector_addr = addr-sector_part_before_data; + + // data_bytes_to_write is what we want to write, but file may contain less + // try to read from file "data_bytes_to_write" or get eof: + size_t remaining_to_read = data_bytes_to_write; + uint8_t *file_data_pointer = sector_buf + addr - erase_sector_addr; + last_read_from_file = 1; + while(remaining_to_read > 0 && last_read_from_file > 0) + { + last_read_from_file = read(file_descriptor, file_data_pointer, remaining_to_read); + if(last_read_from_file > 0) + { + remaining_to_read -= last_read_from_file; + file_data_pointer += last_read_from_file; + } + } + size_t actual_bytes_from_file = data_bytes_to_write - remaining_to_read; + printf("actual_bytes_from_file %d\n", actual_bytes_from_file); + if(last_read_from_file <= 0) + printf("****** EOF *******\n"); + // update number of bytes to write + data_bytes_to_write = actual_bytes_from_file; size_t restore_begin_len = addr - erase_sector_addr; size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; @@ -535,14 +564,13 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) } // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) // read data from file and write to buffer (sector_buf + addr - erase_sector_addr, data_bytes_to_write); - read(file_descriptor, sector_buf + addr - erase_sector_addr, data_bytes_to_write); + // size_t bytes_from_file = read(file_descriptor, sector_buf + addr - erase_sector_addr, data_bytes_to_write); // printf("sector to write\n"); // print_hex_buf(sector_buf, sector_size); // write sector with retry-verify (addr, sector_size) bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; } - printf("bytes from file %d\n", lseek(file_descriptor, 0, SEEK_CUR)); } @@ -697,8 +725,8 @@ int main(void) free(data); test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); - read_file_write_flash("/tmp/flashcontent.bin", 5155, 16000); - // read_file_write_flash("/tmp/flashcontent.bin", 0x100000, 50000); + // read_file_write_flash("/tmp/flashcontent.bin", 5155, 16000); + read_file_write_flash("/tmp/alphabet.bin", 0x300020, 50); return 0; } From 904f132b349ee6e8d3de49b5333fabf5f60d58cc Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 04:10:38 +0200 Subject: [PATCH 56/90] simplify with 4K sectors --- usbasp/spiflashtest.c | 84 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 70 insertions(+), 14 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 40a420c..619d3ed 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -130,6 +130,7 @@ int flash_write_disable() return 0; } + int flash_read(uint8_t *data, size_t addr, size_t length) { uint8_t buf[32]; // USB I/O buffer @@ -381,19 +382,25 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) { const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); - uint8_t sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size + uint8_t flash_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size + uint8_t file_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size int file_descriptor = open(filename, O_RDONLY); + if(file_descriptor < 0) + return -1; // cant't open file #if 0 + /* // PIPE: file length is not known in advance size_t file_length = lseek(file_descriptor, 0, SEEK_END); lseek(file_descriptor, 0, SEEK_SET); // rewind printf("file length %d\n", file_length); if(file_length < length) length = file_length; + */ #endif #if 0 + /* int sector_map_len = length/available_sector_size[0]+1; // max number of sectors uint8_t *sector_map = (uint8_t *) malloc(sector_map_len * sizeof(uint8_t)); // sector erase map memset(sector_map, 0, sector_map_len); @@ -420,9 +427,9 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) read_to_end_of_sector = length - accumulated_read; printf("read_to_end_of_sector 0x%06X-0x%06X, size %d sector %d/%d\n", read_addr, read_addr+read_to_end_of_sector-1, read_to_end_of_sector, sector_num, sector_map_len); - uint8_t *file_byte = sector_buf; + uint8_t *file_byte = flash_sector_buf; read(file_descriptor, file_byte, read_to_end_of_sector); - uint8_t *flash_byte = sector_buf+available_sector_size[0]; + uint8_t *flash_byte = flash_sector_buf+available_sector_size[0]; flash_read(flash_byte, read_addr, read_to_end_of_sector); for(int i = 0; i < read_to_end_of_sector; i++) // compare every byte { @@ -484,6 +491,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("sector map base 0x%06X\n", sector_map_base); print_hex_buf(sector_map, sector_map_len); free(sector_map); + */ #endif // **** sector logic **** @@ -508,7 +516,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) size_t sector_size = available_sector_size[0]; // minimal sector size size_t sector_part_before_data = addr % sector_size; // start as minimal sector // find do we have any larger - if(0) + if(0) // disabled for(int i = 1; i < num_available_sector_size; i++) { if( addr % available_sector_size[i] == sector_part_before_data // if part before is the same @@ -520,10 +528,15 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) data_bytes_to_write = length - bytes_written; // last sector, clamp size size_t erase_sector_addr = addr-sector_part_before_data; + // read sector before erase and before the file + flash_read(flash_sector_buf, erase_sector_addr, sector_size); + // copy to file sector (as file may be read in less than sector size) + memcpy(file_sector_buf, flash_sector_buf, sector_size); + // data_bytes_to_write is what we want to write, but file may contain less // try to read from file "data_bytes_to_write" or get eof: size_t remaining_to_read = data_bytes_to_write; - uint8_t *file_data_pointer = sector_buf + addr - erase_sector_addr; + uint8_t *file_data_pointer = file_sector_buf + addr - erase_sector_addr; last_read_from_file = 1; while(remaining_to_read > 0 && last_read_from_file > 0) { @@ -540,6 +553,44 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("****** EOF *******\n"); // update number of bytes to write data_bytes_to_write = actual_bytes_from_file; + + // determine do we have to 2:erase, 1:write or 0:leave the sector unmodified + // compare byte-by-byte flash_sector_buf and file_sector_buf + uint8_t must_erase = 0; + uint8_t must_write = 0; + for(size_t i = 0; i < sector_size; i++) + { + if( (flash_sector_buf[i] & file_sector_buf[i]) != file_sector_buf[i]) + must_erase = 1; + if( flash_sector_buf[i] != file_sector_buf[i] && file_sector_buf[i] != 0xFF) + must_write = 1; + } + printf("sector 0x%06X-0x%06X (size %d, erase %d, write %d)\n", + erase_sector_addr, + erase_sector_addr+sector_size-1, + sector_size, + must_erase, must_write); + if(must_erase) + flash_erase_sector(erase_sector_addr, sector_size); + if(must_write) + flash_write(file_sector_buf, erase_sector_addr, sector_size); + // verify + // read sector before erase and before the file + flash_read(flash_sector_buf, erase_sector_addr, sector_size); + printf("file sector written\n"); + print_hex_buf(file_sector_buf, 128); + printf("flash sector readback\n"); + print_hex_buf(flash_sector_buf, 128); + int verify_result = memcmp(flash_sector_buf, file_sector_buf, sector_size); + if(verify_result == 0) + printf("VERIFY OK\n"); + else + printf("VERIFY FAIL\n"); + + + + #if 0 + /* size_t restore_begin_len = addr - erase_sector_addr; size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; @@ -552,22 +603,25 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) { // printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); // TODO read with retry-verify - flash_read(sector_buf, erase_sector_addr, restore_begin_len); - // print_hex_buf(sector_buf, restore_begin_len); + // flash_read(flash_sector_buf, erase_sector_addr, restore_begin_len); + // print_hex_buf(flash_sector_buf, restore_begin_len); } if(restore_end_len > 0) { // printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); // TODO read with retry-verify - flash_read(sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); - // print_hex_buf(sector_buf+sector_size-restore_end_len, restore_end_len); + // flash_read(flash_sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); + // print_hex_buf(flash_sector_buf+sector_size-restore_end_len, restore_end_len); } // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) - // read data from file and write to buffer (sector_buf + addr - erase_sector_addr, data_bytes_to_write); - // size_t bytes_from_file = read(file_descriptor, sector_buf + addr - erase_sector_addr, data_bytes_to_write); + // read data from file and write to buffer (flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); + // size_t bytes_from_file = read(file_descriptor, flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); // printf("sector to write\n"); - // print_hex_buf(sector_buf, sector_size); + // print_hex_buf(flash_sector_buf, sector_size); // write sector with retry-verify (addr, sector_size) + */ + #endif + bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; } @@ -725,8 +779,10 @@ int main(void) free(data); test_read(0x200000+33*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); - // read_file_write_flash("/tmp/flashcontent.bin", 5155, 16000); - read_file_write_flash("/tmp/alphabet.bin", 0x300020, 50); + // read_file_write_flash("/tmp/flashcontent.bin", 0, 16000); + read_file_write_flash("/tmp/flashcontent.bin", 0x280000, 16000); + // read_file_write_flash("-", 5155, 90016000); + // read_file_write_flash("/tmp/alphabet.bin", 0x300020, 50); return 0; } From 5d678fe829557332cbfd25a0bec9b6f3d291b16d Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 04:23:00 +0200 Subject: [PATCH 57/90] erase and write commanded, but verify fail, write seems to not work --- usbasp/spiflashtest.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 619d3ed..deeba9d 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -40,7 +40,7 @@ void print_hex_buf(uint8_t *buf, size_t len) { if(i % 32 == 0 && i != 0) printf("\n"); - printf("%02x ", buf[i]); + printf("%02X ", buf[i]); } printf("\n"); } @@ -574,11 +574,11 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) flash_erase_sector(erase_sector_addr, sector_size); if(must_write) flash_write(file_sector_buf, erase_sector_addr, sector_size); + printf("file sector written\n"); + print_hex_buf(file_sector_buf, 128); // verify // read sector before erase and before the file flash_read(flash_sector_buf, erase_sector_addr, sector_size); - printf("file sector written\n"); - print_hex_buf(file_sector_buf, 128); printf("flash sector readback\n"); print_hex_buf(flash_sector_buf, 128); int verify_result = memcmp(flash_sector_buf, file_sector_buf, sector_size); @@ -768,21 +768,21 @@ int main(void) //usleep(1000000); // test_read(0x300000); // alphabet - test_read(0x200000+33*1024-64, 128); // alphabet + test_read(0x200000+2*1024-64, 128); // alphabet - //flash_erase_sector(0x200000, 64*1024); - size_t length = 100; + //flash_erase_sector(0x200000, 4*1024); + size_t length = 4096; uint8_t *data = (uint8_t *)malloc(length * sizeof(uint8_t)); for(int i = 0; i < length; i++) data[i] = 0xFF & i; - // flash_write(data, 0x200000+33*1024, 100); + //flash_write(data, 0x200000+2*1024, length); free(data); - test_read(0x200000+33*1024-64, 256); // alphabet + test_read(0x200000+2*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); // read_file_write_flash("/tmp/flashcontent.bin", 0, 16000); - read_file_write_flash("/tmp/flashcontent.bin", 0x280000, 16000); + // read_file_write_flash("/tmp/flashcontent.bin", 0x280000, 16000); // read_file_write_flash("-", 5155, 90016000); - // read_file_write_flash("/tmp/alphabet.bin", 0x300020, 50); + read_file_write_flash("/tmp/alphabet.bin", 0x200020, 50); return 0; } From fa9098db8b40c1606ff0f89d5d10f3b96f5e5048 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 13:03:07 +0200 Subject: [PATCH 58/90] write must be split into max 256 bytes, now it works --- usbasp/spiflashtest.c | 129 +++++++++++++++++++++--------------------- 1 file changed, 64 insertions(+), 65 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index deeba9d..b9ca77a 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -369,25 +369,7 @@ int read_flash_write_file(char *filename, size_t addr, size_t length) return 0; } - - -// write that many bytes found or file or if file is larger, limit by length -// construct a map of sectors, each byte represents one 4k sector -// map byte value represents erase size in KB 4,32,64 -// compare map with file data to find which sector must be erased -// sector must be erased if any bit changes from 0 to 1 set erase value to 4KB -// collect multiple 4K erase sectors into 32K or 64K - -int read_file_write_flash(char *filename, size_t addr, size_t length) -{ - const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order - const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); - uint8_t flash_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size - uint8_t file_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size - int file_descriptor = open(filename, O_RDONLY); - if(file_descriptor < 0) - return -1; // cant't open file - +/* JUNK CODE */ #if 0 /* // PIPE: file length is not known in advance @@ -494,6 +476,58 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) */ #endif + #if 0 + /* + size_t restore_begin_len = addr - erase_sector_addr; + size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); + size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; + printf("erase sector 0x%06X-0x%06X (size %d, restore begin %d, restore end %d) data 0x%06X-0x%06X\n", + erase_sector_addr, + erase_sector_addr+sector_size-1, + sector_size, restore_begin_len, restore_end_len, + addr, addr+data_bytes_to_write-1); + if(restore_begin_len > 0) + { + // printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); + // TODO read with retry-verify + // flash_read(flash_sector_buf, erase_sector_addr, restore_begin_len); + // print_hex_buf(flash_sector_buf, restore_begin_len); + } + if(restore_end_len > 0) + { + // printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); + // TODO read with retry-verify + // flash_read(flash_sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); + // print_hex_buf(flash_sector_buf+sector_size-restore_end_len, restore_end_len); + } + // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) + // read data from file and write to buffer (flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); + // size_t bytes_from_file = read(file_descriptor, flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); + // printf("sector to write\n"); + // print_hex_buf(flash_sector_buf, sector_size); + // write sector with retry-verify (addr, sector_size) + */ + #endif + + + +// write that many bytes found or file or if file is larger, limit by length +// construct a map of sectors, each byte represents one 4k sector +// map byte value represents erase size in KB 4,32,64 +// compare map with file data to find which sector must be erased +// sector must be erased if any bit changes from 0 to 1 set erase value to 4KB +// collect multiple 4K erase sectors into 32K or 64K + +int read_file_write_flash(char *filename, size_t addr, size_t length) +{ + const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order + const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); + uint8_t flash_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size + uint8_t file_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size + int file_descriptor = open(filename, O_RDONLY); + if(file_descriptor < 0) + return -1; // cant't open file + // **** sector logic **** // we need to interated over flash sectors // if writing to partial sector we first read old data from the sector, @@ -502,9 +536,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) size_t bytes_written = 0; int retries_remaining = retry; - printf("writing range 0x%06X-0x%06X\n", addr, addr+length-1); - - // TODO: file sequential read (from stdio) when length is not known in advance + printf("writing range limit 0x%06X-0x%06X\n", addr, addr+length-1); size_t last_read_from_file = 1; while(bytes_written < length && last_read_from_file > 0) @@ -572,56 +604,23 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) must_erase, must_write); if(must_erase) flash_erase_sector(erase_sector_addr, sector_size); + const size_t page_program_size = 256; // up to this bytes max in one page write operation if(must_write) - flash_write(file_sector_buf, erase_sector_addr, sector_size); - printf("file sector written\n"); - print_hex_buf(file_sector_buf, 128); + for(int i = 0; i < sector_size; i += page_program_size) + flash_write(file_sector_buf + i, erase_sector_addr + i, page_program_size); + //printf("file sector written\n"); + //print_hex_buf(file_sector_buf, sector_size); // verify // read sector before erase and before the file flash_read(flash_sector_buf, erase_sector_addr, sector_size); - printf("flash sector readback\n"); - print_hex_buf(flash_sector_buf, 128); + //printf("flash sector readback\n"); + //print_hex_buf(flash_sector_buf, sector_size); int verify_result = memcmp(flash_sector_buf, file_sector_buf, sector_size); if(verify_result == 0) printf("VERIFY OK\n"); else printf("VERIFY FAIL\n"); - - - #if 0 - /* - size_t restore_begin_len = addr - erase_sector_addr; - size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); - size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; - printf("erase sector 0x%06X-0x%06X (size %d, restore begin %d, restore end %d) data 0x%06X-0x%06X\n", - erase_sector_addr, - erase_sector_addr+sector_size-1, - sector_size, restore_begin_len, restore_end_len, - addr, addr+data_bytes_to_write-1); - if(restore_begin_len > 0) - { - // printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); - // TODO read with retry-verify - // flash_read(flash_sector_buf, erase_sector_addr, restore_begin_len); - // print_hex_buf(flash_sector_buf, restore_begin_len); - } - if(restore_end_len > 0) - { - // printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); - // TODO read with retry-verify - // flash_read(flash_sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); - // print_hex_buf(flash_sector_buf+sector_size-restore_end_len, restore_end_len); - } - // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) - // read data from file and write to buffer (flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); - // size_t bytes_from_file = read(file_descriptor, flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); - // printf("sector to write\n"); - // print_hex_buf(flash_sector_buf, sector_size); - // write sector with retry-verify (addr, sector_size) - */ - #endif - bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; } @@ -775,14 +774,14 @@ int main(void) uint8_t *data = (uint8_t *)malloc(length * sizeof(uint8_t)); for(int i = 0; i < length; i++) data[i] = 0xFF & i; - //flash_write(data, 0x200000+2*1024, length); + // flash_write(data, 0x200000+2*1024, length); free(data); test_read(0x200000+2*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); // read_file_write_flash("/tmp/flashcontent.bin", 0, 16000); - // read_file_write_flash("/tmp/flashcontent.bin", 0x280000, 16000); + read_file_write_flash("/tmp/flashcontent.bin", 0x280000, 128*1024); // read_file_write_flash("-", 5155, 90016000); - read_file_write_flash("/tmp/alphabet.bin", 0x200020, 50); + // read_file_write_flash("/tmp/alphabet.bin", 0x200000+2*1024-64, 5000); return 0; } From 0d7723f964e43a5308ebbdf185e489d041e9e335 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 13:04:32 +0200 Subject: [PATCH 59/90] cleanup (junk code deleted) --- usbasp/spiflashtest.c | 141 ------------------------------------------ 1 file changed, 141 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index b9ca77a..fe94f93 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -369,147 +369,6 @@ int read_flash_write_file(char *filename, size_t addr, size_t length) return 0; } -/* JUNK CODE */ - #if 0 - /* - // PIPE: file length is not known in advance - size_t file_length = lseek(file_descriptor, 0, SEEK_END); - lseek(file_descriptor, 0, SEEK_SET); // rewind - printf("file length %d\n", file_length); - if(file_length < length) - length = file_length; - */ - #endif - - #if 0 - /* - int sector_map_len = length/available_sector_size[0]+1; // max number of sectors - uint8_t *sector_map = (uint8_t *) malloc(sector_map_len * sizeof(uint8_t)); // sector erase map - memset(sector_map, 0, sector_map_len); - size_t sector_map_base = addr - (addr % available_sector_size[0]); - // 0 - skip this sector, correct data already there - // 1 - sector doesn't have to be erased but has to be written - // 4,32,64 - sector has to be erased but not written - // 5,33,65 - sector has to be erased and written - - //printf("sector map base 0x%06X\n", sector_map_base); - //print_hex_buf(sector_map, sector_map_len); - - // compare flash to file, set sector erase map - size_t accumulated_read = 0; - size_t read_addr = addr; - // calculate how much to read until next sector - size_t read_to_end_of_sector = sector_map_base + available_sector_size[0] - addr; - // printf("read_to_end_of_sector 0x%06x-0x%06x, size %d\n", addr, addr+read_to_end_of_sector-1, read_to_end_of_sector); - int sector_num = 0; - if(1) - while(accumulated_read < length) - { - if(accumulated_read + read_to_end_of_sector >= length) - read_to_end_of_sector = length - accumulated_read; - printf("read_to_end_of_sector 0x%06X-0x%06X, size %d sector %d/%d\n", - read_addr, read_addr+read_to_end_of_sector-1, read_to_end_of_sector, sector_num, sector_map_len); - uint8_t *file_byte = flash_sector_buf; - read(file_descriptor, file_byte, read_to_end_of_sector); - uint8_t *flash_byte = flash_sector_buf+available_sector_size[0]; - flash_read(flash_byte, read_addr, read_to_end_of_sector); - for(int i = 0; i < read_to_end_of_sector; i++) // compare every byte - { - if( (*flash_byte & *file_byte) != *file_byte) - sector_map[sector_num] |= 4; // must erase 4K (will become 0xFF after erase) - if( *flash_byte != *file_byte && *file_byte != 0xFF) - sector_map[sector_num] |= 1; // must write data - flash_byte++; - file_byte++; - } - read_addr += read_to_end_of_sector; - accumulated_read += read_to_end_of_sector; - read_to_end_of_sector = available_sector_size[0]; - sector_num++; - } - lseek(file_descriptor, 0, SEEK_SET); // rewind - printf("sector map base 0x%06X\n", sector_map_base); - print_hex_buf(sector_map, sector_map_len); - // join consecutive 4K sectors into 32K or 64K - // calculate which small sector relate to larger sector boundary - size_t sector_32K_map_base = sector_map_base - (sector_map_base % available_sector_size[1]); - int first_32K_sector = (sector_32K_map_base - sector_map_base) / available_sector_size[0]; - size_t sector_64K_map_base = sector_map_base - (sector_map_base % available_sector_size[2]); - int first_64K_sector = (sector_64K_map_base - sector_map_base) / available_sector_size[0]; - printf("first 32K sector %d 0x%06X\n", first_32K_sector, sector_32K_map_base); - printf("first 64K sector %d 0x%06X\n", first_64K_sector, sector_64K_map_base); - // join 8 sectors of 4K to 1 of 32K - int num_sectors_to_join = 8; - for(int i = first_32K_sector; i < sector_map_len-num_sectors_to_join; i += num_sectors_to_join) - { - if(i >= 0) - { - int consecutive_sector_count = 0; - for(int j = 0; j < num_sectors_to_join; j++) - if((sector_map[i+j] & 4) == 4) - consecutive_sector_count++; - if(consecutive_sector_count == num_sectors_to_join) - { - sector_map[i] |= 32; // set 32K erase - for(int j = 0; j < num_sectors_to_join; j++) - sector_map[i+j] &= ~4; // remove 4K erase - } - } - } - // join 2 sectors of 32K to 1 of 64K - num_sectors_to_join = available_sector_size[2]/available_sector_size[0]; - for(int i = first_64K_sector; i < sector_map_len-num_sectors_to_join; i += num_sectors_to_join) - { - if(i >= 0) - { - if(sector_map[i] == 32 && sector_map[i+num_sectors_to_join/2] == 32) - { - sector_map[i] |= 64; // set 64K erase - sector_map[i] &= ~32; // remove 32K erase - sector_map[i+num_sectors_to_join/2] &= ~32; // remove 32K erase - } - } - } - printf("sector map base 0x%06X\n", sector_map_base); - print_hex_buf(sector_map, sector_map_len); - free(sector_map); - */ - #endif - - #if 0 - /* - size_t restore_begin_len = addr - erase_sector_addr; - size_t restore_end_len = erase_sector_addr+sector_size - (addr+data_bytes_to_write); - size_t restore_end_addr = erase_sector_addr+sector_size-restore_end_len; - printf("erase sector 0x%06X-0x%06X (size %d, restore begin %d, restore end %d) data 0x%06X-0x%06X\n", - erase_sector_addr, - erase_sector_addr+sector_size-1, - sector_size, restore_begin_len, restore_end_len, - addr, addr+data_bytes_to_write-1); - if(restore_begin_len > 0) - { - // printf("restore begin 0x%06X-0x%06X\n", erase_sector_addr, erase_sector_addr+restore_begin_len-1); - // TODO read with retry-verify - // flash_read(flash_sector_buf, erase_sector_addr, restore_begin_len); - // print_hex_buf(flash_sector_buf, restore_begin_len); - } - if(restore_end_len > 0) - { - // printf("restore end 0x%06X-0x%06X\n", restore_end_addr, restore_end_addr+restore_end_len-1); - // TODO read with retry-verify - // flash_read(flash_sector_buf+sector_size-restore_end_len, restore_end_addr, restore_end_len); - // print_hex_buf(flash_sector_buf+sector_size-restore_end_len, restore_end_len); - } - // erase sector here (erase_sector_addr, sector_size) (verify if erased to 0xFF) - // read data from file and write to buffer (flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); - // size_t bytes_from_file = read(file_descriptor, flash_sector_buf + addr - erase_sector_addr, data_bytes_to_write); - // printf("sector to write\n"); - // print_hex_buf(flash_sector_buf, sector_size); - // write sector with retry-verify (addr, sector_size) - */ - #endif - - // write that many bytes found or file or if file is larger, limit by length // construct a map of sectors, each byte represents one 4k sector From dbd0949d45177a6870aa00eb12c6cbf2ffaf2322 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 15:16:45 +0200 Subject: [PATCH 60/90] cleanup, optional lseek to determine flash file length --- usbasp/spiflashtest.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index fe94f93..084a55d 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -376,7 +376,9 @@ int read_flash_write_file(char *filename, size_t addr, size_t length) // compare map with file data to find which sector must be erased // sector must be erased if any bit changes from 0 to 1 set erase value to 4KB // collect multiple 4K erase sectors into 32K or 64K - +// length: +// positive integer: limit flash write to max this size +// 0: try to lseek() to determine actual file length int read_file_write_flash(char *filename, size_t addr, size_t length) { const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order @@ -386,6 +388,12 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) int file_descriptor = open(filename, O_RDONLY); if(file_descriptor < 0) return -1; // cant't open file + + if(length == 0) + { + length = lseek(file_descriptor, 0, SEEK_END); + lseek(file_descriptor, 0, SEEK_SET); + } // **** sector logic **** // we need to interated over flash sectors @@ -398,7 +406,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) printf("writing range limit 0x%06X-0x%06X\n", addr, addr+length-1); size_t last_read_from_file = 1; - while(bytes_written < length && last_read_from_file > 0) + while(bytes_written < length && last_read_from_file > 0 && retries_remaining > 0) { size_t length_remaining = length - bytes_written; // find suitable sector to erase @@ -406,6 +414,9 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) // 2. maximize sector size size_t sector_size = available_sector_size[0]; // minimal sector size size_t sector_part_before_data = addr % sector_size; // start as minimal sector + + // printf("retry %d\n", retries_remaining); + retries_remaining--; // if this while does early-exit with "continue", retries will be left decremented // find do we have any larger if(0) // disabled for(int i = 1; i < num_available_sector_size; i++) @@ -439,9 +450,9 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) } } size_t actual_bytes_from_file = data_bytes_to_write - remaining_to_read; - printf("actual_bytes_from_file %d\n", actual_bytes_from_file); - if(last_read_from_file <= 0) - printf("****** EOF *******\n"); + //printf("actual_bytes_from_file %d\n", actual_bytes_from_file); + //if(last_read_from_file <= 0) + // printf("****** EOF *******\n"); // update number of bytes to write data_bytes_to_write = actual_bytes_from_file; @@ -456,6 +467,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) if( flash_sector_buf[i] != file_sector_buf[i] && file_sector_buf[i] != 0xFF) must_write = 1; } + if(0) printf("sector 0x%06X-0x%06X (size %d, erase %d, write %d)\n", erase_sector_addr, erase_sector_addr+sector_size-1, @@ -467,22 +479,19 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) if(must_write) for(int i = 0; i < sector_size; i += page_program_size) flash_write(file_sector_buf + i, erase_sector_addr + i, page_program_size); - //printf("file sector written\n"); - //print_hex_buf(file_sector_buf, sector_size); // verify - // read sector before erase and before the file flash_read(flash_sector_buf, erase_sector_addr, sector_size); - //printf("flash sector readback\n"); - //print_hex_buf(flash_sector_buf, sector_size); - int verify_result = memcmp(flash_sector_buf, file_sector_buf, sector_size); - if(verify_result == 0) - printf("VERIFY OK\n"); - else - printf("VERIFY FAIL\n"); - + int verify_fail = memcmp(flash_sector_buf, file_sector_buf, sector_size); + if(verify_fail) + continue; // jumps to new while iteration without update of addr and bytes written bytes_written += data_bytes_to_write; // not correct but OK for now addr += data_bytes_to_write; + print_progress_bar(bytes_written, length); + retries_remaining = retry; // if we get this far, we are successful and set retry counter } + printf("\n"); // after progress bar to new line + if(retries_remaining == 0) + printf("FAIL\n"); } @@ -638,7 +647,7 @@ int main(void) test_read(0x200000+2*1024-64, 256); // alphabet // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); // read_file_write_flash("/tmp/flashcontent.bin", 0, 16000); - read_file_write_flash("/tmp/flashcontent.bin", 0x280000, 128*1024); + read_file_write_flash("/tmp/f32c.bit", 0x200000, 0); // read_file_write_flash("-", 5155, 90016000); // read_file_write_flash("/tmp/alphabet.bin", 0x200000+2*1024-64, 5000); From e98a19f1924100c4adebcc4a9a58f266eb5d1078 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 15:17:15 +0200 Subject: [PATCH 61/90] enable all warnings - see stuff to be cleaned --- usbasp/makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usbasp/makefile b/usbasp/makefile index 9fcba8f..52e3b8f 100644 --- a/usbasp/makefile +++ b/usbasp/makefile @@ -1,7 +1,7 @@ spiflashtest: spiflashtest.c - gcc -lusb-1.0 $< -o $@ + gcc -lusb-1.0 -Wall $< -o $@ clean: rm -f spiflashtest *~ From 0f759a2bb942903669bb5a9dbf844f1a9b838aed Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 1 Aug 2018 15:40:53 +0200 Subject: [PATCH 62/90] clenup, flashed bitstreams work todo: more cleanup, cmdline parser --- usbasp/spiflashtest.c | 126 ++++++++++++++++-------------------------- 1 file changed, 49 insertions(+), 77 deletions(-) diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 084a55d..5c538dc 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -21,12 +21,12 @@ static struct libusb_device_handle *device_handle = NULL; uint8_t libusb_initialized = 0, interface_claimed = 0; -void print_progress_bar (size_t done, size_t total) +void print_progress_bar (uint32_t done, uint32_t total) { const char *PBSTR = "#################################################"; if(total == 0 || done > total) done = total = 1; // avoid division by zero - const size_t PBWIDTH = strlen(PBSTR); + const uint32_t PBWIDTH = strlen(PBSTR); int percent = (int) (100 * done / total); int lpad = (int) (PBWIDTH * done / total); int rpad = PBWIDTH - lpad; @@ -34,7 +34,7 @@ void print_progress_bar (size_t done, size_t total) fflush(stderr); } -void print_hex_buf(uint8_t *buf, size_t len) +void print_hex_buf(uint8_t *buf, uint32_t len) { for(int i = 0; i < len; i++) { @@ -55,7 +55,7 @@ void cmd_addr(uint8_t *buf, uint8_t cmd, uint32_t addr) } // up to 32 byte single packet in/out exchange -int txrx(uint8_t *out_data, size_t out_len, uint8_t *in_data, size_t in_len) +int txrx(uint8_t *out_data, uint32_t out_len, uint8_t *in_data, uint32_t in_len) { uint8_t bRequest = 0; // currently no use uint16_t wIndex = 0; // currently no use @@ -108,6 +108,7 @@ int flash_read_status() int flash_wait_while_busy() { while(flash_read_status() & 1); + return 0; } int flash_write_enable() @@ -131,11 +132,11 @@ int flash_write_disable() } -int flash_read(uint8_t *data, size_t addr, size_t length) +int flash_read(uint8_t *data, uint32_t addr, uint32_t length) { uint8_t buf[32]; // USB I/O buffer - size_t accumulated_read = 0; // accumulate total read - size_t payload_start = 4; // initial payload starts at byte 4 without continuation + uint32_t accumulated_read = 0; // accumulate total read + uint32_t payload_start = 4; // initial payload starts at byte 4 without continuation uint8_t data1 = 0; // currently no use uint8_t bRequest = 0; // currently no use uint16_t wIndex = 0; // currently no use @@ -174,7 +175,7 @@ int flash_read(uint8_t *data, size_t addr, size_t length) return -1; // something went wrong with USB } // calculate next request length (how much to read from USB) - size_t request_size; + uint32_t request_size; if(accumulated_read + sizeof(buf) - payload_start >= length) { // printf("last packet\n"); @@ -206,7 +207,7 @@ int flash_read(uint8_t *data, size_t addr, size_t length) fprintf(stderr, "IN: %s\n", libusb_error_name(response)); return -1; // something went wrong with USB } - size_t response_size = response - payload_start; + uint32_t response_size = response - payload_start; memcpy(data, buf+payload_start, response_size); data += response_size; accumulated_read += response_size; @@ -217,12 +218,12 @@ int flash_read(uint8_t *data, size_t addr, size_t length) } // retry max "retry" times until 'match' of consecutive identical readings appear -int flash_read_retry(uint8_t *data, size_t addr, size_t length, int retry, int match) +int flash_read_retry(uint8_t *data, uint32_t addr, uint32_t length, int retry, int match) { } // only 3 selected sector lengths are possible -int flash_erase_sector(size_t addr, size_t len) +int flash_erase_sector(uint32_t addr, uint32_t len) { uint8_t opcode = 0; // null-opcode is NOP if(len == 4*1024) opcode = 0x20; @@ -237,13 +238,14 @@ int flash_erase_sector(size_t addr, size_t len) if(rc < 0) return -1; // error in txrx flash_wait_while_busy(); + return 0; } -int flash_write(uint8_t *data, size_t addr, size_t length) +int flash_write(uint8_t *data, uint32_t addr, uint32_t length) { uint8_t buf[32]; // USB I/O buffer - size_t accumulated_write = 0; // accumulate total read - size_t payload_start = 4; // initial payload starts at byte 4 without continuation + uint32_t accumulated_write = 0; // accumulate total read + uint32_t payload_start = 4; // initial payload starts at byte 4 without continuation uint8_t data1 = 0; // currently no use uint8_t bRequest = 0; // currently no use uint16_t wIndex = 0; // currently no use @@ -270,7 +272,7 @@ int flash_write(uint8_t *data, size_t addr, size_t length) #endif // calculate next request length (how much to read from USB) - size_t request_size; + uint32_t request_size; if(accumulated_write + sizeof(buf) - payload_start >= length) { // printf("last packet\n"); @@ -280,7 +282,7 @@ int flash_write(uint8_t *data, size_t addr, size_t length) } else request_size = sizeof(buf); - size_t payload_size = sizeof(buf) - payload_start; + uint32_t payload_size = sizeof(buf) - payload_start; // printf("paystart %d, payload_size %d\n", payload_start, payload_size); memcpy(buf+payload_start, data, payload_size); @@ -317,20 +319,20 @@ int flash_write(uint8_t *data, size_t addr, size_t length) // read from addr, length bytes and write to file -int read_flash_write_file(char *filename, size_t addr, size_t length) +int read_flash_write_file(char *filename, uint32_t addr, uint32_t length) { // printf("reading\n"); const int bufsize = 28; // not much speed improvement in increasing this uint8_t buf[2][bufsize]; // 2 buffers, both must match - size_t accumulated_read = 0; + uint32_t accumulated_read = 0; int file_descriptor = open(filename, O_CREAT | O_TRUNC | O_RDWR, S_IRUSR | S_IWUSR); const int retry = 1000; - size_t next_progress = 0, progress_step = length / 100; + uint32_t next_progress = 0, progress_step = length / 100; while(accumulated_read < length) { int match; // repeat reading until 2 subsequent readings match int ib = 0; // buffer index 0/1 to match - size_t requested_size = accumulated_read + bufsize >= length ? length - accumulated_read : bufsize; + uint32_t requested_size = accumulated_read + bufsize >= length ? length - accumulated_read : bufsize; match = 0; const int match_required = 2; // printf("accumulated_read %d\n", accumulated_read); @@ -379,9 +381,9 @@ int read_flash_write_file(char *filename, size_t addr, size_t length) // length: // positive integer: limit flash write to max this size // 0: try to lseek() to determine actual file length -int read_file_write_flash(char *filename, size_t addr, size_t length) +int read_file_write_flash(char *filename, uint32_t addr, uint32_t length) { - const size_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order + const uint32_t available_sector_size[] = {4*1024, 32*1024, 64*1024}; // sizes in ascending order const int num_available_sector_size = sizeof(available_sector_size)/sizeof(available_sector_size[0]); uint8_t flash_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size uint8_t file_sector_buf[available_sector_size[num_available_sector_size-1]]; // allocate buf, max sector size @@ -400,20 +402,20 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) // if writing to partial sector we first read old data from the sector, // erase whole sector, write from file and write old data, then verify and retry const int retry = 10; - size_t bytes_written = 0; + uint32_t bytes_written = 0; int retries_remaining = retry; - printf("writing range limit 0x%06X-0x%06X\n", addr, addr+length-1); + printf("writing range 0x%06X-0x%06X\n", addr, addr+length-1); - size_t last_read_from_file = 1; + uint32_t last_read_from_file = 1; while(bytes_written < length && last_read_from_file > 0 && retries_remaining > 0) { - size_t length_remaining = length - bytes_written; + uint32_t length_remaining = length - bytes_written; // find suitable sector to erase // 1. priority is to minimize easeing part of data we don't have to erase // 2. maximize sector size - size_t sector_size = available_sector_size[0]; // minimal sector size - size_t sector_part_before_data = addr % sector_size; // start as minimal sector + uint32_t sector_size = available_sector_size[0]; // minimal sector size + uint32_t sector_part_before_data = addr % sector_size; // start as minimal sector // printf("retry %d\n", retries_remaining); retries_remaining--; // if this while does early-exit with "continue", retries will be left decremented @@ -425,10 +427,10 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) && (length_remaining >= available_sector_size[i]-available_sector_size[0])) // and we have enough data sector_size = available_sector_size[i]; // accept new sector size } - size_t data_bytes_to_write = sector_size - sector_part_before_data; + uint32_t data_bytes_to_write = sector_size - sector_part_before_data; if(bytes_written + data_bytes_to_write >= length) data_bytes_to_write = length - bytes_written; // last sector, clamp size - size_t erase_sector_addr = addr-sector_part_before_data; + uint32_t erase_sector_addr = addr-sector_part_before_data; // read sector before erase and before the file flash_read(flash_sector_buf, erase_sector_addr, sector_size); @@ -437,7 +439,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) // data_bytes_to_write is what we want to write, but file may contain less // try to read from file "data_bytes_to_write" or get eof: - size_t remaining_to_read = data_bytes_to_write; + uint32_t remaining_to_read = data_bytes_to_write; uint8_t *file_data_pointer = file_sector_buf + addr - erase_sector_addr; last_read_from_file = 1; while(remaining_to_read > 0 && last_read_from_file > 0) @@ -449,7 +451,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) file_data_pointer += last_read_from_file; } } - size_t actual_bytes_from_file = data_bytes_to_write - remaining_to_read; + uint32_t actual_bytes_from_file = data_bytes_to_write - remaining_to_read; //printf("actual_bytes_from_file %d\n", actual_bytes_from_file); //if(last_read_from_file <= 0) // printf("****** EOF *******\n"); @@ -460,7 +462,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) // compare byte-by-byte flash_sector_buf and file_sector_buf uint8_t must_erase = 0; uint8_t must_write = 0; - for(size_t i = 0; i < sector_size; i++) + for(uint32_t i = 0; i < sector_size; i++) { if( (flash_sector_buf[i] & file_sector_buf[i]) != file_sector_buf[i]) must_erase = 1; @@ -475,7 +477,7 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) must_erase, must_write); if(must_erase) flash_erase_sector(erase_sector_addr, sector_size); - const size_t page_program_size = 256; // up to this bytes max in one page write operation + const uint32_t page_program_size = 256; // up to this bytes max in one page write operation if(must_write) for(int i = 0; i < sector_size; i += page_program_size) flash_write(file_sector_buf + i, erase_sector_addr + i, page_program_size); @@ -491,40 +493,15 @@ int read_file_write_flash(char *filename, size_t addr, size_t length) } printf("\n"); // after progress bar to new line if(retries_remaining == 0) - printf("FAIL\n"); + { + fprintf(stderr, "FAIL\n"); + return -1; + } + printf("last read from file: %d bytes\n", last_read_from_file); + return 0; } -static void print_devs(libusb_device **devs) -{ - libusb_device *dev; - int i = 0, j = 0; - uint8_t path[8]; - - while ((dev = devs[i++]) != NULL) { - struct libusb_device_descriptor desc; - int r = libusb_get_device_descriptor(dev, &desc); - if (r < 0) { - fprintf(stderr, "failed to get device descriptor"); - return; - } - - printf("%04x:%04x (bus %d, device %d)", - desc.idVendor, desc.idProduct, - libusb_get_bus_number(dev), libusb_get_device_address(dev)); - - r = libusb_get_port_numbers(dev, path, sizeof(path)); - if (r > 0) { - printf(" path: %d", path[0]); - for (j = 1; j < r; j++) - printf(".%d", path[j]); - } - printf("\n"); -// if(desc.idVendor == 0x16C0 && desc.idProduct == 0x05DC) -// vendorspecific(); - } -} - void close_usb_device(void) { printf("aaaa\n"); @@ -602,7 +579,7 @@ int send_one_packet() } -int test_read(size_t addr, size_t len) +int test_read(uint32_t addr, uint32_t len) { uint8_t *buf; // buffer 64K buf = (uint8_t *)malloc(len * sizeof(uint8_t)); @@ -617,18 +594,12 @@ int test_read(size_t addr, size_t len) int main(void) { - // vendorspecific(); - if(open_usb_device(0x16C0, 0x05DC) < 0) return -1; - //send_one_packet(); - //send_one_packet(); + printf("FLASH ID: 0x%02X\n", flash_read_id()); - uint8_t flash_id; - for(int i = 0; i < 3; i++) - flash_id = flash_read_id(0xAB); - printf("FLASH ID: 0x%02X\n", flash_id); + #if 0 uint8_t flash_status = flash_read_status(0x05); printf("FLASH STATUS: 0x%02X\n", flash_status); @@ -638,18 +609,19 @@ int main(void) test_read(0x200000+2*1024-64, 128); // alphabet //flash_erase_sector(0x200000, 4*1024); - size_t length = 4096; + uint32_t length = 4096; uint8_t *data = (uint8_t *)malloc(length * sizeof(uint8_t)); for(int i = 0; i < length; i++) data[i] = 0xFF & i; // flash_write(data, 0x200000+2*1024, length); free(data); test_read(0x200000+2*1024-64, 256); // alphabet + #endif + // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); // read_file_write_flash("/tmp/flashcontent.bin", 0, 16000); read_file_write_flash("/tmp/f32c.bit", 0x200000, 0); - // read_file_write_flash("-", 5155, 90016000); - // read_file_write_flash("/tmp/alphabet.bin", 0x200000+2*1024-64, 5000); + // read_file_write_flash("/tmp/oled-example.bit", 0x200000, 0); return 0; } From a11d81bcb3de49b402a887ee7d91501113c1a909 Mon Sep 17 00:00:00 2001 From: Emard Date: Thu, 2 Aug 2018 03:21:20 +0200 Subject: [PATCH 63/90] fixed file redaing with retry logic, sector is read only first retry. Any subsequent retry uses already buffered data, no reading from file again. cmdline.ggo with some todo-options, compiles but currently unused --- usbasp/cmdline.ggo | 15 ++++++++++ usbasp/makefile | 24 +++++++++++++-- usbasp/spiflashtest.c | 68 ++++++++++++++++++++++++++++--------------- usbasp/version.sh | 2 ++ 4 files changed, 83 insertions(+), 26 deletions(-) create mode 100644 usbasp/cmdline.ggo create mode 100755 usbasp/version.sh diff --git a/usbasp/cmdline.ggo b/usbasp/cmdline.ggo new file mode 100644 index 0000000..7239604 --- /dev/null +++ b/usbasp/cmdline.ggo @@ -0,0 +1,15 @@ +# file cmdline.ggo + +# Name of your program +package "fpgasp" # don't use package if you're using automake +# Version of your program +version "0.1.0" # don't use version if you're using automake + +purpose "Flasher for tinyfpga bootloader with USB vendor-specific support" + +# long short description type default required +option "address" a "starting flash address" int default="0x200000" no +option "read" r "read from flash write to file" string default="read.bit" no +option "write" w "read from file write to flash" string default="write.bit" no +option "verbose" v "Print extra info (0-no|1-some|2-much)" int default="0" no +option "device" d "usb device hex vid:pid" string default="16c0:05dc" no diff --git a/usbasp/makefile b/usbasp/makefile index 52e3b8f..c7ffe6e 100644 --- a/usbasp/makefile +++ b/usbasp/makefile @@ -1,7 +1,25 @@ +CFLAGS=-Wall -s -Os +CLIBS=-lusb-1.0 +project=spiflashtest +parser=cmdline +version=$(shell ./version.sh) -spiflashtest: spiflashtest.c - gcc -lusb-1.0 -Wall $< -o $@ +OBJECTS=$(project).o $(parser).o + +all: $(project) + +$(project).o: $(project).c $(parser).h + gcc -c $(CFLAGS) $< + +$(parser).c: $(parser).ggo makefile + gengetopt < $< --file-name=$(parser) # --unamed-opts + +$(parser).h: $(parser).ggo makefile + gengetopt < $< --file-name=$(parser) # --unamed-opts + +$(project): $(OBJECTS) makefile + gcc $(CFLAGS) $(CLIBS) $(OBJECTS) -o $@ clean: - rm -f spiflashtest *~ + rm -f $(project) $(OBJECTS) $(parser).o $(parser).c $(parser).h *~ diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 5c538dc..008c736 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -18,6 +18,12 @@ // USB #include +// commandline parser cmdline.ggo with gengetpot +#include "cmdline.h" + +struct gengetopt_args_info args_info; +struct gengetopt_args_info *args = &args_info; + static struct libusb_device_handle *device_handle = NULL; uint8_t libusb_initialized = 0, interface_claimed = 0; @@ -406,6 +412,8 @@ int read_file_write_flash(char *filename, uint32_t addr, uint32_t length) int retries_remaining = retry; printf("writing range 0x%06X-0x%06X\n", addr, addr+length-1); + // some simple satistics about flash wear + uint32_t count_erase = 0, count_write = 0; uint32_t last_read_from_file = 1; while(bytes_written < length && last_read_from_file > 0 && retries_remaining > 0) @@ -417,10 +425,8 @@ int read_file_write_flash(char *filename, uint32_t addr, uint32_t length) uint32_t sector_size = available_sector_size[0]; // minimal sector size uint32_t sector_part_before_data = addr % sector_size; // start as minimal sector - // printf("retry %d\n", retries_remaining); - retries_remaining--; // if this while does early-exit with "continue", retries will be left decremented - // find do we have any larger - if(0) // disabled + // find do we have any larger sector + if(0) // disabled, the smalles 4K sector is most suitable for retry procedure for(int i = 1; i < num_available_sector_size; i++) { if( addr % available_sector_size[i] == sector_part_before_data // if part before is the same @@ -432,31 +438,39 @@ int read_file_write_flash(char *filename, uint32_t addr, uint32_t length) data_bytes_to_write = length - bytes_written; // last sector, clamp size uint32_t erase_sector_addr = addr-sector_part_before_data; - // read sector before erase and before the file - flash_read(flash_sector_buf, erase_sector_addr, sector_size); - // copy to file sector (as file may be read in less than sector size) - memcpy(file_sector_buf, flash_sector_buf, sector_size); - - // data_bytes_to_write is what we want to write, but file may contain less - // try to read from file "data_bytes_to_write" or get eof: - uint32_t remaining_to_read = data_bytes_to_write; - uint8_t *file_data_pointer = file_sector_buf + addr - erase_sector_addr; - last_read_from_file = 1; - while(remaining_to_read > 0 && last_read_from_file > 0) - { - last_read_from_file = read(file_descriptor, file_data_pointer, remaining_to_read); - if(last_read_from_file > 0) + uint32_t actual_bytes_from_file = 0; + if(retries_remaining == retry) + { // first retry, it's new sector we need to read flash and file + // read sector before erase and before the file + flash_read(flash_sector_buf, erase_sector_addr, sector_size); + // copy to file sector (as file may be read in less than sector size) + memcpy(file_sector_buf, flash_sector_buf, sector_size); + // data_bytes_to_write is what we want to write, but file may contain less + // try to read from file "data_bytes_to_write" or get eof: + uint32_t remaining_to_read = data_bytes_to_write; + uint8_t *file_data_pointer = file_sector_buf + addr - erase_sector_addr; + last_read_from_file = 1; + while(remaining_to_read > 0 && last_read_from_file > 0) { - remaining_to_read -= last_read_from_file; - file_data_pointer += last_read_from_file; + last_read_from_file = read(file_descriptor, file_data_pointer, remaining_to_read); + if(last_read_from_file > 0) + { + remaining_to_read -= last_read_from_file; + file_data_pointer += last_read_from_file; + } } + actual_bytes_from_file = data_bytes_to_write - remaining_to_read; } - uint32_t actual_bytes_from_file = data_bytes_to_write - remaining_to_read; //printf("actual_bytes_from_file %d\n", actual_bytes_from_file); //if(last_read_from_file <= 0) // printf("****** EOF *******\n"); // update number of bytes to write data_bytes_to_write = actual_bytes_from_file; + + // printf("retry %d\n", retries_remaining); + retries_remaining--; + // this while loop may be early relooped after this point + // with "continue" -> retries will be left decremented // determine do we have to 2:erase, 1:write or 0:leave the sector unmodified // compare byte-by-byte flash_sector_buf and file_sector_buf @@ -476,11 +490,17 @@ int read_file_write_flash(char *filename, uint32_t addr, uint32_t length) sector_size, must_erase, must_write); if(must_erase) + { flash_erase_sector(erase_sector_addr, sector_size); + count_erase++; + } const uint32_t page_program_size = 256; // up to this bytes max in one page write operation if(must_write) + { for(int i = 0; i < sector_size; i += page_program_size) flash_write(file_sector_buf + i, erase_sector_addr + i, page_program_size); + count_write++; + } // verify flash_read(flash_sector_buf, erase_sector_addr, sector_size); int verify_fail = memcmp(flash_sector_buf, file_sector_buf, sector_size); @@ -497,7 +517,7 @@ int read_file_write_flash(char *filename, uint32_t addr, uint32_t length) fprintf(stderr, "FAIL\n"); return -1; } - printf("last read from file: %d bytes\n", last_read_from_file); + printf("4K sectors erased:%d written:%d\n", count_erase, count_write); return 0; } @@ -592,8 +612,10 @@ int test_read(uint32_t addr, uint32_t len) return 0; } -int main(void) +int main(int argc, char **argv) { + cmdline_parser(argc, argv, args); + if(open_usb_device(0x16C0, 0x05DC) < 0) return -1; diff --git a/usbasp/version.sh b/usbasp/version.sh new file mode 100755 index 0000000..d1dacdb --- /dev/null +++ b/usbasp/version.sh @@ -0,0 +1,2 @@ +#/!bin/sh +grep "version" cmdline.ggo | sed -e 's/.*"\(.*\)".*/\1/' From da8c0c2903ba5b0111f5c3438bae53bedbdfd114 Mon Sep 17 00:00:00 2001 From: Emard Date: Thu, 2 Aug 2018 21:17:17 +0200 Subject: [PATCH 64/90] basic command line options --- usbasp/cmdline.ggo | 11 ++++++----- usbasp/spiflashtest.c | 10 +++++----- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/usbasp/cmdline.ggo b/usbasp/cmdline.ggo index 7239604..9e8e894 100644 --- a/usbasp/cmdline.ggo +++ b/usbasp/cmdline.ggo @@ -8,8 +8,9 @@ version "0.1.0" # don't use version if you're using automake purpose "Flasher for tinyfpga bootloader with USB vendor-specific support" # long short description type default required -option "address" a "starting flash address" int default="0x200000" no -option "read" r "read from flash write to file" string default="read.bit" no -option "write" w "read from file write to flash" string default="write.bit" no -option "verbose" v "Print extra info (0-no|1-some|2-much)" int default="0" no -option "device" d "usb device hex vid:pid" string default="16c0:05dc" no +option "address" a "byte Start Address" int default="0x200000" no +option "length" l "byte Length" int default="0" no +option "read" r "filename Flash -> File" string default="read.bit" no +option "write" w "filename File -> Flash" string default="write.bit" no +# option "verbose" v "Print extra info (0-no|1-some|2-much)" int default="0" no +# option "device" d "VID:PID of USB device" string default="16c0:05dc" no diff --git a/usbasp/spiflashtest.c b/usbasp/spiflashtest.c index 008c736..5d48d90 100644 --- a/usbasp/spiflashtest.c +++ b/usbasp/spiflashtest.c @@ -618,7 +618,7 @@ int main(int argc, char **argv) if(open_usb_device(0x16C0, 0x05DC) < 0) return -1; - + printf("FLASH ID: 0x%02X\n", flash_read_id()); #if 0 @@ -640,10 +640,10 @@ int main(int argc, char **argv) test_read(0x200000+2*1024-64, 256); // alphabet #endif - // read_flash_write_file("/tmp/flashcontent.bin", 0, 0x400000); - // read_file_write_flash("/tmp/flashcontent.bin", 0, 16000); - read_file_write_flash("/tmp/f32c.bit", 0x200000, 0); - // read_file_write_flash("/tmp/oled-example.bit", 0x200000, 0); + if(args->read_given) + read_flash_write_file(args->read_arg, args->address_arg, args->length_arg); + if(args->write_given) + read_file_write_flash(args->write_arg, args->address_arg, 0); return 0; } From b708ac7b4267b8e904006cf4097bbbad855d5376 Mon Sep 17 00:00:00 2001 From: Emard Date: Fri, 3 Aug 2018 16:07:03 +0200 Subject: [PATCH 65/90] renamed to tinyfpgasp --- .../Makefile | 0 .../bootloader.ldf | 10 +++++----- .../clocks/clk_200M_48M.v | 0 .../clocks/clk_25M_200M.v | 0 .../constraints/ulx3s_v17patch.lpf | 0 .../initialize/boardmeta4MB.bin | 0 .../initialize/boardmeta8MB.bin | 0 .../initialize/initialize4MB.sh | 0 .../initialize/initialize8MB.sh | 0 .../initialize/jump.bin | Bin .../initialize/jump.py | 0 .../tinyfpga_45k.bit | 0 .../tinyfpga_45k_multiboot_flash_micron_32mbit.svf | 0 .../tinyfpga_45k_multiboot_flash_micron_32mbit.vme | 0 ...tinyfpga_45k_multiboot_flash_spansion_64mbit.svf | 0 ...tinyfpga_45k_multiboot_flash_spansion_64mbit.vme | 0 .../tinyfpga_45k_sram.svf | 0 .../tinyfpga_45k_sram.vme | 0 .../top/bootloader_sp_ulx3s.v} | 4 ++-- .../ulx3s_45f_flash_micron_32mbit.xcf | 0 .../ulx3s_45f_flash_spansion_64mbit.xcf | 0 .../ulx3s_45f_multiboot_micron_32mbit.xcf | 0 .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 0 .../ulx3s_45f_sram.xcf | 0 .../{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/Makefile | 0 .../bootloader.ldf | 0 .../clocks/clk_200M_48M.v | 0 .../clocks/clk_25M_200M.v | 0 .../constraints/ulx3s_v17patch.lpf | 0 .../initialize/boardmeta4MB.bin | 0 .../initialize/boardmeta8MB.bin | 0 .../initialize/initialize4MB.sh | 0 .../initialize/initialize8MB.sh | 0 .../initialize/jump.py | 0 .../tinyfpga_45k.bit | 0 .../tinyfpga_45k_multiboot_flash_micron_32mbit.svf | 0 .../tinyfpga_45k_multiboot_flash_micron_32mbit.vme | 0 ...tinyfpga_45k_multiboot_flash_spansion_64mbit.svf | 0 ...tinyfpga_45k_multiboot_flash_spansion_64mbit.vme | 0 .../tinyfpga_45k_sram.svf | 0 .../tinyfpga_45k_sram.vme | 0 .../top/bootloader_ulx3s.v | 0 .../ulx3s_45f_flash_micron_32mbit.xcf | 0 .../ulx3s_45f_flash_spansion_64mbit.xcf | 0 .../ulx3s_45f_multiboot_micron_32mbit.xcf | 0 .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 0 .../ulx3s_45f_sram.xcf | 0 ...{usbasp_bootloader.v => tinyfpgasp_bootloader.v} | 4 ++-- common/{usb_asp_ctrl_ep.v => usb_sp_ctrl_ep.v} | 2 +- {usbasp => programmer/tinyfpgasp}/cmdline.ggo | 0 {usbasp => programmer/tinyfpgasp}/makefile | 2 +- .../tinyfpgasp/tinyfpgasp.c | 0 {usbasp => programmer/tinyfpgasp}/version.sh | 0 53 files changed, 11 insertions(+), 11 deletions(-) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/Makefile (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/bootloader.ldf (84%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/clocks/clk_200M_48M.v (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/clocks/clk_25M_200M.v (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/constraints/ulx3s_v17patch.lpf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/initialize/boardmeta4MB.bin (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/initialize/boardmeta8MB.bin (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/initialize/initialize4MB.sh (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/initialize/initialize8MB.sh (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/initialize/jump.bin (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/initialize/jump.py (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k.bit (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k_multiboot_flash_micron_32mbit.svf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k_multiboot_flash_micron_32mbit.vme (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k_sram.svf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/tinyfpga_45k_sram.vme (100%) rename boards/{ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v => ulx3s-v1.7-45f-asp/top/bootloader_sp_ulx3s.v} (94%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/ulx3s_45f_flash_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/ulx3s_45f_flash_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/ulx3s_45f_multiboot_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/ulx3s_45f_multiboot_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-usbasp => ulx3s-v1.7-45f-asp}/ulx3s_45f_sram.xcf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/Makefile (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/bootloader.ldf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/clocks/clk_200M_48M.v (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/clocks/clk_25M_200M.v (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/constraints/ulx3s_v17patch.lpf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/initialize/boardmeta4MB.bin (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/initialize/boardmeta8MB.bin (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/initialize/initialize4MB.sh (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/initialize/initialize8MB.sh (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/initialize/jump.py (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k.bit (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k_multiboot_flash_micron_32mbit.svf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k_multiboot_flash_micron_32mbit.vme (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k_sram.svf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/tinyfpga_45k_sram.vme (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/top/bootloader_ulx3s.v (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/ulx3s_45f_flash_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/ulx3s_45f_flash_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/ulx3s_45f_multiboot_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/ulx3s_45f_multiboot_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f => ulx3s-v1.7-45f-sp}/ulx3s_45f_sram.xcf (100%) rename common/{usbasp_bootloader.v => tinyfpgasp_bootloader.v} (95%) rename common/{usb_asp_ctrl_ep.v => usb_sp_ctrl_ep.v} (96%) rename {usbasp => programmer/tinyfpgasp}/cmdline.ggo (100%) rename {usbasp => programmer/tinyfpgasp}/makefile (96%) rename usbasp/spiflashtest.c => programmer/tinyfpgasp/tinyfpgasp.c (100%) rename {usbasp => programmer/tinyfpgasp}/version.sh (100%) diff --git a/boards/ulx3s-v1.7-45f-usbasp/Makefile b/boards/ulx3s-v1.7-45f-asp/Makefile similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/Makefile rename to boards/ulx3s-v1.7-45f-asp/Makefile diff --git a/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf b/boards/ulx3s-v1.7-45f-asp/bootloader.ldf similarity index 84% rename from boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf rename to boards/ulx3s-v1.7-45f-asp/bootloader.ldf index b94bc9d..6467f47 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/bootloader.ldf +++ b/boards/ulx3s-v1.7-45f-asp/bootloader.ldf @@ -2,9 +2,9 @@ - - - + + + @@ -15,7 +15,7 @@ - + @@ -48,7 +48,7 @@ - + diff --git a/boards/ulx3s-v1.7-45f-usbasp/clocks/clk_200M_48M.v b/boards/ulx3s-v1.7-45f-asp/clocks/clk_200M_48M.v similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/clocks/clk_200M_48M.v rename to boards/ulx3s-v1.7-45f-asp/clocks/clk_200M_48M.v diff --git a/boards/ulx3s-v1.7-45f-usbasp/clocks/clk_25M_200M.v b/boards/ulx3s-v1.7-45f-asp/clocks/clk_25M_200M.v similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/clocks/clk_25M_200M.v rename to boards/ulx3s-v1.7-45f-asp/clocks/clk_25M_200M.v diff --git a/boards/ulx3s-v1.7-45f-usbasp/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v1.7-45f-asp/constraints/ulx3s_v17patch.lpf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/constraints/ulx3s_v17patch.lpf rename to boards/ulx3s-v1.7-45f-asp/constraints/ulx3s_v17patch.lpf diff --git a/boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta4MB.bin b/boards/ulx3s-v1.7-45f-asp/initialize/boardmeta4MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta4MB.bin rename to boards/ulx3s-v1.7-45f-asp/initialize/boardmeta4MB.bin diff --git a/boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta8MB.bin b/boards/ulx3s-v1.7-45f-asp/initialize/boardmeta8MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/initialize/boardmeta8MB.bin rename to boards/ulx3s-v1.7-45f-asp/initialize/boardmeta8MB.bin diff --git a/boards/ulx3s-v1.7-45f-usbasp/initialize/initialize4MB.sh b/boards/ulx3s-v1.7-45f-asp/initialize/initialize4MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/initialize/initialize4MB.sh rename to boards/ulx3s-v1.7-45f-asp/initialize/initialize4MB.sh diff --git a/boards/ulx3s-v1.7-45f-usbasp/initialize/initialize8MB.sh b/boards/ulx3s-v1.7-45f-asp/initialize/initialize8MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/initialize/initialize8MB.sh rename to boards/ulx3s-v1.7-45f-asp/initialize/initialize8MB.sh diff --git a/boards/ulx3s-v1.7-45f-usbasp/initialize/jump.bin b/boards/ulx3s-v1.7-45f-asp/initialize/jump.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/initialize/jump.bin rename to boards/ulx3s-v1.7-45f-asp/initialize/jump.bin diff --git a/boards/ulx3s-v1.7-45f-usbasp/initialize/jump.py b/boards/ulx3s-v1.7-45f-asp/initialize/jump.py similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/initialize/jump.py rename to boards/ulx3s-v1.7-45f-asp/initialize/jump.py diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k.bit b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k.bit similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k.bit rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k.bit diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.svf b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.svf rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.svf diff --git a/boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.vme b/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/tinyfpga_45k_sram.vme rename to boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.vme diff --git a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v b/boards/ulx3s-v1.7-45f-asp/top/bootloader_sp_ulx3s.v similarity index 94% rename from boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v rename to boards/ulx3s-v1.7-45f-asp/top/bootloader_sp_ulx3s.v index f3aa79e..08fa8f0 100644 --- a/boards/ulx3s-v1.7-45f-usbasp/top/bootloader_asp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-asp/top/bootloader_sp_ulx3s.v @@ -1,4 +1,4 @@ -module bootloader_asp_ulx3s ( +module bootloader_sp_ulx3s ( input clk_25mhz, inout usb_fpga_dp, @@ -57,7 +57,7 @@ module bootloader_asp_ulx3s ( wire S_flash_clk; wire S_flash_csn; - usbasp_bootloader usbasp_bootloader_inst ( + tinyfpgasp_bootloader tinyfpgasp_bootloader_inst ( .clk_48mhz(clk_48mhz), .reset(reset), .usb_p_tx(usb_p_tx), diff --git a/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_flash_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_multiboot_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_sram.xcf b/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_sram.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-usbasp/ulx3s_45f_sram.xcf rename to boards/ulx3s-v1.7-45f-asp/ulx3s_45f_sram.xcf diff --git a/boards/ulx3s-v1.7-45f/Makefile b/boards/ulx3s-v1.7-45f-sp/Makefile similarity index 100% rename from boards/ulx3s-v1.7-45f/Makefile rename to boards/ulx3s-v1.7-45f-sp/Makefile diff --git a/boards/ulx3s-v1.7-45f/bootloader.ldf b/boards/ulx3s-v1.7-45f-sp/bootloader.ldf similarity index 100% rename from boards/ulx3s-v1.7-45f/bootloader.ldf rename to boards/ulx3s-v1.7-45f-sp/bootloader.ldf diff --git a/boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v b/boards/ulx3s-v1.7-45f-sp/clocks/clk_200M_48M.v similarity index 100% rename from boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v rename to boards/ulx3s-v1.7-45f-sp/clocks/clk_200M_48M.v diff --git a/boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v b/boards/ulx3s-v1.7-45f-sp/clocks/clk_25M_200M.v similarity index 100% rename from boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v rename to boards/ulx3s-v1.7-45f-sp/clocks/clk_25M_200M.v diff --git a/boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v1.7-45f-sp/constraints/ulx3s_v17patch.lpf similarity index 100% rename from boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf rename to boards/ulx3s-v1.7-45f-sp/constraints/ulx3s_v17patch.lpf diff --git a/boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin b/boards/ulx3s-v1.7-45f-sp/initialize/boardmeta4MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin rename to boards/ulx3s-v1.7-45f-sp/initialize/boardmeta4MB.bin diff --git a/boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin b/boards/ulx3s-v1.7-45f-sp/initialize/boardmeta8MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin rename to boards/ulx3s-v1.7-45f-sp/initialize/boardmeta8MB.bin diff --git a/boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh b/boards/ulx3s-v1.7-45f-sp/initialize/initialize4MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh rename to boards/ulx3s-v1.7-45f-sp/initialize/initialize4MB.sh diff --git a/boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh b/boards/ulx3s-v1.7-45f-sp/initialize/initialize8MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh rename to boards/ulx3s-v1.7-45f-sp/initialize/initialize8MB.sh diff --git a/boards/ulx3s-v1.7-45f/initialize/jump.py b/boards/ulx3s-v1.7-45f-sp/initialize/jump.py similarity index 100% rename from boards/ulx3s-v1.7-45f/initialize/jump.py rename to boards/ulx3s-v1.7-45f-sp/initialize/jump.py diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k.bit b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k.bit similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k.bit rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k.bit diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_sram.svf similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_sram.svf diff --git a/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme b/boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_sram.vme similarity index 100% rename from boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme rename to boards/ulx3s-v1.7-45f-sp/tinyfpga_45k_sram.vme diff --git a/boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v b/boards/ulx3s-v1.7-45f-sp/top/bootloader_ulx3s.v similarity index 100% rename from boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v rename to boards/ulx3s-v1.7-45f-sp/top/bootloader_ulx3s.v diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_sram.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf rename to boards/ulx3s-v1.7-45f-sp/ulx3s_45f_sram.xcf diff --git a/common/usbasp_bootloader.v b/common/tinyfpgasp_bootloader.v similarity index 95% rename from common/usbasp_bootloader.v rename to common/tinyfpgasp_bootloader.v index 3c0e887..0c836d9 100644 --- a/common/usbasp_bootloader.v +++ b/common/tinyfpgasp_bootloader.v @@ -1,4 +1,4 @@ -module usbasp_bootloader ( +module tinyfpgasp_bootloader ( input clk_48mhz, input reset, @@ -137,7 +137,7 @@ module usbasp_bootloader ( wire boot_to_user_design; assign boot = host_presence_timeout || boot_to_user_design; - usb_asp_ctrl_ep ctrl_ep_inst ( + usb_sp_ctrl_ep ctrl_ep_inst ( .clk(clk_48mhz), .reset(reset), .dev_addr(dev_addr), diff --git a/common/usb_asp_ctrl_ep.v b/common/usb_sp_ctrl_ep.v similarity index 96% rename from common/usb_asp_ctrl_ep.v rename to common/usb_sp_ctrl_ep.v index c7cf9b8..eae1933 100644 --- a/common/usb_asp_ctrl_ep.v +++ b/common/usb_sp_ctrl_ep.v @@ -1,4 +1,4 @@ -module usb_asp_ctrl_ep ( +module usb_sp_ctrl_ep ( input clk, input reset, output [6:0] dev_addr, diff --git a/usbasp/cmdline.ggo b/programmer/tinyfpgasp/cmdline.ggo similarity index 100% rename from usbasp/cmdline.ggo rename to programmer/tinyfpgasp/cmdline.ggo diff --git a/usbasp/makefile b/programmer/tinyfpgasp/makefile similarity index 96% rename from usbasp/makefile rename to programmer/tinyfpgasp/makefile index c7ffe6e..57a59f0 100644 --- a/usbasp/makefile +++ b/programmer/tinyfpgasp/makefile @@ -1,7 +1,7 @@ CFLAGS=-Wall -s -Os CLIBS=-lusb-1.0 -project=spiflashtest +project=tinyfpgasp parser=cmdline version=$(shell ./version.sh) diff --git a/usbasp/spiflashtest.c b/programmer/tinyfpgasp/tinyfpgasp.c similarity index 100% rename from usbasp/spiflashtest.c rename to programmer/tinyfpgasp/tinyfpgasp.c diff --git a/usbasp/version.sh b/programmer/tinyfpgasp/version.sh similarity index 100% rename from usbasp/version.sh rename to programmer/tinyfpgasp/version.sh From 57bc2f940f93d743360d3bc0e3cb8dfd80d6d2a5 Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 4 Aug 2018 01:15:46 +0200 Subject: [PATCH 66/90] renaming mistake fixed --- boards/ulx3s-v1.7-45f-sp/bootloader.ldf | 18 ++++++------------ .../initialize/jump.bin | Bin .../top/bootloader_sp_ulx3s.v | 0 .../Makefile | 0 .../bootloader.ldf | 18 ++++++++++++------ .../clocks/clk_200M_48M.v | 0 .../clocks/clk_25M_200M.v | 0 .../constraints/ulx3s_v17patch.lpf | 0 .../initialize/boardmeta4MB.bin | 0 .../initialize/boardmeta8MB.bin | 0 .../initialize/initialize4MB.sh | 0 .../initialize/initialize8MB.sh | 0 .../initialize/jump.py | 0 .../tinyfpga_45k.bit | 0 ...fpga_45k_multiboot_flash_micron_32mbit.svf | 0 ...fpga_45k_multiboot_flash_micron_32mbit.vme | 0 ...ga_45k_multiboot_flash_spansion_64mbit.svf | 0 ...ga_45k_multiboot_flash_spansion_64mbit.vme | 0 .../tinyfpga_45k_sram.svf | 0 .../tinyfpga_45k_sram.vme | 0 .../top/bootloader_ulx3s.v | 0 .../ulx3s_45f_flash_micron_32mbit.xcf | 0 .../ulx3s_45f_flash_spansion_64mbit.xcf | 0 .../ulx3s_45f_multiboot_micron_32mbit.xcf | 0 .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 0 .../ulx3s_45f_sram.xcf | 0 26 files changed, 18 insertions(+), 18 deletions(-) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f-sp}/initialize/jump.bin (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f-sp}/top/bootloader_sp_ulx3s.v (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/Makefile (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/bootloader.ldf (76%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/clocks/clk_200M_48M.v (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/clocks/clk_25M_200M.v (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/constraints/ulx3s_v17patch.lpf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/initialize/boardmeta4MB.bin (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/initialize/boardmeta8MB.bin (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/initialize/initialize4MB.sh (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/initialize/initialize8MB.sh (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/initialize/jump.py (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k.bit (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k_multiboot_flash_micron_32mbit.svf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k_multiboot_flash_micron_32mbit.vme (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k_sram.svf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/tinyfpga_45k_sram.vme (100%) rename boards/{ulx3s-v1.7-45f-sp => ulx3s-v1.7-45f}/top/bootloader_ulx3s.v (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/ulx3s_45f_flash_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/ulx3s_45f_flash_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/ulx3s_45f_multiboot_micron_32mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/ulx3s_45f_multiboot_spansion_64mbit.xcf (100%) rename boards/{ulx3s-v1.7-45f-asp => ulx3s-v1.7-45f}/ulx3s_45f_sram.xcf (100%) diff --git a/boards/ulx3s-v1.7-45f-sp/bootloader.ldf b/boards/ulx3s-v1.7-45f-sp/bootloader.ldf index b725c28..6467f47 100644 --- a/boards/ulx3s-v1.7-45f-sp/bootloader.ldf +++ b/boards/ulx3s-v1.7-45f-sp/bootloader.ldf @@ -2,9 +2,9 @@ - - - + + + @@ -15,13 +15,10 @@ - - - - + - + @@ -51,10 +48,7 @@ - - - - + diff --git a/boards/ulx3s-v1.7-45f-asp/initialize/jump.bin b/boards/ulx3s-v1.7-45f-sp/initialize/jump.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/initialize/jump.bin rename to boards/ulx3s-v1.7-45f-sp/initialize/jump.bin diff --git a/boards/ulx3s-v1.7-45f-asp/top/bootloader_sp_ulx3s.v b/boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/top/bootloader_sp_ulx3s.v rename to boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v diff --git a/boards/ulx3s-v1.7-45f-asp/Makefile b/boards/ulx3s-v1.7-45f/Makefile similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/Makefile rename to boards/ulx3s-v1.7-45f/Makefile diff --git a/boards/ulx3s-v1.7-45f-asp/bootloader.ldf b/boards/ulx3s-v1.7-45f/bootloader.ldf similarity index 76% rename from boards/ulx3s-v1.7-45f-asp/bootloader.ldf rename to boards/ulx3s-v1.7-45f/bootloader.ldf index 6467f47..b725c28 100644 --- a/boards/ulx3s-v1.7-45f-asp/bootloader.ldf +++ b/boards/ulx3s-v1.7-45f/bootloader.ldf @@ -2,9 +2,9 @@ - - - + + + @@ -15,10 +15,13 @@ - + - + + + + @@ -48,7 +51,10 @@ - + + + + diff --git a/boards/ulx3s-v1.7-45f-asp/clocks/clk_200M_48M.v b/boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/clocks/clk_200M_48M.v rename to boards/ulx3s-v1.7-45f/clocks/clk_200M_48M.v diff --git a/boards/ulx3s-v1.7-45f-asp/clocks/clk_25M_200M.v b/boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/clocks/clk_25M_200M.v rename to boards/ulx3s-v1.7-45f/clocks/clk_25M_200M.v diff --git a/boards/ulx3s-v1.7-45f-asp/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/constraints/ulx3s_v17patch.lpf rename to boards/ulx3s-v1.7-45f/constraints/ulx3s_v17patch.lpf diff --git a/boards/ulx3s-v1.7-45f-asp/initialize/boardmeta4MB.bin b/boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/initialize/boardmeta4MB.bin rename to boards/ulx3s-v1.7-45f/initialize/boardmeta4MB.bin diff --git a/boards/ulx3s-v1.7-45f-asp/initialize/boardmeta8MB.bin b/boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/initialize/boardmeta8MB.bin rename to boards/ulx3s-v1.7-45f/initialize/boardmeta8MB.bin diff --git a/boards/ulx3s-v1.7-45f-asp/initialize/initialize4MB.sh b/boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/initialize/initialize4MB.sh rename to boards/ulx3s-v1.7-45f/initialize/initialize4MB.sh diff --git a/boards/ulx3s-v1.7-45f-asp/initialize/initialize8MB.sh b/boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/initialize/initialize8MB.sh rename to boards/ulx3s-v1.7-45f/initialize/initialize8MB.sh diff --git a/boards/ulx3s-v1.7-45f-asp/initialize/jump.py b/boards/ulx3s-v1.7-45f/initialize/jump.py similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/initialize/jump.py rename to boards/ulx3s-v1.7-45f/initialize/jump.py diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k.bit b/boards/ulx3s-v1.7-45f/tinyfpga_45k.bit similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k.bit rename to boards/ulx3s-v1.7-45f/tinyfpga_45k.bit diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf rename to boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.svf diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme rename to boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_micron_32mbit.vme diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf rename to boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme rename to boards/ulx3s-v1.7-45f/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.svf b/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.svf rename to boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.svf diff --git a/boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.vme b/boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/tinyfpga_45k_sram.vme rename to boards/ulx3s-v1.7-45f/tinyfpga_45k_sram.vme diff --git a/boards/ulx3s-v1.7-45f-sp/top/bootloader_ulx3s.v b/boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v similarity index 100% rename from boards/ulx3s-v1.7-45f-sp/top/bootloader_ulx3s.v rename to boards/ulx3s-v1.7-45f/top/bootloader_ulx3s.v diff --git a/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f/ulx3s_45f_flash_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/ulx3s_45f_flash_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f/ulx3s_45f_flash_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_micron_32mbit.xcf rename to boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_micron_32mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/ulx3s_45f_multiboot_spansion_64mbit.xcf rename to boards/ulx3s-v1.7-45f/ulx3s_45f_multiboot_spansion_64mbit.xcf diff --git a/boards/ulx3s-v1.7-45f-asp/ulx3s_45f_sram.xcf b/boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf similarity index 100% rename from boards/ulx3s-v1.7-45f-asp/ulx3s_45f_sram.xcf rename to boards/ulx3s-v1.7-45f/ulx3s_45f_sram.xcf From df99232778230410c0bad2a5a5f67049430fd64e Mon Sep 17 00:00:00 2001 From: Emard Date: Sat, 4 Aug 2018 01:16:22 +0200 Subject: [PATCH 67/90] cmdline takes device=vid:pid argument --- programmer/tinyfpgasp/cmdline.ggo | 10 +++++----- programmer/tinyfpgasp/tinyfpgasp.c | 9 ++++++--- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/programmer/tinyfpgasp/cmdline.ggo b/programmer/tinyfpgasp/cmdline.ggo index 9e8e894..55a0ad5 100644 --- a/programmer/tinyfpgasp/cmdline.ggo +++ b/programmer/tinyfpgasp/cmdline.ggo @@ -8,9 +8,9 @@ version "0.1.0" # don't use version if you're using automake purpose "Flasher for tinyfpga bootloader with USB vendor-specific support" # long short description type default required -option "address" a "byte Start Address" int default="0x200000" no -option "length" l "byte Length" int default="0" no -option "read" r "filename Flash -> File" string default="read.bit" no -option "write" w "filename File -> Flash" string default="write.bit" no +option "address" a "Byte Start Address" int default="0x200000" no +option "length" l "Bytes Length" int default="0" no +option "read" r "Filename Flash -> File" string default="read.bit" no +option "write" w "Filename File -> Flash" string default="write.bit" no +option "device" d "VID:PID of USB device" string default="16c0:05dc" no # option "verbose" v "Print extra info (0-no|1-some|2-much)" int default="0" no -# option "device" d "VID:PID of USB device" string default="16c0:05dc" no diff --git a/programmer/tinyfpgasp/tinyfpgasp.c b/programmer/tinyfpgasp/tinyfpgasp.c index 5d48d90..dc2a83f 100644 --- a/programmer/tinyfpgasp/tinyfpgasp.c +++ b/programmer/tinyfpgasp/tinyfpgasp.c @@ -548,10 +548,10 @@ int open_usb_device(uint16_t vid, uint16_t pid) } libusb_initialized = 1; - device_handle = libusb_open_device_with_vid_pid(NULL, 0x16C0, 0x05DC); + device_handle = libusb_open_device_with_vid_pid(NULL, vid, pid); if (!device_handle) { - fprintf(stderr, "Error finding USB device\n"); + fprintf(stderr, "Error finding USB device %04X:%04X\n", vid, pid); return -1; } @@ -615,8 +615,11 @@ int test_read(uint32_t addr, uint32_t len) int main(int argc, char **argv) { cmdline_parser(argc, argv, args); + uint32_t usb_vid, usb_pid; + + sscanf(args->device_arg, "%x:%x", &usb_vid, &usb_pid); - if(open_usb_device(0x16C0, 0x05DC) < 0) + if(open_usb_device(usb_vid, usb_pid) < 0) return -1; printf("FLASH ID: 0x%02X\n", flash_read_id()); From 1c1c6a607fe76e3e956885e7eb56fdcf501ec587 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 26 Aug 2018 15:54:59 +0200 Subject: [PATCH 68/90] tinyfpgasp 85k bitstreams --- boards/ulx3s-v2.0-85f-sp/Makefile | 143 ++++++ boards/ulx3s-v2.0-85f-sp/bootloader.ldf | 56 +++ .../ulx3s-v2.0-85f-sp/clocks/clk_200M_48M.v | 75 +++ .../ulx3s-v2.0-85f-sp/clocks/clk_25M_200M.v | 75 +++ .../constraints/ulx3s_v17patch.lpf | 435 +++++++++++++++++ .../constraints/ulx3s_v20.lpf | 452 ++++++++++++++++++ boards/ulx3s-v2.0-85f-sp/ecp5-12f.ocd | 16 + boards/ulx3s-v2.0-85f-sp/ft2232-fpu1.ocd | 9 + .../initialize/boardmeta4MB.bin | 119 +++++ .../initialize/boardmeta8MB.bin | 58 +++ .../initialize/initialize4MB.sh | 30 ++ .../initialize/initialize8MB.sh | 31 ++ boards/ulx3s-v2.0-85f-sp/initialize/jump.bin | Bin 0 -> 50 bytes boards/ulx3s-v2.0-85f-sp/initialize/jump.py | 95 ++++ boards/ulx3s-v2.0-85f-sp/tinyfpga_85k.bit | 1 + ...pga_85k_multiboot_flash_micron_128mbit.svf | 1 + ...pga_85k_multiboot_flash_micron_128mbit.vme | 1 + ...fpga_85k_multiboot_flash_micron_32mbit.svf | 1 + ...fpga_85k_multiboot_flash_micron_32mbit.vme | 1 + ...ga_85k_multiboot_flash_spansion_64mbit.svf | 1 + ...ga_85k_multiboot_flash_spansion_64mbit.vme | 1 + .../ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.svf | 1 + .../ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.vme | 1 + .../top/bootloader_sp_ulx3s.v | 137 ++++++ .../ulx3s_85f_multiboot_micron_128mbit.xcf | 104 ++++ .../ulx3s_85f_multiboot_micron_32mbit.xcf | 104 ++++ .../ulx3s_85f_multiboot_spansion_64mbit.xcf | 104 ++++ boards/ulx3s-v2.0-85f-sp/ulx3s_85f_sram.xcf | 48 ++ 28 files changed, 2100 insertions(+) create mode 100644 boards/ulx3s-v2.0-85f-sp/Makefile create mode 100644 boards/ulx3s-v2.0-85f-sp/bootloader.ldf create mode 100644 boards/ulx3s-v2.0-85f-sp/clocks/clk_200M_48M.v create mode 100644 boards/ulx3s-v2.0-85f-sp/clocks/clk_25M_200M.v create mode 100644 boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v17patch.lpf create mode 100644 boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v20.lpf create mode 100644 boards/ulx3s-v2.0-85f-sp/ecp5-12f.ocd create mode 100644 boards/ulx3s-v2.0-85f-sp/ft2232-fpu1.ocd create mode 100644 boards/ulx3s-v2.0-85f-sp/initialize/boardmeta4MB.bin create mode 100644 boards/ulx3s-v2.0-85f-sp/initialize/boardmeta8MB.bin create mode 100755 boards/ulx3s-v2.0-85f-sp/initialize/initialize4MB.sh create mode 100755 boards/ulx3s-v2.0-85f-sp/initialize/initialize8MB.sh create mode 100644 boards/ulx3s-v2.0-85f-sp/initialize/jump.bin create mode 100755 boards/ulx3s-v2.0-85f-sp/initialize/jump.py create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k.bit create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.svf create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.vme create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.svf create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.vme create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.svf create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.vme create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.svf create mode 120000 boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.vme create mode 100644 boards/ulx3s-v2.0-85f-sp/top/bootloader_sp_ulx3s.v create mode 100644 boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf create mode 100644 boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_32mbit.xcf create mode 100644 boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v2.0-85f-sp/ulx3s_85f_sram.xcf diff --git a/boards/ulx3s-v2.0-85f-sp/Makefile b/boards/ulx3s-v2.0-85f-sp/Makefile new file mode 100644 index 0000000..fac64b1 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/Makefile @@ -0,0 +1,143 @@ + +PROJ_FILE := $(shell ls *.ldf | head -1) +PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) +IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) +IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) + +DIAMOND_BASE := /usr/local/diamond +DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) +DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) +DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) + +# OPENOCD_BASE := ../../programmer/openocd/ulx3s/ +OPENOCD_BASE := ./ + +# name of the project as defined in project file +PROJECT = project + +# FPGA flashing device for programming +FPGA_DEVICE = LFE5U-85F + +JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml +JUNK += dummy_sym.sort project_tcl.html promote.xml +JUNK += generate_core.tcl generate_ngd.tcl msg_file.log +JUNK += project_tcr.dir + +all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf \ + + +$(PROJECT)/$(PROJECT)_$(PROJECT).bit: + echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} + +# same file with different name required for multiboot to work +$(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + cp $< $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_sram.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_sram.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT).mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_flash_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 32 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_multiboot_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_multiboot_micron_32mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + dd if=/dev/zero of=/tmp/zero.bit bs=1k count=300 + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 64 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_multiboot_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_multiboot_spansion_64mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 128 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_multiboot_micron_128mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_multiboot_micron_128mbit.xcf -of $@ + +program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + echo pgr_project open ulx3s_85f_sram.xcf \; pgr_program run | ${DIAMONDC} + +program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-85f.ocd + +program_web: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + svfupload.py ulx3s.lan $< + +program_web_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf + svfupload.py ulx3s.lan $< + +program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-85f.ocd + +program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + +program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme + FleaFPGA-JTAG $< + +program_flea_flash_spansion: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme + FleaFPGA-JTAG $< + +#$(PROJECT)/$(PROJECT)_$(PROJECT).jed: +# echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -fullvme -if sparrowhawk_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ + +flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme + ${PROGRAMMERC} $< + # after this, to gain access to serial port on linux + # rmmod ftdi_sio; modprobe ftdi_sio + +# example another project +#%.svf : %.jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ +# mv -f $@ $@.flash +# ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ +# mv -f $@ $@.sram +# ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ + +clean: + rm -rf $(JUNK) *~ diff --git a/boards/ulx3s-v2.0-85f-sp/bootloader.ldf b/boards/ulx3s-v2.0-85f-sp/bootloader.ldf new file mode 100644 index 0000000..936630d --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/bootloader.ldf @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-85f-sp/clocks/clk_200M_48M.v b/boards/ulx3s-v2.0-85f-sp/clocks/clk_200M_48M.v new file mode 100644 index 0000000..2e9bb80 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/clocks/clk_200M_48M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_200M_48M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 200.00 -fclkop 48.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_200M_48M/clk_200M_48M.fdc */ +/* Wed Jul 11 00:10:22 2018 */ + + +`timescale 1 ns / 1 ps +module clk_200M_48M (CLKI, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire LOCK; + + wire REFCLK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 11 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 12 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 25 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="48.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="200.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 200.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-85f-sp/clocks/clk_25M_200M.v b/boards/ulx3s-v2.0-85f-sp/clocks/clk_25M_200M.v new file mode 100644 index 0000000..0ce5c18 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/clocks/clk_25M_200M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_200M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 200.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_25M_200M/clk_25M_200M.fdc */ +/* Wed Jul 11 00:09:44 2018 */ + + +`timescale 1 ns / 1 ps +module clk_25M_200M (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire REFCLK; + wire LOCK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 2 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 3 ; + defparam PLLInst_0.CLKFB_DIV = 8 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="200.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="25.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 200.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v17patch.lpf new file mode 100644 index 0000000..8e0d34c --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v17patch.lpf @@ -0,0 +1,435 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v1.7 patched towards v1.8 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "W1"; # UP +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "Y2"; # RIGHT +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "J1"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J3"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "K2"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "K1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "H2"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "H1"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; +LOCATE COMP "wifi_gpio17" SITE "N3"; +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Read + +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_clkp" SITE "A17"; # Clock + +LOCATE COMP "gpdi_clkn" SITE "B18"; # Clock - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "C12"; # I2C shared with RTC +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "D15"; # J2_25+ GP22 +LOCATE COMP "gn[22]" SITE "E15"; # J2_25- GN22 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "B15"; # J2_31+ GP25 +LOCATE COMP "gn[25]" SITE "C15"; # J2_31- GN25 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v20.lpf b/boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v20.lpf new file mode 100644 index 0000000..29907ed --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/constraints/ulx3s_v20.lpf @@ -0,0 +1,452 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v2.0 and v2.1 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-85f-sp/ecp5-12f.ocd b/boards/ulx3s-v2.0-85f-sp/ecp5-12f.ocd new file mode 100644 index 0000000..d578c69 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/ecp5-12f.ocd @@ -0,0 +1,16 @@ +# ecp3.cfg +# OpenOCD commands + +telnet_port 4444 +gdb_port 3333 + +# JTAG TAPs +jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 + +init +scan_chain +svf -tap lfe5u12.tap project/project_project_sram.svf +shutdown diff --git a/boards/ulx3s-v2.0-85f-sp/ft2232-fpu1.ocd b/boards/ulx3s-v2.0-85f-sp/ft2232-fpu1.ocd new file mode 100644 index 0000000..6c41311 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/ft2232-fpu1.ocd @@ -0,0 +1,9 @@ +# +# PLDkit FPU1 JTAG Programmer +# + +interface ftdi +ftdi_device_desc "FPU1 JTAG Programmer" +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x3088 0x1f8b +adapter_khz 25000 diff --git a/boards/ulx3s-v2.0-85f-sp/initialize/boardmeta4MB.bin b/boards/ulx3s-v2.0-85f-sp/initialize/boardmeta4MB.bin new file mode 100644 index 0000000..7a525c7 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/initialize/boardmeta4MB.bin @@ -0,0 +1,119 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x2FFFFF", + "userdata": "0x300000-0x3FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-85f-sp/initialize/boardmeta8MB.bin b/boards/ulx3s-v2.0-85f-sp/initialize/boardmeta8MB.bin new file mode 100644 index 0000000..89be03c --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/initialize/boardmeta8MB.bin @@ -0,0 +1,58 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x3FFFFF", + "userdata": "0x500000-0x7FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-85f-sp/initialize/initialize4MB.sh b/boards/ulx3s-v2.0-85f-sp/initialize/initialize4MB.sh new file mode 100755 index 0000000..3d67d93 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/initialize/initialize4MB.sh @@ -0,0 +1,30 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x3FF000) # flash size - 0x1000 +jump_command_address=$(printf "%d" 0x3FFF00) # flash size - 0x100 + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta4MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-85f-sp/initialize/initialize8MB.sh b/boards/ulx3s-v2.0-85f-sp/initialize/initialize8MB.sh new file mode 100755 index 0000000..b127f53 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/initialize/initialize8MB.sh @@ -0,0 +1,31 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 8 Mbit = 1 MB = 0x100000 +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x7FF000) # flash size - 0x1000 (-4KB) +jump_command_address=$(printf "%d" 0x7FFF00) # flash size - 0x100 (-256) + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta8MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-85f-sp/initialize/jump.bin b/boards/ulx3s-v2.0-85f-sp/initialize/jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..d39691f0cc8e593945579b840fe60410bede6a07 GIT binary patch literal 50 bcmezWA06!73=*khU|?VtU|>L({r?{TKoKe0 literal 0 HcmV?d00001 diff --git a/boards/ulx3s-v2.0-85f-sp/initialize/jump.py b/boards/ulx3s-v2.0-85f-sp/initialize/jump.py new file mode 100755 index 0000000..b1ff948 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/initialize/jump.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# Lattice ECP5 jump command generator +# TN1216 p.23 describes the jump command syntax which does not work. +# The syntax has been fixed by looking at dual boot intel hex file +# generated by diamond, this actually works. + +import struct +import sys + +# write output of this funtion at FLASH address: +# jump_command_address = 0x3FFF00 = 4194048 + +# write "golden" bitstream at FLASH address: +golden_image_address = 0x140000 +golden_image_address = int(sys.argv[1]) + +# normally both 0 +reverse_bytes = 0 +reverse_bits = 0 + +# to compare with intel HEX file generated by diamond: +# (not for normal use) +# reverse_bytes = 1 +# reverse_bits = 1 +# ./jump.py | hexdump -C + +def reverse_Bits(n, no_of_bits): + result = 0 + for i in range(no_of_bits): + result <<= 1 + result |= n & 1 + n >>= 1 + return result + +def uint8(n): + if reverse_bits: + n = reverse_Bits(n, 8) + return struct.pack(">B", n) + +def uint16(n): + if reverse_bits: + n = reverse_Bits(n, 16) + if reverse_bytes: + return struct.pack("H", n) + +def uint24(n): + if reverse_bits: + n = reverse_Bits(n, 24) + if reverse_bytes: + return struct.pack("> 8 ) + else: + return struct.pack(">HB", n >> 8, n & 0xFF ) + +def uint32(n): + if reverse_bits: + n = reverse_Bits(n, 32) + if reverse_bytes: + return struct.pack("L", n) + +packet = b'' +# Frame (START) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) +# Preamble +packet += uint16(0xBDB3) # Preamble +# Frame (Control Register 0) commented out, diamond doesn't output this +# if uncommented, jump won't work: +#packet += uint8(0xC4) # Write control register 0 command +#packet += uint24(0) # 24-bit Command Information +#packet += uint32(0) # Control Register 0 data +# This is generated by diamond: +packet += uint32(0xFFFFFFFF) # I don't know what it does but it works +# Framme (Jump Command) +#packet += uint8(0xFE) # Jump command Wrong noted in TN1216 +packet += uint8(0x7E) # Jump command generated by diamond +packet += uint24(0) # 24-bit Command Information +packet += uint8(0x03) # SPI Flash Read opcode (0x03 = regular read, 0x0B = fast read) +packet += uint24(golden_image_address) # 24-bit SPI Flash Sector X address +# Frame (END) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) + +sys.stdout.write(packet) +# print([elem.encode("hex") for elem in packet]) diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k.bit b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k.bit new file mode 120000 index 0000000..59e9556 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k.bit @@ -0,0 +1 @@ +project/project_project.bit \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.svf b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.svf new file mode 120000 index 0000000..a59752b --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.vme b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.vme new file mode 120000 index 0000000..e2f6ec2 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_128mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.svf new file mode 120000 index 0000000..623c0d8 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.vme new file mode 120000 index 0000000..bc0382a --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_micron_32mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.svf new file mode 120000 index 0000000..2c6afa4 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.vme new file mode 120000 index 0000000..9e1e580 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_multiboot_flash_spansion_64mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.svf b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.svf new file mode 120000 index 0000000..bb7617d --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.svf @@ -0,0 +1 @@ +project/project_project_sram.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.vme b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.vme new file mode 120000 index 0000000..d098048 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/tinyfpga_85k_sram.vme @@ -0,0 +1 @@ +project/project_project_sram.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-85f-sp/top/bootloader_sp_ulx3s.v b/boards/ulx3s-v2.0-85f-sp/top/bootloader_sp_ulx3s.v new file mode 100644 index 0000000..f2799ee --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/top/bootloader_sp_ulx3s.v @@ -0,0 +1,137 @@ +module bootloader_sp_ulx3s ( + input clk_25mhz, + + inout usb_fpga_dp, + inout usb_fpga_dn, + + output usb_fpga_pu_dp, + inout user_programn, + + output [7:0] led, + + input flash_miso, + output flash_mosi, + output flash_clk, + output flash_csn, + + input [6:0] btn, + output wifi_gpio0 +); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// generate 48 mhz clock + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + wire clk_200mhz; + clk_25M_200M clk_200M_inst ( + .CLKI(clk_25mhz), + .CLKOP(clk_200mhz) + ); + + wire clk_48mhz; + wire clk_ready; + clk_200M_48M clk_48M_inst ( + .CLKI(clk_200mhz), + .CLKOP(clk_48mhz), + .LOCK(clk_ready) + ); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// instantiate tinyfpga bootloader + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg [15:0] reset_counter = 0; // counter for debouce and prolong reset + wire reset; + assign reset = ~reset_counter[15]; + wire usb_p_tx; + wire usb_n_tx; + wire usb_p_rx; + wire usb_n_rx; + wire usb_tx_en; + wire pin_led; + wire [7:0] debug_led; + wire boot; + wire S_flash_clk; + wire S_flash_csn; + + tinyfpgasp_bootloader tinyfpgasp_bootloader_inst ( + .clk_48mhz(clk_48mhz), + .reset(reset), + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + .led(pin_led), + .debug_led(debug_led), + .spi_miso(flash_miso), + .spi_mosi(flash_mosi), + .spi_sck(S_flash_clk), + .spi_cs(S_flash_csn), + .boot(boot) + ); + + assign usb_fpga_dp = reset ? 1'b0 : (usb_tx_en ? usb_p_tx : 1'bz); + assign usb_fpga_dn = reset ? 1'b0 : (usb_tx_en ? usb_n_tx : 1'bz); + assign usb_p_rx = usb_tx_en ? 1'b1 : usb_fpga_dp; + assign usb_n_rx = usb_tx_en ? 1'b0 : usb_fpga_dn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Vendor-specific clock output to SPI config flash + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + USRMCLK usrmclk_inst ( + .USRMCLKI(S_flash_clk), + .USRMCLKTS(S_flash_csn) + ) /* synthesis syn_noprune=1 */; + assign flash_clk = S_flash_clk; + assign flash_csn = S_flash_csn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Debonuce and prolong RESET + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + always @(posedge clk_48mhz) + begin + if (btn[1] | ~clk_ready) + reset_counter <= 0; + else + if (reset_counter[15] == 0) + reset_counter <= reset_counter + 1; + end + + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// ULX3S board buttons and LEDs + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + assign wifi_gpio0 = btn[0]; + assign led[0] = pin_led; + assign led[1] = ~pin_led; + assign led[5] = debug_led; + assign led[7] = boot; + // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + + // PULLUP 1.5k D+ + assign usb_fpga_pu_dp = 1; + + // EXIT from BOOTLOADER + // assign user_programn = ~boot; + + +endmodule diff --git a/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf new file mode 100644 index 0000000..9ac9906 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Micron + ECP5U + LFE5U-85F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_128mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-85F + 0x41113043 + All + LFE5U-85F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-85F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_128mbit.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_128mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_32mbit.xcf new file mode 100644 index 0000000..07fad7d --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-85F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_32mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-85F + 0x41113043 + All + LFE5U-85F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-85F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P32 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_32mbit.mcs + 0x00000000 + 0x00400000 + 32 + 4194304 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_32mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_spansion_64mbit.xcf new file mode 100644 index 0000000..a898fa2 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-85F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-85F + 0x41113043 + All + LFE5U-85F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-85F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_spansion_64mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_sram.xcf b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_sram.xcf new file mode 100644 index 0000000..e002ae2 --- /dev/null +++ b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_sram.xcf @@ -0,0 +1,48 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5UM + LFE5U-85F + 0x41113043 + All + LFE5U-85F + + 8 + 11111111 + 1 + 0 + + project/project_project.bit + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A + + From f2ff47d4636ece9e9a2dd5ab68a205e9d75ea195 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 26 Aug 2018 15:55:24 +0200 Subject: [PATCH 69/90] tinyfpgasp 45k v1.7patched update (more blinky) --- boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v | 6 ++++-- .../ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf | 2 +- .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v b/boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v index 08fa8f0..3aad1a4 100644 --- a/boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v +++ b/boards/ulx3s-v1.7-45f-sp/top/bootloader_sp_ulx3s.v @@ -118,8 +118,10 @@ module bootloader_sp_ulx3s ( //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// assign wifi_gpio0 = btn[0]; - //assign led[5] = boot; - assign led = debug_led; + assign led[0] = pin_led; + assign led[1] = ~pin_led; + assign led[5] = debug_led; + assign led[7] = boot; // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; diff --git a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf index f20aa77..dfd955c 100644 --- a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf +++ b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf @@ -7,7 +7,7 @@ 1 - Micron + Lattice ECP5U LFE5U-45F All diff --git a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf index 8ccb7e7..9daeac4 100644 --- a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf +++ b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf @@ -7,7 +7,7 @@ 1 - Micron + Lattice ECP5U LFE5U-45F All From 9797753718d69637dd0199dd3d06739416e0c3f3 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 26 Aug 2018 17:17:24 +0200 Subject: [PATCH 70/90] ulx3s updated --- .../ulx3s_45f_flash_micron_32mbit.xcf | 4 +- .../ulx3s_45f_flash_spansion_64mbit.xcf | 2 +- .../ulx3s_45f_multiboot_micron_32mbit.xcf | 14 +- boards/ulx3s-v2.0-12f-sp/Makefile | 143 ++++++ boards/ulx3s-v2.0-12f-sp/bootloader.ldf | 56 +++ .../ulx3s-v2.0-12f-sp/clocks/clk_200M_48M.v | 75 +++ .../ulx3s-v2.0-12f-sp/clocks/clk_25M_200M.v | 75 +++ .../constraints/ulx3s_v17patch.lpf | 435 +++++++++++++++++ .../constraints/ulx3s_v20.lpf | 452 ++++++++++++++++++ boards/ulx3s-v2.0-12f-sp/ecp5-12f.ocd | 16 + boards/ulx3s-v2.0-12f-sp/ft2232-fpu1.ocd | 9 + .../initialize/boardmeta4MB.bin | 119 +++++ .../initialize/boardmeta8MB.bin | 58 +++ .../initialize/initialize4MB.sh | 30 ++ .../initialize/initialize8MB.sh | 31 ++ boards/ulx3s-v2.0-12f-sp/initialize/jump.bin | Bin 0 -> 50 bytes boards/ulx3s-v2.0-12f-sp/initialize/jump.py | 95 ++++ boards/ulx3s-v2.0-12f-sp/tinyfpga_12k.bit | 1 + ...pga_12k_multiboot_flash_micron_128mbit.svf | 1 + ...pga_12k_multiboot_flash_micron_128mbit.vme | 1 + ...fpga_12k_multiboot_flash_micron_32mbit.svf | 1 + ...fpga_12k_multiboot_flash_micron_32mbit.vme | 1 + ...ga_12k_multiboot_flash_spansion_64mbit.svf | 1 + ...ga_12k_multiboot_flash_spansion_64mbit.vme | 1 + .../ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.svf | 1 + .../ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.vme | 1 + .../top/bootloader_sp_ulx3s.v | 137 ++++++ .../ulx3s_12f_flash_micron_128mbit.xcf | 104 ++++ .../ulx3s_12f_flash_micron_32mbit.xcf | 104 ++++ .../ulx3s_12f_flash_spansion_64mbit.xcf | 104 ++++ .../ulx3s_12f_multiboot_micron_128mbit.xcf | 104 ++++ .../ulx3s_12f_multiboot_micron_32mbit.xcf | 104 ++++ .../ulx3s_12f_multiboot_spansion_64mbit.xcf | 104 ++++ boards/ulx3s-v2.0-12f-sp/ulx3s_12f_sram.xcf | 48 ++ boards/ulx3s-v2.0-45f-sp/Makefile | 143 ++++++ boards/ulx3s-v2.0-45f-sp/bootloader.ldf | 56 +++ .../ulx3s-v2.0-45f-sp/clocks/clk_200M_48M.v | 75 +++ .../ulx3s-v2.0-45f-sp/clocks/clk_25M_200M.v | 75 +++ .../constraints/ulx3s_v17patch.lpf | 435 +++++++++++++++++ .../constraints/ulx3s_v20.lpf | 452 ++++++++++++++++++ boards/ulx3s-v2.0-45f-sp/ecp5-12f.ocd | 16 + boards/ulx3s-v2.0-45f-sp/ft2232-fpu1.ocd | 9 + .../initialize/boardmeta4MB.bin | 119 +++++ .../initialize/boardmeta8MB.bin | 58 +++ .../initialize/initialize4MB.sh | 30 ++ .../initialize/initialize8MB.sh | 31 ++ boards/ulx3s-v2.0-45f-sp/initialize/jump.bin | Bin 0 -> 50 bytes boards/ulx3s-v2.0-45f-sp/initialize/jump.py | 95 ++++ boards/ulx3s-v2.0-45f-sp/tinyfpga_45k.bit | 1 + ...pga_45k_multiboot_flash_micron_128mbit.svf | 1 + ...pga_45k_multiboot_flash_micron_128mbit.vme | 1 + ...fpga_45k_multiboot_flash_micron_32mbit.svf | 1 + ...fpga_45k_multiboot_flash_micron_32mbit.vme | 1 + ...ga_45k_multiboot_flash_spansion_64mbit.svf | 1 + ...ga_45k_multiboot_flash_spansion_64mbit.vme | 1 + .../ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.svf | 1 + .../ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.vme | 1 + .../top/bootloader_sp_ulx3s.v | 137 ++++++ .../ulx3s_45f_multiboot_micron_128mbit.xcf | 104 ++++ .../ulx3s_45f_multiboot_micron_32mbit.xcf | 104 ++++ .../ulx3s_45f_multiboot_spansion_64mbit.xcf | 104 ++++ boards/ulx3s-v2.0-45f-sp/ulx3s_45f_sram.xcf | 48 ++ 62 files changed, 4522 insertions(+), 10 deletions(-) create mode 100644 boards/ulx3s-v2.0-12f-sp/Makefile create mode 100644 boards/ulx3s-v2.0-12f-sp/bootloader.ldf create mode 100644 boards/ulx3s-v2.0-12f-sp/clocks/clk_200M_48M.v create mode 100644 boards/ulx3s-v2.0-12f-sp/clocks/clk_25M_200M.v create mode 100644 boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v17patch.lpf create mode 100644 boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v20.lpf create mode 100644 boards/ulx3s-v2.0-12f-sp/ecp5-12f.ocd create mode 100644 boards/ulx3s-v2.0-12f-sp/ft2232-fpu1.ocd create mode 100644 boards/ulx3s-v2.0-12f-sp/initialize/boardmeta4MB.bin create mode 100644 boards/ulx3s-v2.0-12f-sp/initialize/boardmeta8MB.bin create mode 100755 boards/ulx3s-v2.0-12f-sp/initialize/initialize4MB.sh create mode 100755 boards/ulx3s-v2.0-12f-sp/initialize/initialize8MB.sh create mode 100644 boards/ulx3s-v2.0-12f-sp/initialize/jump.bin create mode 100755 boards/ulx3s-v2.0-12f-sp/initialize/jump.py create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k.bit create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.svf create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.vme create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.svf create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.vme create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.svf create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.vme create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.svf create mode 120000 boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.vme create mode 100644 boards/ulx3s-v2.0-12f-sp/top/bootloader_sp_ulx3s.v create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_128mbit.xcf create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_32mbit.xcf create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_128mbit.xcf create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_32mbit.xcf create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v2.0-12f-sp/ulx3s_12f_sram.xcf create mode 100644 boards/ulx3s-v2.0-45f-sp/Makefile create mode 100644 boards/ulx3s-v2.0-45f-sp/bootloader.ldf create mode 100644 boards/ulx3s-v2.0-45f-sp/clocks/clk_200M_48M.v create mode 100644 boards/ulx3s-v2.0-45f-sp/clocks/clk_25M_200M.v create mode 100644 boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v17patch.lpf create mode 100644 boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v20.lpf create mode 100644 boards/ulx3s-v2.0-45f-sp/ecp5-12f.ocd create mode 100644 boards/ulx3s-v2.0-45f-sp/ft2232-fpu1.ocd create mode 100644 boards/ulx3s-v2.0-45f-sp/initialize/boardmeta4MB.bin create mode 100644 boards/ulx3s-v2.0-45f-sp/initialize/boardmeta8MB.bin create mode 100755 boards/ulx3s-v2.0-45f-sp/initialize/initialize4MB.sh create mode 100755 boards/ulx3s-v2.0-45f-sp/initialize/initialize8MB.sh create mode 100644 boards/ulx3s-v2.0-45f-sp/initialize/jump.bin create mode 100755 boards/ulx3s-v2.0-45f-sp/initialize/jump.py create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k.bit create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.svf create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.vme create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.svf create mode 120000 boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.vme create mode 100644 boards/ulx3s-v2.0-45f-sp/top/bootloader_sp_ulx3s.v create mode 100644 boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_128mbit.xcf create mode 100644 boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf create mode 100644 boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v2.0-45f-sp/ulx3s_45f_sram.xcf diff --git a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_micron_32mbit.xcf index 8bde416..965834b 100644 --- a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_micron_32mbit.xcf +++ b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_micron_32mbit.xcf @@ -7,7 +7,7 @@ 1 - Micron + Lattice ECP5U LFE5U-45F All @@ -62,7 +62,7 @@ SPI Flash Erase,Program project/project_project.mcs 0x00000000 - 0x00080000 + 0x00400000 32 4194304 1 diff --git a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_spansion_64mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_spansion_64mbit.xcf index 5ab9626..aedb695 100644 --- a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_spansion_64mbit.xcf +++ b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_flash_spansion_64mbit.xcf @@ -7,7 +7,7 @@ 1 - Micron + Lattice ECP5U LFE5U-45F All diff --git a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf index dfd955c..3109f0d 100644 --- a/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf +++ b/boards/ulx3s-v1.7-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf @@ -54,17 +54,17 @@ 1 - SPANSION + Micron SPI Serial Flash - SPI-S25FL164K - 0x16 - 8-lead SOIC + SPI-M25P32 + 0x15 + 8-pin VDFPN8 SPI Flash Erase,Program project/project_project_multiboot_flash_micron_32mbit.mcs 0x00000000 - 0x00800000 - 64 - 8388608 + 0x00400000 + 32 + 4194304 1 diff --git a/boards/ulx3s-v2.0-12f-sp/Makefile b/boards/ulx3s-v2.0-12f-sp/Makefile new file mode 100644 index 0000000..f5f893f --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/Makefile @@ -0,0 +1,143 @@ + +PROJ_FILE := $(shell ls *.ldf | head -1) +PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) +IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) +IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) + +DIAMOND_BASE := /usr/local/diamond +DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) +DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) +DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) + +# OPENOCD_BASE := ../../programmer/openocd/ulx3s/ +OPENOCD_BASE := ./ + +# name of the project as defined in project file +PROJECT = project + +# FPGA flashing device for programming +FPGA_DEVICE = LFE5U-12F + +JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml +JUNK += dummy_sym.sort project_tcl.html promote.xml +JUNK += generate_core.tcl generate_ngd.tcl msg_file.log +JUNK += project_tcr.dir + +all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf \ + + +$(PROJECT)/$(PROJECT)_$(PROJECT).bit: + echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} + +# same file with different name required for multiboot to work +$(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + cp $< $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_12f_sram.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_12f_sram.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT).mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_12f_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_12f_flash_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 32 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_12f_multiboot_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_12f_multiboot_micron_32mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + dd if=/dev/zero of=/tmp/zero.bit bs=1k count=300 + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 64 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_12f_multiboot_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_12f_multiboot_spansion_64mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 128 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_12f_multiboot_micron_128mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_12f_multiboot_micron_128mbit.xcf -of $@ + +program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + echo pgr_project open ulx3s_12f_sram.xcf \; pgr_program run | ${DIAMONDC} + +program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-12f.ocd + +program_web: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + svfupload.py ulx3s.lan $< + +program_web_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf + svfupload.py ulx3s.lan $< + +program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-12f.ocd + +program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + +program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme + FleaFPGA-JTAG $< + +program_flea_flash_spansion: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme + FleaFPGA-JTAG $< + +#$(PROJECT)/$(PROJECT)_$(PROJECT).jed: +# echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -fullvme -if sparrowhawk_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ + +flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme + ${PROGRAMMERC} $< + # after this, to gain access to serial port on linux + # rmmod ftdi_sio; modprobe ftdi_sio + +# example another project +#%.svf : %.jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ +# mv -f $@ $@.flash +# ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ +# mv -f $@ $@.sram +# ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ + +clean: + rm -rf $(JUNK) *~ diff --git a/boards/ulx3s-v2.0-12f-sp/bootloader.ldf b/boards/ulx3s-v2.0-12f-sp/bootloader.ldf new file mode 100644 index 0000000..940df22 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/bootloader.ldf @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-12f-sp/clocks/clk_200M_48M.v b/boards/ulx3s-v2.0-12f-sp/clocks/clk_200M_48M.v new file mode 100644 index 0000000..2e9bb80 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/clocks/clk_200M_48M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_200M_48M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 200.00 -fclkop 48.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_200M_48M/clk_200M_48M.fdc */ +/* Wed Jul 11 00:10:22 2018 */ + + +`timescale 1 ns / 1 ps +module clk_200M_48M (CLKI, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire LOCK; + + wire REFCLK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 11 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 12 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 25 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="48.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="200.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 200.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-12f-sp/clocks/clk_25M_200M.v b/boards/ulx3s-v2.0-12f-sp/clocks/clk_25M_200M.v new file mode 100644 index 0000000..0ce5c18 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/clocks/clk_25M_200M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_200M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 200.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_25M_200M/clk_25M_200M.fdc */ +/* Wed Jul 11 00:09:44 2018 */ + + +`timescale 1 ns / 1 ps +module clk_25M_200M (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire REFCLK; + wire LOCK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 2 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 3 ; + defparam PLLInst_0.CLKFB_DIV = 8 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="200.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="25.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 200.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v17patch.lpf new file mode 100644 index 0000000..8e0d34c --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v17patch.lpf @@ -0,0 +1,435 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v1.7 patched towards v1.8 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "W1"; # UP +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "Y2"; # RIGHT +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "J1"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J3"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "K2"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "K1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "H2"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "H1"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; +LOCATE COMP "wifi_gpio17" SITE "N3"; +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Read + +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_clkp" SITE "A17"; # Clock + +LOCATE COMP "gpdi_clkn" SITE "B18"; # Clock - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "C12"; # I2C shared with RTC +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "D15"; # J2_25+ GP22 +LOCATE COMP "gn[22]" SITE "E15"; # J2_25- GN22 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "B15"; # J2_31+ GP25 +LOCATE COMP "gn[25]" SITE "C15"; # J2_31- GN25 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v20.lpf b/boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v20.lpf new file mode 100644 index 0000000..29907ed --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/constraints/ulx3s_v20.lpf @@ -0,0 +1,452 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v2.0 and v2.1 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-12f-sp/ecp5-12f.ocd b/boards/ulx3s-v2.0-12f-sp/ecp5-12f.ocd new file mode 100644 index 0000000..d578c69 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ecp5-12f.ocd @@ -0,0 +1,16 @@ +# ecp3.cfg +# OpenOCD commands + +telnet_port 4444 +gdb_port 3333 + +# JTAG TAPs +jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 + +init +scan_chain +svf -tap lfe5u12.tap project/project_project_sram.svf +shutdown diff --git a/boards/ulx3s-v2.0-12f-sp/ft2232-fpu1.ocd b/boards/ulx3s-v2.0-12f-sp/ft2232-fpu1.ocd new file mode 100644 index 0000000..6c41311 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ft2232-fpu1.ocd @@ -0,0 +1,9 @@ +# +# PLDkit FPU1 JTAG Programmer +# + +interface ftdi +ftdi_device_desc "FPU1 JTAG Programmer" +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x3088 0x1f8b +adapter_khz 25000 diff --git a/boards/ulx3s-v2.0-12f-sp/initialize/boardmeta4MB.bin b/boards/ulx3s-v2.0-12f-sp/initialize/boardmeta4MB.bin new file mode 100644 index 0000000..7a525c7 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/initialize/boardmeta4MB.bin @@ -0,0 +1,119 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x2FFFFF", + "userdata": "0x300000-0x3FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-12f-sp/initialize/boardmeta8MB.bin b/boards/ulx3s-v2.0-12f-sp/initialize/boardmeta8MB.bin new file mode 100644 index 0000000..89be03c --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/initialize/boardmeta8MB.bin @@ -0,0 +1,58 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x3FFFFF", + "userdata": "0x500000-0x7FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-12f-sp/initialize/initialize4MB.sh b/boards/ulx3s-v2.0-12f-sp/initialize/initialize4MB.sh new file mode 100755 index 0000000..3d67d93 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/initialize/initialize4MB.sh @@ -0,0 +1,30 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x3FF000) # flash size - 0x1000 +jump_command_address=$(printf "%d" 0x3FFF00) # flash size - 0x100 + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta4MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-12f-sp/initialize/initialize8MB.sh b/boards/ulx3s-v2.0-12f-sp/initialize/initialize8MB.sh new file mode 100755 index 0000000..b127f53 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/initialize/initialize8MB.sh @@ -0,0 +1,31 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 8 Mbit = 1 MB = 0x100000 +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x7FF000) # flash size - 0x1000 (-4KB) +jump_command_address=$(printf "%d" 0x7FFF00) # flash size - 0x100 (-256) + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta8MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-12f-sp/initialize/jump.bin b/boards/ulx3s-v2.0-12f-sp/initialize/jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..d39691f0cc8e593945579b840fe60410bede6a07 GIT binary patch literal 50 bcmezWA06!73=*khU|?VtU|>L({r?{TKoKe0 literal 0 HcmV?d00001 diff --git a/boards/ulx3s-v2.0-12f-sp/initialize/jump.py b/boards/ulx3s-v2.0-12f-sp/initialize/jump.py new file mode 100755 index 0000000..b1ff948 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/initialize/jump.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# Lattice ECP5 jump command generator +# TN1216 p.23 describes the jump command syntax which does not work. +# The syntax has been fixed by looking at dual boot intel hex file +# generated by diamond, this actually works. + +import struct +import sys + +# write output of this funtion at FLASH address: +# jump_command_address = 0x3FFF00 = 4194048 + +# write "golden" bitstream at FLASH address: +golden_image_address = 0x140000 +golden_image_address = int(sys.argv[1]) + +# normally both 0 +reverse_bytes = 0 +reverse_bits = 0 + +# to compare with intel HEX file generated by diamond: +# (not for normal use) +# reverse_bytes = 1 +# reverse_bits = 1 +# ./jump.py | hexdump -C + +def reverse_Bits(n, no_of_bits): + result = 0 + for i in range(no_of_bits): + result <<= 1 + result |= n & 1 + n >>= 1 + return result + +def uint8(n): + if reverse_bits: + n = reverse_Bits(n, 8) + return struct.pack(">B", n) + +def uint16(n): + if reverse_bits: + n = reverse_Bits(n, 16) + if reverse_bytes: + return struct.pack("H", n) + +def uint24(n): + if reverse_bits: + n = reverse_Bits(n, 24) + if reverse_bytes: + return struct.pack("> 8 ) + else: + return struct.pack(">HB", n >> 8, n & 0xFF ) + +def uint32(n): + if reverse_bits: + n = reverse_Bits(n, 32) + if reverse_bytes: + return struct.pack("L", n) + +packet = b'' +# Frame (START) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) +# Preamble +packet += uint16(0xBDB3) # Preamble +# Frame (Control Register 0) commented out, diamond doesn't output this +# if uncommented, jump won't work: +#packet += uint8(0xC4) # Write control register 0 command +#packet += uint24(0) # 24-bit Command Information +#packet += uint32(0) # Control Register 0 data +# This is generated by diamond: +packet += uint32(0xFFFFFFFF) # I don't know what it does but it works +# Framme (Jump Command) +#packet += uint8(0xFE) # Jump command Wrong noted in TN1216 +packet += uint8(0x7E) # Jump command generated by diamond +packet += uint24(0) # 24-bit Command Information +packet += uint8(0x03) # SPI Flash Read opcode (0x03 = regular read, 0x0B = fast read) +packet += uint24(golden_image_address) # 24-bit SPI Flash Sector X address +# Frame (END) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) + +sys.stdout.write(packet) +# print([elem.encode("hex") for elem in packet]) diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k.bit b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k.bit new file mode 120000 index 0000000..59e9556 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k.bit @@ -0,0 +1 @@ +project/project_project.bit \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.svf b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.svf new file mode 120000 index 0000000..a59752b --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.vme b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.vme new file mode 120000 index 0000000..e2f6ec2 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_128mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.svf new file mode 120000 index 0000000..623c0d8 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.vme new file mode 120000 index 0000000..bc0382a --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_micron_32mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.svf new file mode 120000 index 0000000..2c6afa4 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.vme new file mode 120000 index 0000000..9e1e580 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_multiboot_flash_spansion_64mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.svf b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.svf new file mode 120000 index 0000000..bb7617d --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.svf @@ -0,0 +1 @@ +project/project_project_sram.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.vme b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.vme new file mode 120000 index 0000000..d098048 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/tinyfpga_12k_sram.vme @@ -0,0 +1 @@ +project/project_project_sram.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-12f-sp/top/bootloader_sp_ulx3s.v b/boards/ulx3s-v2.0-12f-sp/top/bootloader_sp_ulx3s.v new file mode 100644 index 0000000..f2799ee --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/top/bootloader_sp_ulx3s.v @@ -0,0 +1,137 @@ +module bootloader_sp_ulx3s ( + input clk_25mhz, + + inout usb_fpga_dp, + inout usb_fpga_dn, + + output usb_fpga_pu_dp, + inout user_programn, + + output [7:0] led, + + input flash_miso, + output flash_mosi, + output flash_clk, + output flash_csn, + + input [6:0] btn, + output wifi_gpio0 +); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// generate 48 mhz clock + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + wire clk_200mhz; + clk_25M_200M clk_200M_inst ( + .CLKI(clk_25mhz), + .CLKOP(clk_200mhz) + ); + + wire clk_48mhz; + wire clk_ready; + clk_200M_48M clk_48M_inst ( + .CLKI(clk_200mhz), + .CLKOP(clk_48mhz), + .LOCK(clk_ready) + ); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// instantiate tinyfpga bootloader + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg [15:0] reset_counter = 0; // counter for debouce and prolong reset + wire reset; + assign reset = ~reset_counter[15]; + wire usb_p_tx; + wire usb_n_tx; + wire usb_p_rx; + wire usb_n_rx; + wire usb_tx_en; + wire pin_led; + wire [7:0] debug_led; + wire boot; + wire S_flash_clk; + wire S_flash_csn; + + tinyfpgasp_bootloader tinyfpgasp_bootloader_inst ( + .clk_48mhz(clk_48mhz), + .reset(reset), + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + .led(pin_led), + .debug_led(debug_led), + .spi_miso(flash_miso), + .spi_mosi(flash_mosi), + .spi_sck(S_flash_clk), + .spi_cs(S_flash_csn), + .boot(boot) + ); + + assign usb_fpga_dp = reset ? 1'b0 : (usb_tx_en ? usb_p_tx : 1'bz); + assign usb_fpga_dn = reset ? 1'b0 : (usb_tx_en ? usb_n_tx : 1'bz); + assign usb_p_rx = usb_tx_en ? 1'b1 : usb_fpga_dp; + assign usb_n_rx = usb_tx_en ? 1'b0 : usb_fpga_dn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Vendor-specific clock output to SPI config flash + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + USRMCLK usrmclk_inst ( + .USRMCLKI(S_flash_clk), + .USRMCLKTS(S_flash_csn) + ) /* synthesis syn_noprune=1 */; + assign flash_clk = S_flash_clk; + assign flash_csn = S_flash_csn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Debonuce and prolong RESET + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + always @(posedge clk_48mhz) + begin + if (btn[1] | ~clk_ready) + reset_counter <= 0; + else + if (reset_counter[15] == 0) + reset_counter <= reset_counter + 1; + end + + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// ULX3S board buttons and LEDs + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + assign wifi_gpio0 = btn[0]; + assign led[0] = pin_led; + assign led[1] = ~pin_led; + assign led[5] = debug_led; + assign led[7] = boot; + // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + + // PULLUP 1.5k D+ + assign usb_fpga_pu_dp = 1; + + // EXIT from BOOTLOADER + // assign user_programn = ~boot; + + +endmodule diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_128mbit.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_128mbit.xcf new file mode 100644 index 0000000..3ab3a9b --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_128mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-12F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_32mbit.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_32mbit.xcf new file mode 100644 index 0000000..0b1e60f --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-12F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P32 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x00400000 + 32 + 4194304 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_spansion_64mbit.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_spansion_64mbit.xcf new file mode 100644 index 0000000..fa4e499 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_flash_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-12F + All + + 8 + 11111111 + 1 + 0 + + project/project_project.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_128mbit.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_128mbit.xcf new file mode 100644 index 0000000..23ca92d --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_128mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-12F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_128mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_128mbit.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_128mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_32mbit.xcf new file mode 100644 index 0000000..0884e60 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-12F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_32mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P32 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_32mbit.mcs + 0x00000000 + 0x00400000 + 32 + 4194304 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_32mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_spansion_64mbit.xcf new file mode 100644 index 0000000..3fd2d25 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_multiboot_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + SPANSION + ECP5U + LFE5U-12F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_spansion_64mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_sram.xcf b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_sram.xcf new file mode 100644 index 0000000..7d59714 --- /dev/null +++ b/boards/ulx3s-v2.0-12f-sp/ulx3s_12f_sram.xcf @@ -0,0 +1,48 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-12F + 0x21111043 + All + LFE5U-12F + + 8 + 11111111 + 1 + 0 + + project/project_project.bit + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A + + diff --git a/boards/ulx3s-v2.0-45f-sp/Makefile b/boards/ulx3s-v2.0-45f-sp/Makefile new file mode 100644 index 0000000..cae1bbe --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/Makefile @@ -0,0 +1,143 @@ + +PROJ_FILE := $(shell ls *.ldf | head -1) +PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) +IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) +IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) + +DIAMOND_BASE := /usr/local/diamond +DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) +DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) +DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) + +# OPENOCD_BASE := ../../programmer/openocd/ulx3s/ +OPENOCD_BASE := ./ + +# name of the project as defined in project file +PROJECT = project + +# FPGA flashing device for programming +FPGA_DEVICE = LFE5U-45F + +JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml +JUNK += dummy_sym.sort project_tcl.html promote.xml +JUNK += generate_core.tcl generate_ngd.tcl msg_file.log +JUNK += project_tcr.dir + +all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf \ + + +$(PROJECT)/$(PROJECT)_$(PROJECT).bit: + echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} + +# same file with different name required for multiboot to work +$(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + cp $< $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_sram.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_sram.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT).mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_flash_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 32 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_micron_32mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + dd if=/dev/zero of=/tmp/zero.bit bs=1k count=300 + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 64 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_spansion_64mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 128 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_45f_multiboot_micron_128mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_45f_multiboot_micron_128mbit.xcf -of $@ + +program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + echo pgr_project open ulx3s_45f_sram.xcf \; pgr_program run | ${DIAMONDC} + +program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-45f.ocd + +program_web: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + svfupload.py ulx3s.lan $< + +program_web_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf + svfupload.py ulx3s.lan $< + +program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-45f.ocd + +program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + +program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme + FleaFPGA-JTAG $< + +program_flea_flash_spansion: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme + FleaFPGA-JTAG $< + +#$(PROJECT)/$(PROJECT)_$(PROJECT).jed: +# echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -fullvme -if sparrowhawk_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ + +flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme + ${PROGRAMMERC} $< + # after this, to gain access to serial port on linux + # rmmod ftdi_sio; modprobe ftdi_sio + +# example another project +#%.svf : %.jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ +# mv -f $@ $@.flash +# ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ +# mv -f $@ $@.sram +# ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ + +clean: + rm -rf $(JUNK) *~ diff --git a/boards/ulx3s-v2.0-45f-sp/bootloader.ldf b/boards/ulx3s-v2.0-45f-sp/bootloader.ldf new file mode 100644 index 0000000..a125c79 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/bootloader.ldf @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-45f-sp/clocks/clk_200M_48M.v b/boards/ulx3s-v2.0-45f-sp/clocks/clk_200M_48M.v new file mode 100644 index 0000000..2e9bb80 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/clocks/clk_200M_48M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_200M_48M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 200.00 -fclkop 48.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_200M_48M/clk_200M_48M.fdc */ +/* Wed Jul 11 00:10:22 2018 */ + + +`timescale 1 ns / 1 ps +module clk_200M_48M (CLKI, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire LOCK; + + wire REFCLK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 11 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 12 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 25 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="48.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="200.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 200.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-45f-sp/clocks/clk_25M_200M.v b/boards/ulx3s-v2.0-45f-sp/clocks/clk_25M_200M.v new file mode 100644 index 0000000..0ce5c18 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/clocks/clk_25M_200M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_200M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 200.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_25M_200M/clk_25M_200M.fdc */ +/* Wed Jul 11 00:09:44 2018 */ + + +`timescale 1 ns / 1 ps +module clk_25M_200M (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire REFCLK; + wire LOCK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 2 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 3 ; + defparam PLLInst_0.CLKFB_DIV = 8 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="200.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="25.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 200.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v17patch.lpf new file mode 100644 index 0000000..8e0d34c --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v17patch.lpf @@ -0,0 +1,435 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v1.7 patched towards v1.8 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "W1"; # UP +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "Y2"; # RIGHT +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "J1"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J3"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "K2"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "K1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "H2"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "H1"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; +LOCATE COMP "wifi_gpio17" SITE "N3"; +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Read + +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_clkp" SITE "A17"; # Clock + +LOCATE COMP "gpdi_clkn" SITE "B18"; # Clock - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "C12"; # I2C shared with RTC +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "D15"; # J2_25+ GP22 +LOCATE COMP "gn[22]" SITE "E15"; # J2_25- GN22 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "B15"; # J2_31+ GP25 +LOCATE COMP "gn[25]" SITE "C15"; # J2_31- GN25 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v20.lpf b/boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v20.lpf new file mode 100644 index 0000000..29907ed --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/constraints/ulx3s_v20.lpf @@ -0,0 +1,452 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v2.0 and v2.1 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-45f-sp/ecp5-12f.ocd b/boards/ulx3s-v2.0-45f-sp/ecp5-12f.ocd new file mode 100644 index 0000000..d578c69 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/ecp5-12f.ocd @@ -0,0 +1,16 @@ +# ecp3.cfg +# OpenOCD commands + +telnet_port 4444 +gdb_port 3333 + +# JTAG TAPs +jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 + +init +scan_chain +svf -tap lfe5u12.tap project/project_project_sram.svf +shutdown diff --git a/boards/ulx3s-v2.0-45f-sp/ft2232-fpu1.ocd b/boards/ulx3s-v2.0-45f-sp/ft2232-fpu1.ocd new file mode 100644 index 0000000..6c41311 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/ft2232-fpu1.ocd @@ -0,0 +1,9 @@ +# +# PLDkit FPU1 JTAG Programmer +# + +interface ftdi +ftdi_device_desc "FPU1 JTAG Programmer" +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x3088 0x1f8b +adapter_khz 25000 diff --git a/boards/ulx3s-v2.0-45f-sp/initialize/boardmeta4MB.bin b/boards/ulx3s-v2.0-45f-sp/initialize/boardmeta4MB.bin new file mode 100644 index 0000000..7a525c7 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/initialize/boardmeta4MB.bin @@ -0,0 +1,119 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x2FFFFF", + "userdata": "0x300000-0x3FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-45f-sp/initialize/boardmeta8MB.bin b/boards/ulx3s-v2.0-45f-sp/initialize/boardmeta8MB.bin new file mode 100644 index 0000000..89be03c --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/initialize/boardmeta8MB.bin @@ -0,0 +1,58 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x3FFFFF", + "userdata": "0x500000-0x7FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-45f-sp/initialize/initialize4MB.sh b/boards/ulx3s-v2.0-45f-sp/initialize/initialize4MB.sh new file mode 100755 index 0000000..3d67d93 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/initialize/initialize4MB.sh @@ -0,0 +1,30 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x3FF000) # flash size - 0x1000 +jump_command_address=$(printf "%d" 0x3FFF00) # flash size - 0x100 + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta4MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-45f-sp/initialize/initialize8MB.sh b/boards/ulx3s-v2.0-45f-sp/initialize/initialize8MB.sh new file mode 100755 index 0000000..b127f53 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/initialize/initialize8MB.sh @@ -0,0 +1,31 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 8 Mbit = 1 MB = 0x100000 +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x7FF000) # flash size - 0x1000 (-4KB) +jump_command_address=$(printf "%d" 0x7FFF00) # flash size - 0x100 (-256) + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta8MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-45f-sp/initialize/jump.bin b/boards/ulx3s-v2.0-45f-sp/initialize/jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..d39691f0cc8e593945579b840fe60410bede6a07 GIT binary patch literal 50 bcmezWA06!73=*khU|?VtU|>L({r?{TKoKe0 literal 0 HcmV?d00001 diff --git a/boards/ulx3s-v2.0-45f-sp/initialize/jump.py b/boards/ulx3s-v2.0-45f-sp/initialize/jump.py new file mode 100755 index 0000000..b1ff948 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/initialize/jump.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# Lattice ECP5 jump command generator +# TN1216 p.23 describes the jump command syntax which does not work. +# The syntax has been fixed by looking at dual boot intel hex file +# generated by diamond, this actually works. + +import struct +import sys + +# write output of this funtion at FLASH address: +# jump_command_address = 0x3FFF00 = 4194048 + +# write "golden" bitstream at FLASH address: +golden_image_address = 0x140000 +golden_image_address = int(sys.argv[1]) + +# normally both 0 +reverse_bytes = 0 +reverse_bits = 0 + +# to compare with intel HEX file generated by diamond: +# (not for normal use) +# reverse_bytes = 1 +# reverse_bits = 1 +# ./jump.py | hexdump -C + +def reverse_Bits(n, no_of_bits): + result = 0 + for i in range(no_of_bits): + result <<= 1 + result |= n & 1 + n >>= 1 + return result + +def uint8(n): + if reverse_bits: + n = reverse_Bits(n, 8) + return struct.pack(">B", n) + +def uint16(n): + if reverse_bits: + n = reverse_Bits(n, 16) + if reverse_bytes: + return struct.pack("H", n) + +def uint24(n): + if reverse_bits: + n = reverse_Bits(n, 24) + if reverse_bytes: + return struct.pack("> 8 ) + else: + return struct.pack(">HB", n >> 8, n & 0xFF ) + +def uint32(n): + if reverse_bits: + n = reverse_Bits(n, 32) + if reverse_bytes: + return struct.pack("L", n) + +packet = b'' +# Frame (START) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) +# Preamble +packet += uint16(0xBDB3) # Preamble +# Frame (Control Register 0) commented out, diamond doesn't output this +# if uncommented, jump won't work: +#packet += uint8(0xC4) # Write control register 0 command +#packet += uint24(0) # 24-bit Command Information +#packet += uint32(0) # Control Register 0 data +# This is generated by diamond: +packet += uint32(0xFFFFFFFF) # I don't know what it does but it works +# Framme (Jump Command) +#packet += uint8(0xFE) # Jump command Wrong noted in TN1216 +packet += uint8(0x7E) # Jump command generated by diamond +packet += uint24(0) # 24-bit Command Information +packet += uint8(0x03) # SPI Flash Read opcode (0x03 = regular read, 0x0B = fast read) +packet += uint24(golden_image_address) # 24-bit SPI Flash Sector X address +# Frame (END) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) + +sys.stdout.write(packet) +# print([elem.encode("hex") for elem in packet]) diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k.bit b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k.bit new file mode 120000 index 0000000..59e9556 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k.bit @@ -0,0 +1 @@ +project/project_project.bit \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.svf b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.svf new file mode 120000 index 0000000..a59752b --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.vme b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.vme new file mode 120000 index 0000000..e2f6ec2 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_128mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf new file mode 120000 index 0000000..623c0d8 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme new file mode 120000 index 0000000..bc0382a --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_micron_32mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf new file mode 120000 index 0000000..2c6afa4 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme new file mode 120000 index 0000000..9e1e580 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_multiboot_flash_spansion_64mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.svf b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.svf new file mode 120000 index 0000000..bb7617d --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.svf @@ -0,0 +1 @@ +project/project_project_sram.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.vme b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.vme new file mode 120000 index 0000000..d098048 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/tinyfpga_45k_sram.vme @@ -0,0 +1 @@ +project/project_project_sram.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-45f-sp/top/bootloader_sp_ulx3s.v b/boards/ulx3s-v2.0-45f-sp/top/bootloader_sp_ulx3s.v new file mode 100644 index 0000000..f2799ee --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/top/bootloader_sp_ulx3s.v @@ -0,0 +1,137 @@ +module bootloader_sp_ulx3s ( + input clk_25mhz, + + inout usb_fpga_dp, + inout usb_fpga_dn, + + output usb_fpga_pu_dp, + inout user_programn, + + output [7:0] led, + + input flash_miso, + output flash_mosi, + output flash_clk, + output flash_csn, + + input [6:0] btn, + output wifi_gpio0 +); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// generate 48 mhz clock + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + wire clk_200mhz; + clk_25M_200M clk_200M_inst ( + .CLKI(clk_25mhz), + .CLKOP(clk_200mhz) + ); + + wire clk_48mhz; + wire clk_ready; + clk_200M_48M clk_48M_inst ( + .CLKI(clk_200mhz), + .CLKOP(clk_48mhz), + .LOCK(clk_ready) + ); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// instantiate tinyfpga bootloader + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg [15:0] reset_counter = 0; // counter for debouce and prolong reset + wire reset; + assign reset = ~reset_counter[15]; + wire usb_p_tx; + wire usb_n_tx; + wire usb_p_rx; + wire usb_n_rx; + wire usb_tx_en; + wire pin_led; + wire [7:0] debug_led; + wire boot; + wire S_flash_clk; + wire S_flash_csn; + + tinyfpgasp_bootloader tinyfpgasp_bootloader_inst ( + .clk_48mhz(clk_48mhz), + .reset(reset), + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + .led(pin_led), + .debug_led(debug_led), + .spi_miso(flash_miso), + .spi_mosi(flash_mosi), + .spi_sck(S_flash_clk), + .spi_cs(S_flash_csn), + .boot(boot) + ); + + assign usb_fpga_dp = reset ? 1'b0 : (usb_tx_en ? usb_p_tx : 1'bz); + assign usb_fpga_dn = reset ? 1'b0 : (usb_tx_en ? usb_n_tx : 1'bz); + assign usb_p_rx = usb_tx_en ? 1'b1 : usb_fpga_dp; + assign usb_n_rx = usb_tx_en ? 1'b0 : usb_fpga_dn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Vendor-specific clock output to SPI config flash + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + USRMCLK usrmclk_inst ( + .USRMCLKI(S_flash_clk), + .USRMCLKTS(S_flash_csn) + ) /* synthesis syn_noprune=1 */; + assign flash_clk = S_flash_clk; + assign flash_csn = S_flash_csn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Debonuce and prolong RESET + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + always @(posedge clk_48mhz) + begin + if (btn[1] | ~clk_ready) + reset_counter <= 0; + else + if (reset_counter[15] == 0) + reset_counter <= reset_counter + 1; + end + + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// ULX3S board buttons and LEDs + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + assign wifi_gpio0 = btn[0]; + assign led[0] = pin_led; + assign led[1] = ~pin_led; + assign led[5] = debug_led; + assign led[7] = boot; + // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + + // PULLUP 1.5k D+ + assign usb_fpga_pu_dp = 1; + + // EXIT from BOOTLOADER + // assign user_programn = ~boot; + + +endmodule diff --git a/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_128mbit.xcf b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_128mbit.xcf new file mode 100644 index 0000000..de2a4ef --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_128mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_128mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_128mbit.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_128mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf new file mode 100644 index 0000000..7b541c2 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_32mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_32mbit.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_32mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf new file mode 100644 index 0000000..9daeac4 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_multiboot_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_spansion_64mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_sram.xcf b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_sram.xcf new file mode 100644 index 0000000..b11ed78 --- /dev/null +++ b/boards/ulx3s-v2.0-45f-sp/ulx3s_45f_sram.xcf @@ -0,0 +1,48 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5UM + LFE5U-45F + 0x41112043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + project/project_project.bit + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A + + From 7e302173d3c9341b7a7251e45deda596e39bf194 Mon Sep 17 00:00:00 2001 From: Emard Date: Sun, 26 Aug 2018 18:20:06 +0200 Subject: [PATCH 71/90] ulx3s 25k tinyfpgasp --- boards/ulx3s-v2.0-25f-sp/Makefile | 143 ++++++ boards/ulx3s-v2.0-25f-sp/bootloader.ldf | 56 +++ .../ulx3s-v2.0-25f-sp/clocks/clk_200M_48M.v | 75 +++ .../ulx3s-v2.0-25f-sp/clocks/clk_25M_200M.v | 75 +++ .../constraints/ulx3s_v17patch.lpf | 435 +++++++++++++++++ .../constraints/ulx3s_v20.lpf | 452 ++++++++++++++++++ boards/ulx3s-v2.0-25f-sp/ecp5-12f.ocd | 16 + boards/ulx3s-v2.0-25f-sp/ft2232-fpu1.ocd | 9 + .../initialize/boardmeta4MB.bin | 119 +++++ .../initialize/boardmeta8MB.bin | 58 +++ .../initialize/initialize4MB.sh | 30 ++ .../initialize/initialize8MB.sh | 31 ++ boards/ulx3s-v2.0-25f-sp/initialize/jump.bin | Bin 0 -> 50 bytes boards/ulx3s-v2.0-25f-sp/initialize/jump.py | 95 ++++ boards/ulx3s-v2.0-25f-sp/tinyfpga_25k.bit | 1 + ...pga_25k_multiboot_flash_micron_128mbit.svf | 1 + ...pga_25k_multiboot_flash_micron_128mbit.vme | 1 + ...fpga_25k_multiboot_flash_micron_32mbit.svf | 1 + ...fpga_25k_multiboot_flash_micron_32mbit.vme | 1 + ...ga_25k_multiboot_flash_spansion_64mbit.svf | 1 + ...ga_25k_multiboot_flash_spansion_64mbit.vme | 1 + .../ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.svf | 1 + .../ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.vme | 1 + .../top/bootloader_sp_ulx3s.v | 137 ++++++ .../ulx3s_25f_multiboot_micron_128mbit.xcf | 104 ++++ .../ulx3s_25f_multiboot_micron_32mbit.xcf | 104 ++++ .../ulx3s_25f_multiboot_spansion_64mbit.xcf | 104 ++++ boards/ulx3s-v2.0-25f-sp/ulx3s_25f_sram.xcf | 48 ++ 28 files changed, 2100 insertions(+) create mode 100644 boards/ulx3s-v2.0-25f-sp/Makefile create mode 100644 boards/ulx3s-v2.0-25f-sp/bootloader.ldf create mode 100644 boards/ulx3s-v2.0-25f-sp/clocks/clk_200M_48M.v create mode 100644 boards/ulx3s-v2.0-25f-sp/clocks/clk_25M_200M.v create mode 100644 boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v17patch.lpf create mode 100644 boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v20.lpf create mode 100644 boards/ulx3s-v2.0-25f-sp/ecp5-12f.ocd create mode 100644 boards/ulx3s-v2.0-25f-sp/ft2232-fpu1.ocd create mode 100644 boards/ulx3s-v2.0-25f-sp/initialize/boardmeta4MB.bin create mode 100644 boards/ulx3s-v2.0-25f-sp/initialize/boardmeta8MB.bin create mode 100755 boards/ulx3s-v2.0-25f-sp/initialize/initialize4MB.sh create mode 100755 boards/ulx3s-v2.0-25f-sp/initialize/initialize8MB.sh create mode 100644 boards/ulx3s-v2.0-25f-sp/initialize/jump.bin create mode 100755 boards/ulx3s-v2.0-25f-sp/initialize/jump.py create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k.bit create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.svf create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.vme create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.svf create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.vme create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.svf create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.vme create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.svf create mode 120000 boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.vme create mode 100644 boards/ulx3s-v2.0-25f-sp/top/bootloader_sp_ulx3s.v create mode 100644 boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf create mode 100644 boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf create mode 100644 boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf create mode 100644 boards/ulx3s-v2.0-25f-sp/ulx3s_25f_sram.xcf diff --git a/boards/ulx3s-v2.0-25f-sp/Makefile b/boards/ulx3s-v2.0-25f-sp/Makefile new file mode 100644 index 0000000..2a82391 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/Makefile @@ -0,0 +1,143 @@ + +PROJ_FILE := $(shell ls *.ldf | head -1) +PROJ_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 4) +IMPL_NAME := $(shell fgrep default_implementation ${PROJ_FILE} | cut -d'"' -f 8) +IMPL_DIR := $(shell fgrep default_strategy ${PROJ_FILE} | cut -d'"' -f 4) + +DIAMOND_BASE := /usr/local/diamond +DIAMOND_BIN := $(shell find ${DIAMOND_BASE}/ -maxdepth 2 -name bin | sort -rn | head -1) +DIAMONDC := $(shell find ${DIAMOND_BIN}/ -name diamondc) +DDTCMD := $(shell find ${DIAMOND_BIN}/ -name ddtcmd) + +# OPENOCD_BASE := ../../programmer/openocd/ulx3s/ +OPENOCD_BASE := ./ + +# name of the project as defined in project file +PROJECT = project + +# FPGA flashing device for programming +FPGA_DEVICE = LFE5U-25F + +JUNK = ${IMPL_DIR} .recovery ._Real_._Math_.vhd *.sty reportview.xml +JUNK += dummy_sym.sort project_tcl.html promote.xml +JUNK += generate_core.tcl generate_ngd.tcl msg_file.log +JUNK += project_tcr.dir + +all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf \ + + +$(PROJECT)/$(PROJECT)_$(PROJECT).bit: + echo prj_project open ${PROJ_FILE} \; prj_run Export -task Bitgen | ${DIAMONDC} + +# same file with different name required for multiboot to work +$(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + cp $< $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_25f_sram.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_25f_sram.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT).mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit -oft -int -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_25f_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_25f_flash_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 32 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_25f_multiboot_micron_32mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_25f_multiboot_micron_32mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + dd if=/dev/zero of=/tmp/zero.bit bs=1k count=300 + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 64 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_25f_multiboot_spansion_64mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_25f_multiboot_spansion_64mbit.xcf -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit + LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 128 -header \ + -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ + -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_25f_multiboot_micron_128mbit.xcf -nocompress -noheader -of $@ + +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_25f_multiboot_micron_128mbit.xcf -of $@ + +program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit + echo pgr_project open ulx3s_25f_sram.xcf \; pgr_program run | ${DIAMONDC} + +program_wifi: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/remote.ocd --file=$(OPENOCD_BASE)/ecp5-25f.ocd + +program_web: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + svfupload.py ulx3s.lan $< + +program_web_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf + svfupload.py ulx3s.lan $< + +program_ft2232: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.svf + openocd --file=$(OPENOCD_BASE)/ft2232-fpu1.ocd --file=$(OPENOCD_BASE)/ecp5-25f.ocd + +program_flea: $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + FleaFPGA-JTAG $(PROJECT)/$(PROJECT)_$(PROJECT)_sram.vme + +program_flea_flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.vme + FleaFPGA-JTAG $< + +program_flea_flash_spansion: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme + FleaFPGA-JTAG $< + +#$(PROJECT)/$(PROJECT)_$(PROJECT).jed: +# echo prj_project open ${PROJ_FILE} \; prj_run Export -task Jedecgen | ${DIAMONDC} + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -fullvme -if sparrowhawk_flash_micron_32mbit.xcf -nocompress -noheader -of $@ + +#$(PROJECT)/$(PROJECT)_$(PROJECT)_flash.svf: $(PROJECT)/$(PROJECT)_$(PROJECT).jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ + +flash: $(PROJECT)/$(PROJECT)_$(PROJECT)_flash.vme + ${PROGRAMMERC} $< + # after this, to gain access to serial port on linux + # rmmod ftdi_sio; modprobe ftdi_sio + +# example another project +#%.svf : %.jed +# ${DDTCMD} -oft -svfsingle -op "FLASH Erase,Program,Verify" -if $< -of $@ +# mv -f $@ $@.flash +# ${DDTCMD} -oft -svfsingle -revd -op "SRAM Fast Program" -if $< -of $@ +# mv -f $@ $@.sram +# ./svf_to_urjtag.pl <$@.flash | sed 's/,/./g' > $@ + +clean: + rm -rf $(JUNK) *~ diff --git a/boards/ulx3s-v2.0-25f-sp/bootloader.ldf b/boards/ulx3s-v2.0-25f-sp/bootloader.ldf new file mode 100644 index 0000000..cfc465c --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/bootloader.ldf @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-25f-sp/clocks/clk_200M_48M.v b/boards/ulx3s-v2.0-25f-sp/clocks/clk_200M_48M.v new file mode 100644 index 0000000..2e9bb80 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/clocks/clk_200M_48M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_200M_48M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 200.00 -fclkop 48.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_200M_48M/clk_200M_48M.fdc */ +/* Wed Jul 11 00:10:22 2018 */ + + +`timescale 1 ns / 1 ps +module clk_200M_48M (CLKI, CLKOP, LOCK)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + output wire LOCK; + + wire REFCLK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 11 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 12 ; + defparam PLLInst_0.CLKFB_DIV = 6 ; + defparam PLLInst_0.CLKI_DIV = 25 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="48.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="200.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 48.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 200.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-25f-sp/clocks/clk_25M_200M.v b/boards/ulx3s-v2.0-25f-sp/clocks/clk_25M_200M.v new file mode 100644 index 0000000..0ce5c18 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/clocks/clk_25M_200M.v @@ -0,0 +1,75 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1 */ +/* Module Version: 5.7 */ +/* /mt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n clk_25M_200M -lang verilog -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 25.00 -fclkop 200.00 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /home/guest/src/fpga/usbserial-core/TinyFPGA-Bootloader/boards/ulx3s/clock/clk_25M_200M/clk_25M_200M.fdc */ +/* Wed Jul 11 00:09:44 2018 */ + + +`timescale 1 ns / 1 ps +module clk_25M_200M (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */; + input wire CLKI; + output wire CLKOP; + + wire REFCLK; + wire LOCK; + wire CLKOP_t; + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam PLLInst_0.PLLRST_ENA = "DISABLED" ; + defparam PLLInst_0.INTFB_WAKE = "DISABLED" ; + defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ; + defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ; + defparam PLLInst_0.CLKOS3_FPHASE = 0 ; + defparam PLLInst_0.CLKOS3_CPHASE = 0 ; + defparam PLLInst_0.CLKOS2_FPHASE = 0 ; + defparam PLLInst_0.CLKOS2_CPHASE = 0 ; + defparam PLLInst_0.CLKOS_FPHASE = 0 ; + defparam PLLInst_0.CLKOS_CPHASE = 0 ; + defparam PLLInst_0.CLKOP_FPHASE = 0 ; + defparam PLLInst_0.CLKOP_CPHASE = 2 ; + defparam PLLInst_0.PLL_LOCK_MODE = 0 ; + defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ; + defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ; + defparam PLLInst_0.CLKOP_TRIM_POL = "FALLING" ; + defparam PLLInst_0.OUTDIVIDER_MUXD = "DIVD" ; + defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXC = "DIVC" ; + defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXB = "DIVB" ; + defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ; + defparam PLLInst_0.OUTDIVIDER_MUXA = "DIVA" ; + defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ; + defparam PLLInst_0.CLKOS3_DIV = 1 ; + defparam PLLInst_0.CLKOS2_DIV = 1 ; + defparam PLLInst_0.CLKOS_DIV = 1 ; + defparam PLLInst_0.CLKOP_DIV = 3 ; + defparam PLLInst_0.CLKFB_DIV = 8 ; + defparam PLLInst_0.CLKI_DIV = 1 ; + defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ; + EHXPLLL PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo), + .PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo), + .PHASELOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo), + .RST(scuba_vlo), .ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo), + .ENCLKOS3(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(), + .LOCK(LOCK), .INTLOCK(), .REFCLK(REFCLK), .CLKINTFB()) + /* synthesis FREQUENCY_PIN_CLKOP="200.000000" */ + /* synthesis FREQUENCY_PIN_CLKI="25.000000" */ + /* synthesis ICP_CURRENT="5" */ + /* synthesis LPF_RESISTOR="16" */; + + assign CLKOP = CLKOP_t; + + + // exemplar begin + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 200.000000 + // exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 25.000000 + // exemplar attribute PLLInst_0 ICP_CURRENT 5 + // exemplar attribute PLLInst_0 LPF_RESISTOR 16 + // exemplar end + +endmodule diff --git a/boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v17patch.lpf b/boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v17patch.lpf new file mode 100644 index 0000000..8e0d34c --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v17patch.lpf @@ -0,0 +1,435 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v1.7 patched towards v1.8 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "W1"; # UP +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "Y2"; # RIGHT +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "J1"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J3"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "K2"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "K1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "H2"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "H1"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; +LOCATE COMP "wifi_gpio17" SITE "N3"; +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Read + +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_clkp" SITE "A17"; # Clock + +LOCATE COMP "gpdi_clkn" SITE "B18"; # Clock - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "C12"; # I2C shared with RTC +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_clkn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "D15"; # J2_25+ GP22 +LOCATE COMP "gn[22]" SITE "E15"; # J2_25- GN22 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "B15"; # J2_31+ GP25 +LOCATE COMP "gn[25]" SITE "C15"; # J2_31- GN25 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v20.lpf b/boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v20.lpf new file mode 100644 index 0000000..29907ed --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/constraints/ulx3s_v20.lpf @@ -0,0 +1,452 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +## ULX3S v2.0 and v2.1 + +# The clock "usb" and "gpdi" sheet +LOCATE COMP "clk_25mhz" SITE "G2"; +IOBUF PORT "clk_25mhz" PULLMODE=NONE IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk_25mhz" 25 MHZ; + +# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash +SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; + +## USBSERIAL FTDI-FPGA serial port "usb" sheet +LOCATE COMP "ftdi_rxd" SITE "L4"; # FPGA transmits to ftdi +LOCATE COMP "ftdi_txd" SITE "M1"; # FPGA receives from ftdi +LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives +LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives +LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives +IOBUF PORT "ftdi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "ftdi_txd" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33; +IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33; + +## LED indicators "blinkey" and "gpio" sheet +LOCATE COMP "led[7]" SITE "H3"; +LOCATE COMP "led[6]" SITE "E1"; +LOCATE COMP "led[5]" SITE "E2"; +LOCATE COMP "led[4]" SITE "D1"; +LOCATE COMP "led[3]" SITE "D2"; +LOCATE COMP "led[2]" SITE "C1"; +LOCATE COMP "led[1]" SITE "C2"; +LOCATE COMP "led[0]" SITE "B2"; +IOBUF PORT "led[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "led[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet +LOCATE COMP "btn[0]" SITE "D6"; # BTN_PWRn (inverted logic) +LOCATE COMP "btn[1]" SITE "R1"; # FIRE1 +LOCATE COMP "btn[2]" SITE "T1"; # FIRE2 +LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18 +LOCATE COMP "btn[4]" SITE "V1"; # DOWN +LOCATE COMP "btn[5]" SITE "U1"; # LEFT +LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16 +IOBUF PORT "btn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## DIP switch "blinkey", "gpio" sheet +LOCATE COMP "sw[0]" SITE "E8"; # SW1 +LOCATE COMP "sw[1]" SITE "D8"; # SW2 +LOCATE COMP "sw[2]" SITE "D7"; # SW3 +LOCATE COMP "sw[3]" SITE "E7"; # SW4 +IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet +LOCATE COMP "oled_clk" SITE "P4"; +LOCATE COMP "oled_mosi" SITE "P3"; +LOCATE COMP "oled_dc" SITE "P1"; +LOCATE COMP "oled_resn" SITE "P2"; +LOCATE COMP "oled_csn" SITE "N2"; +IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SPI Flash chip "flash" sheet +LOCATE COMP "flash_csn" SITE "R2"; +LOCATE COMP "flash_clk" SITE "U3"; +LOCATE COMP "flash_mosi" SITE "W2"; +LOCATE COMP "flash_miso" SITE "V2"; +LOCATE COMP "flash_holdn" SITE "W1"; +LOCATE COMP "flash_wpn" SITE "Y2"; +#LOCATE COMP "flash_csspin" SITE "AJ3"; +#LOCATE COMP "flash_initn" SITE "AG4"; +#LOCATE COMP "flash_done" SITE "AJ4"; +#LOCATE COMP "flash_programn" SITE "AH4"; +#LOCATE COMP "flash_cfg_select[0]" SITE "AM4"; +#LOCATE COMP "flash_cfg_select[1]" SITE "AL4"; +#LOCATE COMP "flash_cfg_select[2]" SITE "AK4"; +IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; + +## SD card "sdcard", "usb" sheet +LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14 +LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15 +LOCATE COMP "sd_d[0]" SITE "J3"; # sd_dat0_do (MISO) WiFi GPIO2 +LOCATE COMP "sd_d[1]" SITE "H1"; # sd_dat1_irq WiFi GPIO4 +LOCATE COMP "sd_d[2]" SITE "K1"; # sd_dat2 WiFi_GPIO12 +LOCATE COMP "sd_d[3]" SITE "K2"; # sd_dat3_csn WiFi_GPIO13 +LOCATE COMP "sd_wp" SITE "P5"; # not connected +LOCATE COMP "sd_cdn" SITE "N5"; # not connected +IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping requirement +IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## ADC SPI (MAX11123) "analog", "ram" sheet +LOCATE COMP "adc_csn" SITE "R17"; +LOCATE COMP "adc_mosi" SITE "R16"; +LOCATE COMP "adc_miso" SITE "U16"; +LOCATE COMP "adc_sclk" SITE "P17"; +IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## Audio 4-bit DAC "analog", "gpio" sheet +# 4-bit mode can drive down to 75 ohm load impedance. +# Lower impedance leads to IO overload, +# FPGA will stop working and need reboot. +# For standard 17 ohm earphones: +# use bits 2,3 as input (High-Z) and drive only bits 0,1. +LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio) +LOCATE COMP "audio_l[2]" SITE "C3"; +LOCATE COMP "audio_l[1]" SITE "D3"; +LOCATE COMP "audio_l[0]" SITE "E4"; +LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio) +LOCATE COMP "audio_r[2]" SITE "D5"; +LOCATE COMP "audio_r[1]" SITE "B5"; +LOCATE COMP "audio_r[0]" SITE "A3"; +LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio) +LOCATE COMP "audio_v[2]" SITE "F5"; +LOCATE COMP "audio_v[1]" SITE "F2"; +LOCATE COMP "audio_v[0]" SITE "H5"; +IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## WiFi ESP-32 "wifi", "usb", "flash" sheet +# other pins are shared with GP/GN, SD card and JTAG +LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi +LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi +LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi +LOCATE COMP "wifi_gpio0" SITE "L2"; +LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED +LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX +LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX +# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active +IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PCB antenna 433 MHz (may be also used for FM) "usb" sheet +LOCATE COMP "ant_433mhz" SITE "G1"; +IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +## Second USB port "US2" going directly into FPGA "usb", "ram" sheet +LOCATE COMP "usb_fpga_dp" SITE "E16"; # single ended or differential input only +LOCATE COMP "usb_fpga_dn" SITE "F16"; +IOBUF PORT "usb_fpga_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # differential bidirectional +LOCATE COMP "usb_fpga_bd_dn" SITE "E15"; +IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=4; +LOCATE COMP "usb_fpga_pu_dp" SITE "B12"; # pull up/down control +LOCATE COMP "usb_fpga_pu_dn" SITE "C12"; +IOBUF PORT "usb_fpga_pu_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; +IOBUF PORT "usb_fpga_pu_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16; + +## JTAG ESP-32 "usb" sheet +# connected to FT231X and ESP-32 +# commented out because those are dedicated pins, not directly useable as GPIO +# but could be used by some vendor-specific JTAG bridging (boundary scan) module +#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives +#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits +#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives +#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives +#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SDRAM "ram" sheet +LOCATE COMP "sdram_clk" SITE "F19"; +LOCATE COMP "sdram_cke" SITE "F20"; +LOCATE COMP "sdram_csn" SITE "P20"; +LOCATE COMP "sdram_wen" SITE "T20"; +LOCATE COMP "sdram_rasn" SITE "R20"; +LOCATE COMP "sdram_casn" SITE "T19"; +LOCATE COMP "sdram_a[0]" SITE "M20"; +LOCATE COMP "sdram_a[1]" SITE "M19"; +LOCATE COMP "sdram_a[2]" SITE "L20"; +LOCATE COMP "sdram_a[3]" SITE "L19"; +LOCATE COMP "sdram_a[4]" SITE "K20"; +LOCATE COMP "sdram_a[5]" SITE "K19"; +LOCATE COMP "sdram_a[6]" SITE "K18"; +LOCATE COMP "sdram_a[7]" SITE "J20"; +LOCATE COMP "sdram_a[8]" SITE "J19"; +LOCATE COMP "sdram_a[9]" SITE "H20"; +LOCATE COMP "sdram_a[10]" SITE "N19"; +LOCATE COMP "sdram_a[11]" SITE "G20"; +LOCATE COMP "sdram_a[12]" SITE "G19"; +LOCATE COMP "sdram_ba[0]" SITE "P19"; +LOCATE COMP "sdram_ba[1]" SITE "N20"; +LOCATE COMP "sdram_dqm[0]" SITE "U19"; +LOCATE COMP "sdram_dqm[1]" SITE "E20"; +LOCATE COMP "sdram_d[0]" SITE "J16"; +LOCATE COMP "sdram_d[1]" SITE "L18"; +LOCATE COMP "sdram_d[2]" SITE "M18"; +LOCATE COMP "sdram_d[3]" SITE "N18"; +LOCATE COMP "sdram_d[4]" SITE "P18"; +LOCATE COMP "sdram_d[5]" SITE "T18"; +LOCATE COMP "sdram_d[6]" SITE "T17"; +LOCATE COMP "sdram_d[7]" SITE "U20"; +LOCATE COMP "sdram_d[8]" SITE "E19"; +LOCATE COMP "sdram_d[9]" SITE "D20"; +LOCATE COMP "sdram_d[10]" SITE "D19"; +LOCATE COMP "sdram_d[11]" SITE "C20"; +LOCATE COMP "sdram_d[12]" SITE "E18"; +LOCATE COMP "sdram_d[13]" SITE "F18"; +LOCATE COMP "sdram_d[14]" SITE "J18"; +LOCATE COMP "sdram_d[15]" SITE "J17"; +IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; + +# GPDI differential interface (Video) "gpdi" sheet +LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue + +LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue - +LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green + +LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green - +LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red + +LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red - +LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock + +LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock - +LOCATE COMP "gpdi_ethp" SITE "A19"; # Ethernet + +LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet - +LOCATE COMP "gpdi_cec" SITE "A18"; +LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC +LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12 +IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4; +IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet +# Pins enumerated gp[0-27], gn[0-27]. +# With differential mode enabled on Lattice, +# gp[] (+) are used, gn[] (-) are ignored from design +# as they handle inverted signal by default. +# To enable differential, rename LVCMOS33->LVCMOS33D +LOCATE COMP "gp[0]" SITE "B11"; # J1_5+ GP0 +LOCATE COMP "gn[0]" SITE "C11"; # J1_5- GN0 +LOCATE COMP "gp[1]" SITE "A10"; # J1_7+ GP1 +LOCATE COMP "gn[1]" SITE "A11"; # J1_7- GN1 +LOCATE COMP "gp[2]" SITE "A9"; # J1_9+ GP2 +LOCATE COMP "gn[2]" SITE "B10"; # J1_9- GN2 +LOCATE COMP "gp[3]" SITE "B9"; # J1_11+ GP3 +LOCATE COMP "gn[3]" SITE "C10"; # J1_11- GN3 +LOCATE COMP "gp[4]" SITE "A7"; # J1_13+ GP4 +LOCATE COMP "gn[4]" SITE "A8"; # J1_13- GN4 +LOCATE COMP "gp[5]" SITE "C8"; # J1_15+ GP5 +LOCATE COMP "gn[5]" SITE "B8"; # J1_15- GN5 +LOCATE COMP "gp[6]" SITE "C6"; # J1_17+ GP6 +LOCATE COMP "gn[6]" SITE "C7"; # J1_17- GN6 +IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[7]" SITE "A6"; # J1_23+ GP7 +LOCATE COMP "gn[7]" SITE "B6"; # J1_23- GN7 +LOCATE COMP "gp[8]" SITE "A4"; # J1_25+ GP8 +LOCATE COMP "gn[8]" SITE "A5"; # J1_25- GN8 +LOCATE COMP "gp[9]" SITE "A2"; # J1_27+ GP9 +LOCATE COMP "gn[9]" SITE "B1"; # J1_27- GN9 +LOCATE COMP "gp[10]" SITE "C4"; # J1_29+ GP10 WIFI_GPIO27 +LOCATE COMP "gn[10]" SITE "B4"; # J1_29- GN10 +LOCATE COMP "gp[11]" SITE "F4"; # J1_31+ GP11 WIFI_GPIO25 +LOCATE COMP "gn[11]" SITE "E3"; # J1_31- GN11 WIFI_GPIO26 +LOCATE COMP "gp[12]" SITE "G3"; # J1_33+ GP12 WIFI_GPIO32 +LOCATE COMP "gn[12]" SITE "F3"; # J1_33- GN12 WIFI_GPIO33 +LOCATE COMP "gp[13]" SITE "H4"; # J1_35+ GP13 WIFI_GPIO34 +LOCATE COMP "gn[13]" SITE "G5"; # J1_35- GN13 WIFI_GPIO35 +IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[14]" SITE "U18"; # J2_5+ GP14 +LOCATE COMP "gn[14]" SITE "U17"; # J2_5- GN14 +LOCATE COMP "gp[15]" SITE "N17"; # J2_7+ GP15 +LOCATE COMP "gn[15]" SITE "P16"; # J2_7- GN15 +LOCATE COMP "gp[16]" SITE "N16"; # J2_9+ GP16 +LOCATE COMP "gn[16]" SITE "M17"; # J2_9- GN16 +LOCATE COMP "gp[17]" SITE "L16"; # J2_11+ GP17 +LOCATE COMP "gn[17]" SITE "L17"; # J2_11- GN17 +LOCATE COMP "gp[18]" SITE "H18"; # J2_13+ GP18 +LOCATE COMP "gn[18]" SITE "H17"; # J2_13- GN18 +LOCATE COMP "gp[19]" SITE "F17"; # J2_15+ GP19 +LOCATE COMP "gn[19]" SITE "G18"; # J2_15- GN19 +LOCATE COMP "gp[20]" SITE "D18"; # J2_17+ GP20 +LOCATE COMP "gn[20]" SITE "E17"; # J2_17- GN20 +IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +LOCATE COMP "gp[21]" SITE "C18"; # J2_23+ GP21 +LOCATE COMP "gn[21]" SITE "D17"; # J2_23- GN21 +LOCATE COMP "gp[22]" SITE "B15"; # J2_25+ GP22 D15->B15 +LOCATE COMP "gn[22]" SITE "C15"; # J2_25- GN22 E15->C15 +LOCATE COMP "gp[23]" SITE "B17"; # J2_27+ GP23 +LOCATE COMP "gn[23]" SITE "C17"; # J2_27- GN23 +LOCATE COMP "gp[24]" SITE "C16"; # J2_29+ GP24 +LOCATE COMP "gn[24]" SITE "D16"; # J2_29- GN24 +LOCATE COMP "gp[25]" SITE "D14"; # J2_31+ GP25 B15->D14 +LOCATE COMP "gn[25]" SITE "E14"; # J2_31- GN25 C15->E14 +LOCATE COMP "gp[26]" SITE "B13"; # J2_33+ GP26 +LOCATE COMP "gn[26]" SITE "C13"; # J2_33- GN26 +LOCATE COMP "gp[27]" SITE "D13"; # J2_35+ GP27 +LOCATE COMP "gn[27]" SITE "E13"; # J2_35- GN27 +IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; +IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## PROGRAMN (reload bitstream from FLASH, exit from bootloader) +# PCB v2.0.5 and higher +LOCATE COMP "user_programn" SITE "M4"; +IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; + +## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) +# on PCB v1.7 shutdown is not connected to FPGA +LOCATE COMP "shutdown" SITE "G16"; # FPGA receives +IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/boards/ulx3s-v2.0-25f-sp/ecp5-12f.ocd b/boards/ulx3s-v2.0-25f-sp/ecp5-12f.ocd new file mode 100644 index 0000000..d578c69 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/ecp5-12f.ocd @@ -0,0 +1,16 @@ +# ecp3.cfg +# OpenOCD commands + +telnet_port 4444 +gdb_port 3333 + +# JTAG TAPs +jtag newtap lfe5u12 tap -expected-id 0x21111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u25 tap -expected-id 0x41111043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u45 tap -expected-id 0x41112043 -irlen 8 -irmask 0xFF -ircapture 0x5 +#jtag newtap lfe5u85 tap -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 + +init +scan_chain +svf -tap lfe5u12.tap project/project_project_sram.svf +shutdown diff --git a/boards/ulx3s-v2.0-25f-sp/ft2232-fpu1.ocd b/boards/ulx3s-v2.0-25f-sp/ft2232-fpu1.ocd new file mode 100644 index 0000000..6c41311 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/ft2232-fpu1.ocd @@ -0,0 +1,9 @@ +# +# PLDkit FPU1 JTAG Programmer +# + +interface ftdi +ftdi_device_desc "FPU1 JTAG Programmer" +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x3088 0x1f8b +adapter_khz 25000 diff --git a/boards/ulx3s-v2.0-25f-sp/initialize/boardmeta4MB.bin b/boards/ulx3s-v2.0-25f-sp/initialize/boardmeta4MB.bin new file mode 100644 index 0000000..7a525c7 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/initialize/boardmeta4MB.bin @@ -0,0 +1,119 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x2FFFFF", + "userdata": "0x300000-0x3FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-25f-sp/initialize/boardmeta8MB.bin b/boards/ulx3s-v2.0-25f-sp/initialize/boardmeta8MB.bin new file mode 100644 index 0000000..89be03c --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/initialize/boardmeta8MB.bin @@ -0,0 +1,58 @@ +{ + "boardmeta": + { + "name": "ULX3S", + "fpga": "LFE5U-45F-6BG381C", + "hver": "1.7", + "uuid": "00000000-0000-0000-0000-000000000000", + "serial": 12345 + }, + "bootmeta": + { + "bootloader": "TinyFPGA USB Bootloader", + "bver": "2.0.0", + "update": "https://github.com/emard/TinyFPGA-Bootloader", + "addrmap": + { + "bootloader": "0x000000-0x0FFFFF", + "golden": "0x100000-0x1FFFFF", + "userimage": "0x200000-0x3FFFFF", + "userdata": "0x500000-0x7FBFFF" + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/ulx3s-v2.0-25f-sp/initialize/initialize4MB.sh b/boards/ulx3s-v2.0-25f-sp/initialize/initialize4MB.sh new file mode 100755 index 0000000..3d67d93 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/initialize/initialize4MB.sh @@ -0,0 +1,30 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x3FF000) # flash size - 0x1000 +jump_command_address=$(printf "%d" 0x3FFF00) # flash size - 0x100 + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta4MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-25f-sp/initialize/initialize8MB.sh b/boards/ulx3s-v2.0-25f-sp/initialize/initialize8MB.sh new file mode 100755 index 0000000..b127f53 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/initialize/initialize8MB.sh @@ -0,0 +1,31 @@ +#!/bin/sh -e + +# Initializer for ECP5 dual boot. + +# first half of the FLASH is for user bitstram +# bootloader bitstream starts at second half of the FLASH +# board metadata at last 0x1000 bytes +# Jump command at last 0x100 bytes + +# flash size: 8 Mbit = 1 MB = 0x100000 +# flash size: 16 Mbit = 2 MB = 0x200000 +# flash size: 32 Mbit = 4 MB = 0x400000 +# flash size: 64 Mbit = 8 MB = 0x800000 +# flash size: 128 Mbit = 16 MB = 0x1000000 + +bootloader_image_address=$(printf "%d" 0x000000) # 0 +golden_image_address=$(printf "%d" 0x100000) # 0x100000 (1MB) (backup of bootloader) +board_meta_address=$(printf "%d" 0x7FF000) # flash size - 0x1000 (-4KB) +jump_command_address=$(printf "%d" 0x7FFF00) # flash size - 0x100 (-256) + +# primary image must be generated by diamond deployment tool (ddtcmd) +# simply overwriting bootloader image will not have multiboot capability +#tinyprog --pyserial --no-boot -a $bootloader_image_address -u ../../boards/ulx3s-v1.7-45f/tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $golden_image_address -u ../tinyfpga_45k.bit +tinyprog --pyserial --no-boot -a $(printf "%d" $board_meta_address) -u boardmeta8MB.bin +./jump.py $golden_image_address > jump.bin +tinyprog --pyserial --no-boot -a $(printf "%d" $jump_command_address) -u jump.bin +# hexdump -C jump.bin +# check that's board is recognized by tingprog +tinyprog --pyserial -l +#tinyprog -m diff --git a/boards/ulx3s-v2.0-25f-sp/initialize/jump.bin b/boards/ulx3s-v2.0-25f-sp/initialize/jump.bin new file mode 100644 index 0000000000000000000000000000000000000000..d39691f0cc8e593945579b840fe60410bede6a07 GIT binary patch literal 50 bcmezWA06!73=*khU|?VtU|>L({r?{TKoKe0 literal 0 HcmV?d00001 diff --git a/boards/ulx3s-v2.0-25f-sp/initialize/jump.py b/boards/ulx3s-v2.0-25f-sp/initialize/jump.py new file mode 100755 index 0000000..b1ff948 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/initialize/jump.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# Lattice ECP5 jump command generator +# TN1216 p.23 describes the jump command syntax which does not work. +# The syntax has been fixed by looking at dual boot intel hex file +# generated by diamond, this actually works. + +import struct +import sys + +# write output of this funtion at FLASH address: +# jump_command_address = 0x3FFF00 = 4194048 + +# write "golden" bitstream at FLASH address: +golden_image_address = 0x140000 +golden_image_address = int(sys.argv[1]) + +# normally both 0 +reverse_bytes = 0 +reverse_bits = 0 + +# to compare with intel HEX file generated by diamond: +# (not for normal use) +# reverse_bytes = 1 +# reverse_bits = 1 +# ./jump.py | hexdump -C + +def reverse_Bits(n, no_of_bits): + result = 0 + for i in range(no_of_bits): + result <<= 1 + result |= n & 1 + n >>= 1 + return result + +def uint8(n): + if reverse_bits: + n = reverse_Bits(n, 8) + return struct.pack(">B", n) + +def uint16(n): + if reverse_bits: + n = reverse_Bits(n, 16) + if reverse_bytes: + return struct.pack("H", n) + +def uint24(n): + if reverse_bits: + n = reverse_Bits(n, 24) + if reverse_bytes: + return struct.pack("> 8 ) + else: + return struct.pack(">HB", n >> 8, n & 0xFF ) + +def uint32(n): + if reverse_bits: + n = reverse_Bits(n, 32) + if reverse_bytes: + return struct.pack("L", n) + +packet = b'' +# Frame (START) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) +# Preamble +packet += uint16(0xBDB3) # Preamble +# Frame (Control Register 0) commented out, diamond doesn't output this +# if uncommented, jump won't work: +#packet += uint8(0xC4) # Write control register 0 command +#packet += uint24(0) # 24-bit Command Information +#packet += uint32(0) # Control Register 0 data +# This is generated by diamond: +packet += uint32(0xFFFFFFFF) # I don't know what it does but it works +# Framme (Jump Command) +#packet += uint8(0xFE) # Jump command Wrong noted in TN1216 +packet += uint8(0x7E) # Jump command generated by diamond +packet += uint24(0) # 24-bit Command Information +packet += uint8(0x03) # SPI Flash Read opcode (0x03 = regular read, 0x0B = fast read) +packet += uint24(golden_image_address) # 24-bit SPI Flash Sector X address +# Frame (END) 18 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint32(0xFFFFFFFF) # 4 dummy bytes +packet += uint16(0xFFFF) # 2 dummy bytes (diamond generates this 2 bytes more) + +sys.stdout.write(packet) +# print([elem.encode("hex") for elem in packet]) diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k.bit b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k.bit new file mode 120000 index 0000000..59e9556 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k.bit @@ -0,0 +1 @@ +project/project_project.bit \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.svf b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.svf new file mode 120000 index 0000000..a59752b --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.vme b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.vme new file mode 120000 index 0000000..e2f6ec2 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_128mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_128mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.svf b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.svf new file mode 120000 index 0000000..623c0d8 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.vme b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.vme new file mode 120000 index 0000000..bc0382a --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_micron_32mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_micron_32mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.svf b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.svf new file mode 120000 index 0000000..2c6afa4 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.svf @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.vme b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.vme new file mode 120000 index 0000000..9e1e580 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_multiboot_flash_spansion_64mbit.vme @@ -0,0 +1 @@ +project/project_project_multiboot_flash_spansion_64mbit.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.svf b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.svf new file mode 120000 index 0000000..bb7617d --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.svf @@ -0,0 +1 @@ +project/project_project_sram.svf \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.vme b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.vme new file mode 120000 index 0000000..d098048 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/tinyfpga_25k_sram.vme @@ -0,0 +1 @@ +project/project_project_sram.vme \ No newline at end of file diff --git a/boards/ulx3s-v2.0-25f-sp/top/bootloader_sp_ulx3s.v b/boards/ulx3s-v2.0-25f-sp/top/bootloader_sp_ulx3s.v new file mode 100644 index 0000000..f2799ee --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/top/bootloader_sp_ulx3s.v @@ -0,0 +1,137 @@ +module bootloader_sp_ulx3s ( + input clk_25mhz, + + inout usb_fpga_dp, + inout usb_fpga_dn, + + output usb_fpga_pu_dp, + inout user_programn, + + output [7:0] led, + + input flash_miso, + output flash_mosi, + output flash_clk, + output flash_csn, + + input [6:0] btn, + output wifi_gpio0 +); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// generate 48 mhz clock + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + wire clk_200mhz; + clk_25M_200M clk_200M_inst ( + .CLKI(clk_25mhz), + .CLKOP(clk_200mhz) + ); + + wire clk_48mhz; + wire clk_ready; + clk_200M_48M clk_48M_inst ( + .CLKI(clk_200mhz), + .CLKOP(clk_48mhz), + .LOCK(clk_ready) + ); + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// instantiate tinyfpga bootloader + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + reg [15:0] reset_counter = 0; // counter for debouce and prolong reset + wire reset; + assign reset = ~reset_counter[15]; + wire usb_p_tx; + wire usb_n_tx; + wire usb_p_rx; + wire usb_n_rx; + wire usb_tx_en; + wire pin_led; + wire [7:0] debug_led; + wire boot; + wire S_flash_clk; + wire S_flash_csn; + + tinyfpgasp_bootloader tinyfpgasp_bootloader_inst ( + .clk_48mhz(clk_48mhz), + .reset(reset), + .usb_p_tx(usb_p_tx), + .usb_n_tx(usb_n_tx), + .usb_p_rx(usb_p_rx), + .usb_n_rx(usb_n_rx), + .usb_tx_en(usb_tx_en), + .led(pin_led), + .debug_led(debug_led), + .spi_miso(flash_miso), + .spi_mosi(flash_mosi), + .spi_sck(S_flash_clk), + .spi_cs(S_flash_csn), + .boot(boot) + ); + + assign usb_fpga_dp = reset ? 1'b0 : (usb_tx_en ? usb_p_tx : 1'bz); + assign usb_fpga_dn = reset ? 1'b0 : (usb_tx_en ? usb_n_tx : 1'bz); + assign usb_p_rx = usb_tx_en ? 1'b1 : usb_fpga_dp; + assign usb_n_rx = usb_tx_en ? 1'b0 : usb_fpga_dn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Vendor-specific clock output to SPI config flash + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + USRMCLK usrmclk_inst ( + .USRMCLKI(S_flash_clk), + .USRMCLKTS(S_flash_csn) + ) /* synthesis syn_noprune=1 */; + assign flash_clk = S_flash_clk; + assign flash_csn = S_flash_csn; + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// Debonuce and prolong RESET + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + always @(posedge clk_48mhz) + begin + if (btn[1] | ~clk_ready) + reset_counter <= 0; + else + if (reset_counter[15] == 0) + reset_counter <= reset_counter + 1; + end + + + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + //////// + //////// ULX3S board buttons and LEDs + //////// + //////////////////////////////////////////////////////////////////////////////// + //////////////////////////////////////////////////////////////////////////////// + assign wifi_gpio0 = btn[0]; + assign led[0] = pin_led; + assign led[1] = ~pin_led; + assign led[5] = debug_led; + assign led[7] = boot; + // assign led[3:0] = {flash_miso, flash_mosi, S_flash_clk, S_flash_csn}; + + // PULLUP 1.5k D+ + assign usb_fpga_pu_dp = 1; + + // EXIT from BOOTLOADER + // assign user_programn = ~boot; + + +endmodule diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf new file mode 100644 index 0000000..7a080a6 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_128mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41111043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_128mbit.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_128mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf new file mode 100644 index 0000000..d7f82bb --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_micron_32mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41111043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + Micron + SPI Serial Flash + SPI-M25P128 + 0x15 + 8-pin VDFPN8 + SPI Flash Erase,Program + project/project_project_multiboot_flash_micron_32mbit.mcs + 0x00000000 + 0x01000000 + 128 + 16777216 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_micron_32mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf new file mode 100644 index 0000000..7aa952f --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf @@ -0,0 +1,104 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-45F + All + + 8 + 11111111 + 1 + 0 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + 12/23/17 00:34:50 + SPI Flash Erase,Program + + + + + 1 + Lattice + ECP5U + LFE5U-45F + 0x41111043 + All + LFE5U-45F + + 8 + 11111111 + 1 + 0 + + /mt/lattice/diamond/3.7_x64/data/vmdata/database/xpga/ecp5/LFE5U-45F.msk + Bypass + + + + + + 1 + SPANSION + SPI Serial Flash + SPI-S25FL164K + 0x16 + 8-lead SOIC + SPI Flash Erase,Program + project/project_project_multiboot_flash_spansion_64mbit.mcs + 0x00000000 + 0x00800000 + 64 + 8388608 + 1 + + + + + + 1 + + project/project_project_multiboot_flash_spansion_64mbit.mcs + + + + + + + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + FPU1 JTAG PROGRAMMER A Location 0000 Serial FPU1 JTAG Programmer A + + diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_sram.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_sram.xcf new file mode 100644 index 0000000..dd6a770 --- /dev/null +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_sram.xcf @@ -0,0 +1,48 @@ + + + + + + JTAG + + + 1 + Lattice + ECP5U + LFE5U-25F + 0x41111043 + All + LFE5U-25F + + 8 + 11111111 + 1 + 0 + + project/project_project.bit + Fast Program + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB2 + FTUSB-0 + DUAL RS232-HS A Location 0000 Serial Dual RS232-HS A + + From 600b434375e88784930c7574871f05d0541030bd Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 12 Sep 2018 14:28:41 +0200 Subject: [PATCH 72/90] ulx3s 25F fix flashing 128-mbit ISSI flash --- .../ulx3s_25f_multiboot_micron_128mbit.xcf | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf index 7a080a6..abdc554 100644 --- a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_128mbit.xcf @@ -9,7 +9,7 @@ 1 Lattice ECP5U - LFE5U-45F + LFE5U-25F All 8 @@ -30,10 +30,10 @@ 1 Lattice ECP5U - LFE5U-45F + LFE5U-25F 0x41111043 All - LFE5U-45F + LFE5U-25F 8 11111111 @@ -54,11 +54,11 @@ 1 - Micron + SPANSION SPI Serial Flash - SPI-M25P128 - 0x15 - 8-pin VDFPN8 + SPI-S25FL128S + 0x17 + 8-lead WSON SPI Flash Erase,Program project/project_project_multiboot_flash_micron_128mbit.mcs 0x00000000 From 286966d990c0f9aec38ed12c8175466acc4161c0 Mon Sep 17 00:00:00 2001 From: Emard Date: Wed, 12 Sep 2018 14:29:09 +0200 Subject: [PATCH 73/90] ulx3s 25F correct chip name 45F->25F --- .../ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf | 6 +++--- .../ulx3s_25f_multiboot_spansion_64mbit.xcf | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf index d7f82bb..7b84b66 100644 --- a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_micron_32mbit.xcf @@ -9,7 +9,7 @@ 1 Lattice ECP5U - LFE5U-45F + LFE5U-25F All 8 @@ -30,10 +30,10 @@ 1 Lattice ECP5U - LFE5U-45F + LFE5U-25F 0x41111043 All - LFE5U-45F + LFE5U-25F 8 11111111 diff --git a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf index 7aa952f..47468f5 100644 --- a/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf +++ b/boards/ulx3s-v2.0-25f-sp/ulx3s_25f_multiboot_spansion_64mbit.xcf @@ -9,7 +9,7 @@ 1 Lattice ECP5U - LFE5U-45F + LFE5U-25F All 8 @@ -30,10 +30,10 @@ 1 Lattice ECP5U - LFE5U-45F + LFE5U-25F 0x41111043 All - LFE5U-45F + LFE5U-25F 8 11111111 From d9438e973d66c836bde54661b481395464dfc69a Mon Sep 17 00:00:00 2001 From: Emard Date: Fri, 14 Sep 2018 08:51:59 +0200 Subject: [PATCH 74/90] ulx3s 85f issi is25lp128f flasher with verify (slow) --- boards/ulx3s-v2.0-85f-sp/Makefile | 14 ++++++------- ...xcf => ulx3s_85f_multiboot_is25lp128f.xcf} | 20 +++++++++---------- 2 files changed, 17 insertions(+), 17 deletions(-) rename boards/ulx3s-v2.0-85f-sp/{ulx3s_85f_multiboot_micron_128mbit.xcf => ulx3s_85f_multiboot_is25lp128f.xcf} (83%) diff --git a/boards/ulx3s-v2.0-85f-sp/Makefile b/boards/ulx3s-v2.0-85f-sp/Makefile index fac64b1..37bb2b1 100644 --- a/boards/ulx3s-v2.0-85f-sp/Makefile +++ b/boards/ulx3s-v2.0-85f-sp/Makefile @@ -30,8 +30,8 @@ all: $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_32mbit.svf \ $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme \ $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf \ - $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme \ - $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.vme \ + $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.svf \ $(PROJECT)/$(PROJECT)_$(PROJECT).bit: @@ -81,17 +81,17 @@ $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.vme: $(PROJECT) $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_spansion_64mbit.mcs LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_multiboot_spansion_64mbit.xcf -of $@ -$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.mcs: $(PROJECT)/$(PROJECT)_$(PROJECT).bit $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit LANG=C ${DDTCMD} -dev $(FPGA_DEVICE) -oft -advanced -format int -flashsize 128 -header \ -if $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ -golden $(PROJECT)/$(PROJECT)_$(PROJECT).bit \ -multi 1 -altfile $(PROJECT)/$(PROJECT)_$(PROJECT)_altfile.bit -address 0x200000 -next prim -of $@ -$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs - LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_multiboot_micron_128mbit.xcf -nocompress -noheader -of $@ +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.vme: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.mcs + LANG=C ${DDTCMD} -oft -fullvme -if ulx3s_85f_multiboot_is25lp128f.xcf -nocompress -noheader -of $@ -$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_micron_128mbit.mcs - LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_multiboot_micron_128mbit.xcf -of $@ +$(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.svf: $(PROJECT)/$(PROJECT)_$(PROJECT)_multiboot_flash_is25lp128f.mcs + LANG=C ${DDTCMD} -oft -svfsingle -revd -maxdata 8 -if ulx3s_85f_multiboot_is25lp128f.xcf -of $@ program: $(PROJECT)/$(PROJECT)_$(PROJECT).bit echo pgr_project open ulx3s_85f_sram.xcf \; pgr_program run | ${DIAMONDC} diff --git a/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_is25lp128f.xcf similarity index 83% rename from boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf rename to boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_is25lp128f.xcf index 9ac9906..577759f 100644 --- a/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_micron_128mbit.xcf +++ b/boards/ulx3s-v2.0-85f-sp/ulx3s_85f_multiboot_is25lp128f.xcf @@ -17,9 +17,9 @@ 1 0 - project/project_project_multiboot_flash_micron_128mbit.mcs + project/project_project_multiboot_flash_is25lp128f.mcs 12/23/17 00:34:50 - SPI Flash Erase,Program + SPI Flash Erase,Program,Verify - project/project_project.mcs + project/project_project_multiboot_flash_is25lp032d.mcs 12/23/17 00:34:50 SPI Flash Erase,Program - project/project_project.mcs + project/project_project_multiboot_flash_is25lp128f.mcs 12/23/17 00:34:50 SPI Flash Erase,Program - project/project_project_multiboot_flash_spansion_64mbit.mcs + project/project_project_multiboot_flash_s25fl164k.mcs 12/23/17 00:34:50 SPI Flash Erase,Program - project/project_project_multiboot_flash_micron_32mbit.mcs + project/project_project_multiboot_flash_is25lp032d.mcs 12/23/17 00:34:50 SPI Flash Erase,Program - project/project_project_multiboot_flash_micron_128mbit.mcs + project/project_project_multiboot_flash_is25lp128f.mcs 12/23/17 00:34:50 SPI Flash Erase,Program