From 717b537a8868ff4c9a7f8ad569b13d6268616f76 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sat, 18 Aug 2018 22:59:02 +0200 Subject: [PATCH 1/4] Expose ENABLE_IRQ_QREGS to toplevel --- examples/picosoc/hardware.v | 1 + examples/picosoc/picosoc.v | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/examples/picosoc/hardware.v b/examples/picosoc/hardware.v index 46b2820..87dfa66 100644 --- a/examples/picosoc/hardware.v +++ b/examples/picosoc/hardware.v @@ -121,6 +121,7 @@ module hardware ( end picosoc #( + .ENABLE_IRQ_QREGS(1), .PROGADDR_RESET(32'h0005_0000), // beginning of user space in SPI flash .PROGADDR_IRQ(32'h0005_0010), .MEM_WORDS(2048) // use 2KBytes of block RAM by default diff --git a/examples/picosoc/picosoc.v b/examples/picosoc/picosoc.v index 7b3cfbd..1ce9420 100644 --- a/examples/picosoc/picosoc.v +++ b/examples/picosoc/picosoc.v @@ -59,6 +59,7 @@ module picosoc ( input flash_io2_di, input flash_io3_di ); + parameter [0:0] ENABLE_IRQ_QREGS = 0; parameter integer MEM_WORDS = 256; parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory parameter [31:0] PROGADDR_RESET = 32'h 0005_0000; // 1 MB into flash @@ -122,7 +123,7 @@ module picosoc ( .ENABLE_MUL(1), .ENABLE_DIV(1), .ENABLE_IRQ(1), - .ENABLE_IRQ_QREGS(1) + .ENABLE_IRQ_QREGS(ENABLE_IRQ_QREGS) ) cpu ( .clk (clk ), .resetn (resetn ), From 9a566f6164ce0babe0f735ead7b88acded9f2816 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sat, 18 Aug 2018 23:02:13 +0200 Subject: [PATCH 2/4] Add rule for creating firmware.hex --- examples/picosoc/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/examples/picosoc/Makefile b/examples/picosoc/Makefile index d174349..847a8a9 100644 --- a/examples/picosoc/Makefile +++ b/examples/picosoc/Makefile @@ -20,6 +20,8 @@ firmware.elf: sections.lds start.S firmware.c firmware.bin: firmware.elf riscv32-unknown-elf-objcopy -O binary firmware.elf /dev/stdout > firmware.bin +firmware.hex: firmware.elf + riscv32-unknown-elf-objcopy -O verilog firmware.elf firmware.hex clean: rm -f firmware.elf firmware.hex firmware.bin firmware.o firmware.map \ From 1708f4c3dc5d4dfe3ebd21bb93637a63034494ee Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sat, 18 Aug 2018 23:02:36 +0200 Subject: [PATCH 3/4] Add top-level testbench --- examples/picosoc/hardware_tb.v | 56 ++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 examples/picosoc/hardware_tb.v diff --git a/examples/picosoc/hardware_tb.v b/examples/picosoc/hardware_tb.v new file mode 100644 index 0000000..619c4ec --- /dev/null +++ b/examples/picosoc/hardware_tb.v @@ -0,0 +1,56 @@ +module hardware_tb; + + vlog_tb_utils vtu(); + + reg clk = 1'b1; + always #31 clk = !clk; //~16 MHz clock + + wire user_led; + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + wire flash_io2; + wire flash_io3; + + initial begin + repeat (2) begin + @(posedge user_led); + $display("LED is on"); + @(posedge user_led); + $display("LED is off"); + end + $finish; + end + + hardware dut + (.clk_16mhz (clk), + // onboard USB interface + .pin_pu (), + .pin_usbp (), + .pin_usbn (), + // hardware UART + .pin_1 (), + .pin_2 (1'b1), + // onboard LED + .user_led (user_led), + // onboard SPI flash interface + .flash_csb (flash_csb), + .flash_clk (flash_clk), + .flash_io0 (flash_io0), + .flash_io1 (flash_io1), + .flash_io2 (flash_io2), + .flash_io3 (flash_io3)); + + AT25SF081 + #(.tVSL (1000)) //Ensure flash is ready when reset is released + spiflash + (.SCLK (flash_clk), + .CS_N (flash_csb), + .SI (flash_io0), + .HOLD_N (flash_io3), + .WP_N (flash_io2), + .SO (flash_io1)); + +endmodule From 07ba11ad3b13863359e2a712690750590449cff2 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sat, 18 Aug 2018 23:03:19 +0200 Subject: [PATCH 4/4] Add FuseSoC .core file --- examples/picosoc/picosoc.core | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 examples/picosoc/picosoc.core diff --git a/examples/picosoc/picosoc.core b/examples/picosoc/picosoc.core new file mode 100644 index 0000000..4512fd3 --- /dev/null +++ b/examples/picosoc/picosoc.core @@ -0,0 +1,33 @@ +CAPI=2: +name : tinyfpga:bx:picosoc:0 + +filesets: + rtl: + files: + - hardware.v : {file_type : verilogSource} + depend : [picosoc] + constraints: + files: + - hardware.pcf : {file_type : PCF} + tb: + files: + - hardware_tb.v : {file_type : verilogSource} + depend : [at25sf081, vlog_tb_utils, "yosys:techlibs:ice40"] + +targets: + synth: + default_tool : icestorm + filesets: [rtl, constraints] + tools: + icestorm: + arachne_pnr_options : [-d, 8k, -P, cm81] + nextpnr_options : [--lp8k, --package, cm81] + pnr: next + toplevel : hardware + sim: + default_tool: icarus + filesets: [rtl, tb] + tools: + modelsim: + vlog_options: [-timescale=1ns/100ps] + toplevel: hardware_tb