diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h index a26269d33a..8d1355495a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h @@ -240,11 +240,6 @@ typedef struct uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ - uint32_t RESERVED3[246]; /*!< Reserved, */ - __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ - __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ } CRC_TypeDef; /** @@ -1758,11 +1753,11 @@ typedef struct #define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) /*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Pos (0UL) #define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos (0U) +#define RSSLIB_HDP_AREA1_Pos (0UL) #define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos (1U) +#define RSSLIB_HDP_AREA2_Pos (1UL) #define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) /** @@ -2888,164 +2883,164 @@ typedef struct /******************************* ADC VERSION ********************************/ #define ADC_VER_V5_X /******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Pos (0UL) #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ -#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Pos (1UL) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ -#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Pos (2UL) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ -#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Pos (3UL) #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Pos (4UL) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Pos (5UL) #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Pos (6UL) #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Pos (7UL) #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Pos (8UL) #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Pos (9UL) #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Pos (10UL) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ -#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Pos (11UL) #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ -#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Pos (12UL) #define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ #define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ /******************** Bit definition for ADC_IER register ********************/ -#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Pos (0UL) #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Pos (1UL) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ -#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Pos (2UL) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Pos (3UL) #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ -#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Pos (4UL) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ -#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Pos (5UL) #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Pos (6UL) #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ -#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Pos (7UL) #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ -#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Pos (8UL) #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ -#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Pos (9UL) #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ -#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Pos (10UL) #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ -#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Pos (11UL) #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ -#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Pos (12UL) #define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ #define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ /******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Pos (0UL) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ -#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Pos (1UL) #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ -#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Pos (2UL) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ -#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Pos (3UL) #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ -#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Pos (4UL) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ -#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Pos (5UL) #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ -#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Pos (16UL) #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ -#define ADC_CR_CALINDEX_Pos (24U) +#define ADC_CR_CALINDEX_Pos (24UL) #define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ #define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ -#define ADC_CR_CALINDEX0_Pos (24U) +#define ADC_CR_CALINDEX0_Pos (24UL) #define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ #define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ -#define ADC_CR_CALINDEX1_Pos (25U) +#define ADC_CR_CALINDEX1_Pos (25UL) #define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ #define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ -#define ADC_CR_CALINDEX2_Pos (26U) +#define ADC_CR_CALINDEX2_Pos (26UL) #define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ #define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ -#define ADC_CR_CALINDEX3_Pos (27U) +#define ADC_CR_CALINDEX3_Pos (27UL) #define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ #define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ -#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Pos (28UL) #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ -#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Pos (29UL) #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ -#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Pos (31UL) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ /******************** Bit definition for ADC_CFGR register ********************/ -#define ADC_CFGR1_DMNGT_Pos (0U) +#define ADC_CFGR1_DMNGT_Pos (0UL) #define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ #define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ #define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ -#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Pos (2UL) #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ -#define ADC4_CFGR1_DMAEN_Pos (0U) +#define ADC4_CFGR1_DMAEN_Pos (0UL) #define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC4_CFGR1_DMACFG_Pos (1U) +#define ADC4_CFGR1_DMACFG_Pos (1UL) #define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ -#define ADC4_CFGR1_SCANDIR_Pos (4U) +#define ADC4_CFGR1_SCANDIR_Pos (4UL) #define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ -#define ADC4_CFGR1_ALIGN_Pos (5U) +#define ADC4_CFGR1_ALIGN_Pos (5UL) #define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ -#define ADC_CFGR1_EXTSEL_Pos (5U) +#define ADC_CFGR1_EXTSEL_Pos (5UL) #define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ @@ -3054,68 +3049,68 @@ typedef struct #define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ -#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Pos (10UL) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ -#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Pos (12UL) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ -#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Pos (13UL) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ -#define ADC_CFGR1_AUTDLY_Pos (14U) +#define ADC_CFGR1_AUTDLY_Pos (14UL) #define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ -#define ADC4_CFGR1_WAIT_Pos (14U) +#define ADC4_CFGR1_WAIT_Pos (14UL) #define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ -#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Pos (16UL) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ -#define ADC_CFGR1_DISCNUM_Pos (17U) +#define ADC_CFGR1_DISCNUM_Pos (17UL) #define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ #define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ #define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ #define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ #define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ -#define ADC_CFGR1_JDISCEN_Pos (20U) +#define ADC_CFGR1_JDISCEN_Pos (20UL) #define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ #define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ -#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Pos (22UL) #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Pos (23UL) #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ -#define ADC_CFGR1_JAWD1EN_Pos (24U) +#define ADC_CFGR1_JAWD1EN_Pos (24UL) #define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ #define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ -#define ADC_CFGR1_JAUTO_Pos (25U) +#define ADC_CFGR1_JAUTO_Pos (25UL) #define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ #define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ /* Specific ADC4 */ -#define ADC4_CFGR1_EXTSEL_Pos (6U) +#define ADC4_CFGR1_EXTSEL_Pos (6UL) #define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ #define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ #define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ #define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC4_CFGR1_CHSELRMOD_Pos (21U) +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) #define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ #define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ -#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Pos (26UL) #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ @@ -3125,14 +3120,14 @@ typedef struct #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_CFGR2 register ********************/ -#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Pos (0UL) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ -#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Pos (1UL) #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ -#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Pos (5UL) #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ @@ -3140,14 +3135,14 @@ typedef struct #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ -#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Pos (9UL) #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ -#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Pos (10UL) #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ -#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Pos (16UL) #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ @@ -3161,23 +3156,23 @@ typedef struct #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ -#define ADC_CFGR2_BULB_Pos (13U) +#define ADC_CFGR2_BULB_Pos (13UL) #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ -#define ADC_CFGR2_SWTRIG_Pos (14U) +#define ADC_CFGR2_SWTRIG_Pos (14UL) #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ -#define ADC_CFGR2_SMPTRIG_Pos (15U) +#define ADC_CFGR2_SMPTRIG_Pos (15UL) #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ -#define ADC_CFGR2_LFTRIG_Pos (27U) +#define ADC_CFGR2_LFTRIG_Pos (27UL) #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ -#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Pos (28UL) #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ @@ -3186,243 +3181,243 @@ typedef struct #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ /* Specific ADC4 */ -#define ADC4_CFGR2_OVSR_Pos (2U) +#define ADC4_CFGR2_OVSR_Pos (2UL) #define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ #define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ #define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ #define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ #define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ -#define ADC4_CFGR2_LFTRIG_Pos (29U) +#define ADC4_CFGR2_LFTRIG_Pos (29UL) #define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ #define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ /******************** Bit definition for ADC_SMPR1 register ********************/ -#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Pos (0UL) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ -#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Pos (3UL) #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ -#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Pos (6UL) #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ -#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Pos (9UL) #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ -#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Pos (12UL) #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ -#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Pos (15UL) #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ -#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Pos (18UL) #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ -#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Pos (21UL) #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ -#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Pos (24UL) #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ -#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Pos (27UL) #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ -#define ADC4_SMPR_SMP1_Pos (0U) +#define ADC4_SMPR_SMP1_Pos (0UL) #define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ #define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ #define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ #define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ #define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ -#define ADC4_SMPR_SMP2_Pos (4U) +#define ADC4_SMPR_SMP2_Pos (4UL) #define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ #define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ #define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ #define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ #define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ -#define ADC4_SMPR_SMPSEL_Pos (8U) +#define ADC4_SMPR_SMPSEL_Pos (8UL) #define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ #define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ -#define ADC4_SMPR_SMPSEL0_Pos (8U) +#define ADC4_SMPR_SMPSEL0_Pos (8UL) #define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ #define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ -#define ADC4_SMPR_SMPSEL1_Pos (9U) +#define ADC4_SMPR_SMPSEL1_Pos (9UL) #define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ #define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ -#define ADC4_SMPR_SMPSEL2_Pos (10U) +#define ADC4_SMPR_SMPSEL2_Pos (10UL) #define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ #define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ -#define ADC4_SMPR_SMPSEL3_Pos (11U) +#define ADC4_SMPR_SMPSEL3_Pos (11UL) #define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ #define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ -#define ADC4_SMPR_SMPSEL4_Pos (12U) +#define ADC4_SMPR_SMPSEL4_Pos (12UL) #define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ #define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ -#define ADC4_SMPR_SMPSEL5_Pos (13U) +#define ADC4_SMPR_SMPSEL5_Pos (13UL) #define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ #define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ -#define ADC4_SMPR_SMPSEL6_Pos (14U) +#define ADC4_SMPR_SMPSEL6_Pos (14UL) #define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ #define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ -#define ADC4_SMPR_SMPSEL7_Pos (15U) +#define ADC4_SMPR_SMPSEL7_Pos (15UL) #define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ #define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ -#define ADC4_SMPR_SMPSEL8_Pos (16U) +#define ADC4_SMPR_SMPSEL8_Pos (16UL) #define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ #define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ -#define ADC4_SMPR_SMPSEL9_Pos (17U) +#define ADC4_SMPR_SMPSEL9_Pos (17UL) #define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ #define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ -#define ADC4_SMPR_SMPSEL10_Pos (18U) +#define ADC4_SMPR_SMPSEL10_Pos (18UL) #define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ #define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ -#define ADC4_SMPR_SMPSEL11_Pos (19U) +#define ADC4_SMPR_SMPSEL11_Pos (19UL) #define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ #define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ -#define ADC4_SMPR_SMPSEL12_Pos (20U) +#define ADC4_SMPR_SMPSEL12_Pos (20UL) #define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ #define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ -#define ADC4_SMPR_SMPSEL13_Pos (21U) +#define ADC4_SMPR_SMPSEL13_Pos (21UL) #define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ #define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ -#define ADC4_SMPR_SMPSEL14_Pos (22U) +#define ADC4_SMPR_SMPSEL14_Pos (22UL) #define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ #define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ -#define ADC4_SMPR_SMPSEL15_Pos (23U) +#define ADC4_SMPR_SMPSEL15_Pos (23UL) #define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ #define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ -#define ADC4_SMPR_SMPSEL16_Pos (24U) +#define ADC4_SMPR_SMPSEL16_Pos (24UL) #define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ #define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ -#define ADC4_SMPR_SMPSEL17_Pos (25U) +#define ADC4_SMPR_SMPSEL17_Pos (25UL) #define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ #define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ -#define ADC4_SMPR_SMPSEL18_Pos (26U) +#define ADC4_SMPR_SMPSEL18_Pos (26UL) #define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ #define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ -#define ADC4_SMPR_SMPSEL19_Pos (27U) +#define ADC4_SMPR_SMPSEL19_Pos (27UL) #define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ #define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ -#define ADC4_SMPR_SMPSEL20_Pos (26U) +#define ADC4_SMPR_SMPSEL20_Pos (26UL) #define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ #define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ -#define ADC4_SMPR_SMPSEL21_Pos (26U) +#define ADC4_SMPR_SMPSEL21_Pos (26UL) #define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ #define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ -#define ADC4_SMPR_SMPSEL22_Pos (30U) +#define ADC4_SMPR_SMPSEL22_Pos (30UL) #define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ #define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ -#define ADC4_SMPR_SMPSEL23_Pos (31U) +#define ADC4_SMPR_SMPSEL23_Pos (31UL) #define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ #define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ /******************** Bit definition for ADC_SMPR2 register ********************/ -#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Pos (0UL) #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ -#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Pos (3UL) #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ -#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Pos (6UL) #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ -#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Pos (9UL) #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ -#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Pos (12UL) #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ -#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Pos (15UL) #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ -#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Pos (18UL) #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ -#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Pos (21UL) #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ -#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Pos (24UL) #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ -#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Pos (27UL) #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ @@ -3430,7 +3425,7 @@ typedef struct #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ /******************** Bit definition for ADC_PCSEL register ********************/ -#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Pos (0UL) #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ @@ -3455,16 +3450,16 @@ typedef struct #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ -#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Pos (0UL) #define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ -#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Pos (0UL) #define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ -#define ADC_HTR_AWDFILT_Pos (29U) +#define ADC_HTR_AWDFILT_Pos (29UL) #define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ #define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ #define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ @@ -3472,7 +3467,7 @@ typedef struct #define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_SQR1 register ********************/ -#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Pos (0UL) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ @@ -3480,7 +3475,7 @@ typedef struct #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ -#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Pos (6UL) #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ @@ -3489,7 +3484,7 @@ typedef struct #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ -#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Pos (12UL) #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ @@ -3498,7 +3493,7 @@ typedef struct #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ -#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Pos (18UL) #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ @@ -3507,7 +3502,7 @@ typedef struct #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ -#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Pos (24UL) #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ @@ -3517,7 +3512,7 @@ typedef struct #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR2 register ********************/ -#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Pos (0UL) #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ @@ -3526,7 +3521,7 @@ typedef struct #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ -#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Pos (6UL) #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ @@ -3535,7 +3530,7 @@ typedef struct #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ -#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Pos (12UL) #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ @@ -3544,7 +3539,7 @@ typedef struct #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ -#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Pos (18UL) #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ @@ -3553,7 +3548,7 @@ typedef struct #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ -#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Pos (24UL) #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ @@ -3563,7 +3558,7 @@ typedef struct #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR3 register ********************/ -#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Pos (0UL) #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ @@ -3572,7 +3567,7 @@ typedef struct #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ -#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Pos (6UL) #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ @@ -3581,7 +3576,7 @@ typedef struct #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ -#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Pos (12UL) #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ @@ -3590,7 +3585,7 @@ typedef struct #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ -#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Pos (18UL) #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ @@ -3599,7 +3594,7 @@ typedef struct #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ -#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Pos (24UL) #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ @@ -3609,7 +3604,7 @@ typedef struct #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ /******************** Bit definition for ADC_SQR4 register ********************/ -#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Pos (0UL) #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ @@ -3618,7 +3613,7 @@ typedef struct #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ -#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Pos (6UL) #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ @@ -3627,21 +3622,21 @@ typedef struct #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ /******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Pos (0UL) #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ /******************** Bit definition for ADC_PW register ********************/ -#define ADC4_PWRR_AUTOFF_Pos (0U) +#define ADC4_PWRR_AUTOFF_Pos (0UL) #define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ #define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ -#define ADC4_PWRR_DPD_Pos (1U) +#define ADC4_PWRR_DPD_Pos (1UL) #define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ #define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ -#define ADC4_PWRR_VREFPROT_Pos (2U) +#define ADC4_PWRR_VREFPROT_Pos (2UL) #define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ #define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ -#define ADC4_PWRR_VREFSECSMP_Pos (3U) +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) #define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ #define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ @@ -3660,13 +3655,13 @@ typedef struct #define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP /******************** Bit definition for ADC_JSQR register ********************/ -#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Pos (0UL) #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ -#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Pos (2UL) #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ @@ -3675,13 +3670,13 @@ typedef struct #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Pos (7UL) #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Pos (9UL) #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ @@ -3690,7 +3685,7 @@ typedef struct #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ -#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Pos (15UL) #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ @@ -3699,7 +3694,7 @@ typedef struct #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ -#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Pos (21UL) #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ @@ -3708,7 +3703,7 @@ typedef struct #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ -#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Pos (27UL) #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ @@ -3718,7 +3713,7 @@ typedef struct #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OFR1 register ********************/ -#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Pos (0UL) #define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ @@ -3746,18 +3741,18 @@ typedef struct #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ -#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Pos (24UL) #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR1_USAT_Pos (25U) +#define ADC_OFR1_USAT_Pos (25UL) #define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR1_SSAT_Pos (26U) +#define ADC_OFR1_SSAT_Pos (26UL) #define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR1_OFFSET1_CH_Pos (27U) +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ @@ -3767,7 +3762,7 @@ typedef struct #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR2 register ********************/ -#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Pos (0UL) #define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ @@ -3795,18 +3790,18 @@ typedef struct #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ -#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Pos (24UL) #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR2_USAT_Pos (25U) +#define ADC_OFR2_USAT_Pos (25UL) #define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR2_SSAT_Pos (26U) +#define ADC_OFR2_SSAT_Pos (26UL) #define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR2_OFFSET2_CH_Pos (27U) +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ @@ -3816,7 +3811,7 @@ typedef struct #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR3 register ********************/ -#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Pos (0UL) #define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ @@ -3844,18 +3839,18 @@ typedef struct #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ -#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Pos (24UL) #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR3_USAT_Pos (25U) +#define ADC_OFR3_USAT_Pos (25UL) #define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR3_SSAT_Pos (26U) +#define ADC_OFR3_SSAT_Pos (26UL) #define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR3_OFFSET3_CH_Pos (27U) +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ @@ -3865,7 +3860,7 @@ typedef struct #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_OFR4 register ********************/ -#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Pos (0UL) #define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ @@ -3893,18 +3888,18 @@ typedef struct #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ -#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Pos (24UL) #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR4_USAT_Pos (25U) +#define ADC_OFR4_USAT_Pos (25UL) #define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ #define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ -#define ADC_OFR4_SSAT_Pos (26U) +#define ADC_OFR4_SSAT_Pos (26UL) #define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ #define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ -#define ADC_OFR4_OFFSET4_CH_Pos (27U) +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ @@ -3914,15 +3909,15 @@ typedef struct #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ /******************** Bit definition for ADC_GCOMP register ********************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ -#define ADC_GCOMP_GCOMP_Pos (31U) +#define ADC_GCOMP_GCOMP_Pos (31UL) #define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ #define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ /******************** Bit definition for ADC_JDR1 register ********************/ -#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Pos (0UL) #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ @@ -3959,7 +3954,7 @@ typedef struct #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Pos (0UL) #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ @@ -3996,7 +3991,7 @@ typedef struct #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Pos (0UL) #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ @@ -4033,7 +4028,7 @@ typedef struct #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Pos (0UL) #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ @@ -4070,7 +4065,7 @@ typedef struct #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD2CR register ********************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Pos (0UL) #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ @@ -4099,7 +4094,7 @@ typedef struct #define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_AWD1TR register *******************/ -#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Pos (0UL) #define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ #define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ @@ -4115,7 +4110,7 @@ typedef struct #define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ #define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ -#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Pos (16UL) #define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ @@ -4132,7 +4127,7 @@ typedef struct #define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWDTR2 register *******************/ -#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Pos (0UL) #define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ #define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ #define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ @@ -4148,7 +4143,7 @@ typedef struct #define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ #define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ -#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Pos (16UL) #define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ #define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ @@ -4165,88 +4160,88 @@ typedef struct #define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_CHSELR register ****************/ -#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Pos (0UL) #define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Pos (0UL) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Pos (1UL) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Pos (2UL) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Pos (3UL) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Pos (4UL) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Pos (5UL) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Pos (6UL) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Pos (7UL) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Pos (8UL) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Pos (9UL) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Pos (10UL) #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Pos (11UL) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Pos (12UL) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Pos (13UL) #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Pos (14UL) #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Pos (15UL) #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Pos (16UL) #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Pos (17UL) #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Pos (18UL) #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL19_Pos (19U) +#define ADC_CHSELR_CHSEL19_Pos (19UL) #define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL20_Pos (20U) +#define ADC_CHSELR_CHSEL20_Pos (20UL) #define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL21_Pos (21U) +#define ADC_CHSELR_CHSEL21_Pos (21UL) #define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL22_Pos (22U) +#define ADC_CHSELR_CHSEL22_Pos (22UL) #define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL23_Pos (23U) +#define ADC_CHSELR_CHSEL23_Pos (23UL) #define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Pos (0UL) #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Pos (0UL) #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ @@ -4254,7 +4249,7 @@ typedef struct #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ -#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Pos (4UL) #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ @@ -4262,7 +4257,7 @@ typedef struct #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ -#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Pos (8UL) #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ @@ -4270,7 +4265,7 @@ typedef struct #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ -#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Pos (12UL) #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ @@ -4278,7 +4273,7 @@ typedef struct #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ -#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Pos (16UL) #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ @@ -4286,7 +4281,7 @@ typedef struct #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ -#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Pos (20UL) #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ @@ -4294,7 +4289,7 @@ typedef struct #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ -#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Pos (24UL) #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ @@ -4302,7 +4297,7 @@ typedef struct #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ -#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Pos (28UL) #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ @@ -4311,7 +4306,7 @@ typedef struct #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_AWD3TR register *******************/ -#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Pos (0UL) #define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ #define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ #define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ @@ -4327,7 +4322,7 @@ typedef struct #define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ #define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ -#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Pos (16UL) #define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ #define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ #define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ @@ -4344,7 +4339,7 @@ typedef struct #define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ /******************** Bit definition for ADC_AWD3CR register ********************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Pos (0UL) #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ @@ -4373,7 +4368,7 @@ typedef struct #define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ /******************** Bit definition for ADC_DIFSEL register ********************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Pos (0UL) #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ @@ -4398,7 +4393,7 @@ typedef struct #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_I_APB_ADDR_Pos (0U) +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) #define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ #define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ #define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ @@ -4410,7 +4405,7 @@ typedef struct #define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ #define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ -#define ADC_CALFACT_I_APB_DATA_Pos (08U) +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) #define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ #define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ #define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ @@ -4422,17 +4417,17 @@ typedef struct #define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ #define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ -#define ADC_CALFACT_VALIDITY_Pos (16U) +#define ADC_CALFACT_VALIDITY_Pos (16UL) #define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ #define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_LATCH_COEF_Pos (24U) +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) #define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) #define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ #define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ -#define ADC4_CALFACT_CALFACT_Pos (0U) +#define ADC4_CALFACT_CALFACT_Pos (0UL) #define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ #define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ #define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ @@ -4444,7 +4439,7 @@ typedef struct #define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ /******************** Bit definition for ADC_CALFACT2 register ********************/ -#define ADC_CALFACT2_CALFACT_Pos (0U) +#define ADC_CALFACT2_CALFACT_Pos (0UL) #define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ #define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ @@ -4481,13 +4476,13 @@ typedef struct #define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ /******************** Bit definition for ADC_OR register ********************/ -#define ADC_OR_CHN0SEL_Pos (0U) +#define ADC_OR_CHN0SEL_Pos (0UL) #define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ #define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ /************************* ADC Common registers *****************************/ -#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Pos (18UL) #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ @@ -4495,19 +4490,19 @@ typedef struct #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ -#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Pos (22UL) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) +#define ADC_CCR_VSENSEEN_Pos (23UL) #define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Pos (24UL) #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ -#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Pos (25UL) #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ -#define ADC_CCR_VDDCOREN_Pos (26U) +#define ADC_CCR_VDDCOREN_Pos (26UL) #define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ #define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ @@ -4518,58 +4513,58 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CORDIC_CSR register *****************/ -#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Pos (0UL) #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ -#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Pos (4UL) #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ -#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Pos (8UL) #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ -#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Pos (16UL) #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ -#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Pos (17UL) #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ -#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Pos (18UL) #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ -#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Pos (19UL) #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ -#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Pos (20UL) #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ -#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Pos (21UL) #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ -#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Pos (22UL) #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ -#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Pos (31UL) #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ /******************* Bit definition for CORDIC_WDATA register ***************/ -#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Pos (0UL) #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ /******************* Bit definition for CORDIC_RDATA register ***************/ -#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Pos (0UL) #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ @@ -4579,40 +4574,40 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Pos (0UL) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Pos (0UL) #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ /******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Pos (0UL) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Pos (3UL) #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Pos (5UL) #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Pos (7UL) #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ /******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Pos (0UL) #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ /******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Pos (0UL) #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ @@ -4621,93 +4616,93 @@ typedef struct /* CRS Clock Recovery System */ /******************************************************************************/ /******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Pos (0UL) #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Pos (1UL) #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Pos (2UL) #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Pos (3UL) #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Pos (5UL) #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Pos (6UL) #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Pos (7UL) #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Pos (8UL) #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ /******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Pos (0UL) #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Pos (16UL) #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Pos (24UL) #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Pos (28UL) #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Pos (31UL) #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ /******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Pos (0UL) #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Pos (1UL) #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Pos (2UL) #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Pos (3UL) #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Pos (8UL) #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Pos (9UL) #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Pos (10UL) #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Pos (15UL) #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Pos (16UL) #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ /******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Pos (0UL) #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Pos (1UL) #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Pos (2UL) #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Pos (3UL) #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ @@ -4717,83 +4712,83 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Pos (2UL) #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk -#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Pos (3UL) #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk -#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Pos (5UL) #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ #define RNG_CR_CED RNG_CR_CED_Msk -#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Pos (7UL) #define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) #define RNG_CR_ARDIS RNG_CR_ARDIS_Msk -#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Pos (8UL) #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk -#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Pos (12UL) #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) #define RNG_CR_NISTC RNG_CR_NISTC_Msk -#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Pos (13UL) #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk -#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Pos (16UL) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk #define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ #define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ #define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ #define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ -#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Pos (20UL) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk -#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Pos (30UL) #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk -#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Pos (31UL) #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Pos (0UL) #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk -#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Pos (1UL) #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk -#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Pos (2UL) #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk -#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Pos (5UL) #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk -#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Pos (6UL) #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************** Bits definition for RNG_NSCR register *******************/ -#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Pos (0UL) #define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ #define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk -#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Pos (3UL) #define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ #define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Pos (6UL) #define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ #define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk -#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Pos (9UL) #define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ #define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk -#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Pos (12UL) #define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ #define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk -#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Pos (15UL) #define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ #define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk /******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Pos (0UL) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk /******************** RNG Nist Compliance Values *******************/ @@ -4808,277 +4803,277 @@ typedef struct #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Pos (0UL) #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -16031,257 +16028,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -16292,57 +16289,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -16350,7 +16347,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -16361,10 +16358,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -16375,489 +16372,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -16867,44 +16864,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -16583,257 +16580,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -16844,57 +16841,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -16902,7 +16899,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -16913,10 +16910,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -16927,489 +16924,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -17419,44 +17416,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -17546,257 +17543,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -17807,57 +17804,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -17865,7 +17862,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -17876,10 +17873,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -17890,489 +17887,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -18382,44 +18379,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -18156,257 +18153,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -18417,57 +18414,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -18475,7 +18472,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -18486,10 +18483,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -18500,489 +18497,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -18992,44 +18989,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -18656,257 +18653,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -18917,57 +18914,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -18975,7 +18972,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -18986,10 +18983,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -19000,489 +18997,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -19492,44 +19489,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -22430,257 +22427,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -22691,57 +22688,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -22749,7 +22746,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -22760,10 +22757,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -22774,489 +22771,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -23266,44 +23263,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -19266,257 +19263,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -19527,57 +19524,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -19585,7 +19582,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -19596,10 +19593,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -19610,489 +19607,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -20102,44 +20099,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -23040,257 +23037,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -23301,57 +23298,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -23359,7 +23356,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -23370,10 +23367,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -23384,489 +23381,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -23876,44 +23873,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -20249,257 +20246,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -20510,57 +20507,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -20568,7 +20565,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -20579,10 +20576,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -20593,489 +20590,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -21085,44 +21082,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -23390,257 +23387,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -23651,57 +23648,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -23709,7 +23706,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -23720,10 +23717,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -23734,489 +23731,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -24226,44 +24223,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -20859,257 +20856,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -21120,57 +21117,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -21178,7 +21175,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -21189,10 +21186,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -21203,489 +21200,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -21695,44 +21692,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Pos (14UL) #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Pos (16UL) #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Pos (30UL) #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ /******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Pos (0UL) #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Pos (4UL) #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Pos (7UL) #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Pos (8UL) #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Pos (12UL) #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Pos (15UL) #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Pos (16UL) #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Pos (20UL) #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Pos (22UL) #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Pos (23UL) #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Pos (24UL) #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Pos (28UL) #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Pos (30UL) #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Pos (31UL) #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Pos (0UL) #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Pos (24UL) #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Pos (31UL) #define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk /******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Pos (0UL) #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Pos (4UL) #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Pos (7UL) #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Pos (8UL) #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Pos (12UL) #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Pos (15UL) #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Pos (16UL) #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Pos (20UL) #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Pos (22UL) #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Pos (23UL) #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Pos (24UL) #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Pos (28UL) #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Pos (30UL) #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Pos (31UL) #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Pos (0UL) #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) #define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ #define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk /******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Pos (0UL) #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Pos (1UL) #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Pos (2UL) #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ #define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Pos (3UL) #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ #define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Pos (4UL) #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Pos (5UL) #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ #define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Pos (6UL) #define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ #define RTC_SR_SSRUF RTC_SR_SSRUF_Msk /******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Pos (0UL) #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Pos (1UL) #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Pos (2UL) #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Pos (3UL) #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Pos (4UL) #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Pos (5UL) #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Pos (6UL) #define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk /******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Pos (0UL) #define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ #define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Pos (1UL) #define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ #define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Pos (2UL) #define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ #define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Pos (3UL) #define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ #define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Pos (4UL) #define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ #define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Pos (5UL) #define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ #define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Pos (6UL) #define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ #define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk /******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Pos (0UL) #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Pos (1UL) #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Pos (2UL) #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Pos (3UL) #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Pos (4UL) #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Pos (5UL) #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Pos (6UL) #define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ #define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk /******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Pos (0UL) #define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk /******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Pos (0UL) #define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ #define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk @@ -24000,257 +23997,257 @@ typedef struct /* */ /******************************************************************************/ /******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Pos (0UL) #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Pos (1UL) #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Pos (2UL) #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Pos (3UL) #define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ #define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Pos (4UL) #define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ #define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Pos (5UL) #define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ #define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Pos (6UL) #define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ #define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Pos (7UL) #define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ #define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Pos (16UL) #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Pos (17UL) #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Pos (18UL) #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Pos (20UL) #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Pos (21UL) #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Pos (22UL) #define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ #define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Pos (23UL) #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Pos (24UL) #define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ #define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Pos (26UL) #define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Pos (27UL) #define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Pos (28UL) #define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ #define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk /******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) #define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ #define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) #define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ #define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) #define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ #define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) #define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ #define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) #define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ #define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Pos (16UL) #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Pos (17UL) #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Pos (18UL) #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Pos (22UL) #define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Pos (23UL) #define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ #define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Pos (24UL) #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Pos (25UL) #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Pos (26UL) #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Pos (27UL) #define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Pos (28UL) #define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Pos (29UL) #define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Pos (30UL) #define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Pos (31UL) #define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ #define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk /******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) #define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ #define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) #define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ #define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) #define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ #define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) #define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ #define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) #define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ #define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) #define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ #define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) #define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) #define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) #define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ #define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk /******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk /******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) #define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ #define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) #define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) #define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ #define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) #define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ #define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) #define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ #define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) #define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ #define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Pos (24UL) #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk #define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ #define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ #define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Pos (31UL) #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk /******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Pos (0UL) #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk /******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Pos (0UL) #define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk #define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ @@ -24261,57 +24258,57 @@ typedef struct #define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ #define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ #define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Pos (14UL) #define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Pos (15UL) #define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk /******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) #define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ #define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk #define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ #define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ #define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) #define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ #define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk #define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ #define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ #define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) #define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ #define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk #define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ #define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ #define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) #define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ #define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk #define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ #define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ #define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) #define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ #define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk #define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ #define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ #define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) #define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ #define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk #define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ #define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ #define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) #define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ #define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk #define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ #define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ #define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) #define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ #define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk #define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ @@ -24319,7 +24316,7 @@ typedef struct #define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ /******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) #define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ #define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk #define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ @@ -24330,10 +24327,10 @@ typedef struct #define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ #define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ #define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) #define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ #define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) #define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ #define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk #define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ @@ -24344,489 +24341,489 @@ typedef struct #define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ #define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ #define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) #define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ #define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) #define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ #define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk /******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) #define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) #define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ #define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) #define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ #define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) #define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ #define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk /******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Pos (0UL) #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Pos (1UL) #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Pos (2UL) #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Pos (3UL) #define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ #define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Pos (4UL) #define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ #define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Pos (5UL) #define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ #define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Pos (6UL) #define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ #define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Pos (7UL) #define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ #define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Pos (16UL) #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Pos (17UL) #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Pos (18UL) #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Pos (20UL) #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Pos (21UL) #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Pos (22UL) #define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ #define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Pos (23UL) #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Pos (24UL) #define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ #define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Pos (26UL) #define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ #define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Pos (27UL) #define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ #define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Pos (28UL) #define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ #define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk /******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Pos (0UL) #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Pos (1UL) #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Pos (2UL) #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Pos (3UL) #define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Pos (4UL) #define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Pos (5UL) #define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Pos (6UL) #define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Pos (7UL) #define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Pos (16UL) #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Pos (17UL) #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Pos (18UL) #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Pos (20UL) #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Pos (21UL) #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Pos (22UL) #define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Pos (23UL) #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Pos (24UL) #define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Pos (26UL) #define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Pos (27UL) #define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Pos (28UL) #define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk /******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Pos (0UL) #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Pos (1UL) #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Pos (2UL) #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Pos (3UL) #define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Pos (4UL) #define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Pos (5UL) #define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Pos (6UL) #define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Pos (7UL) #define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Pos (16UL) #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Pos (17UL) #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Pos (18UL) #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Pos (20UL) #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Pos (21UL) #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Pos (22UL) #define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Pos (23UL) #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Pos (24UL) #define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Pos (26UL) #define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Pos (27UL) #define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Pos (28UL) #define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Pos (0UL) #define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ #define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Pos (1UL) #define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ #define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Pos (2UL) #define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ #define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Pos (3UL) #define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ #define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Pos (4UL) #define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ #define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Pos (5UL) #define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ #define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Pos (6UL) #define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ #define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Pos (7UL) #define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ #define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) #define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) #define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ #define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) #define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ #define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) #define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ #define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) #define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ #define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) #define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ #define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) #define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ #define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) #define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ #define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) #define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ #define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) #define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ #define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) #define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ #define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk /******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Pos (0UL) #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Pos (1UL) #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Pos (2UL) #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Pos (3UL) #define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ #define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Pos (4UL) #define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ #define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Pos (5UL) #define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ #define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Pos (6UL) #define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ #define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Pos (7UL) #define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ #define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Pos (16UL) #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Pos (17UL) #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Pos (18UL) #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Pos (20UL) #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Pos (21UL) #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Pos (22UL) #define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ #define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Pos (23UL) #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Pos (24UL) #define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ #define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Pos (26UL) #define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ #define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Pos (27UL) #define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ #define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Pos (28UL) #define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ #define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Pos (16UL) #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ #define TAMP_COUNTR TAMP_COUNTR_Msk /******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) +#define TAMP_ERCFGR0_Pos (0UL) #define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ #define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Pos (0UL) #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP0R TAMP_BKP0R_Msk /******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Pos (0UL) #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP1R TAMP_BKP1R_Msk /******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Pos (0UL) #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP2R TAMP_BKP2R_Msk /******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Pos (0UL) #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP3R TAMP_BKP3R_Msk /******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Pos (0UL) #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP4R TAMP_BKP4R_Msk /******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Pos (0UL) #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP5R TAMP_BKP5R_Msk /******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Pos (0UL) #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP6R TAMP_BKP6R_Msk /******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Pos (0UL) #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP7R TAMP_BKP7R_Msk /******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Pos (0UL) #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP8R TAMP_BKP8R_Msk /******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Pos (0UL) #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP9R TAMP_BKP9R_Msk /******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Pos (0UL) #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP10R TAMP_BKP10R_Msk /******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Pos (0UL) #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP11R TAMP_BKP11R_Msk /******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Pos (0UL) #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP12R TAMP_BKP12R_Msk /******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Pos (0UL) #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP13R TAMP_BKP13R_Msk /******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Pos (0UL) #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP14R TAMP_BKP14R_Msk /******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Pos (0UL) #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP15R TAMP_BKP15R_Msk /******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Pos (0UL) #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP16R TAMP_BKP16R_Msk /******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Pos (0UL) #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP17R TAMP_BKP17R_Msk /******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Pos (0UL) #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP18R TAMP_BKP18R_Msk /******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Pos (0UL) #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP19R TAMP_BKP19R_Msk /******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Pos (0UL) #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP20R TAMP_BKP20R_Msk /******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Pos (0UL) #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP21R TAMP_BKP21R_Msk /******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Pos (0UL) #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP22R TAMP_BKP22R_Msk /******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Pos (0UL) #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP23R TAMP_BKP23R_Msk /******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Pos (0UL) #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP24R TAMP_BKP24R_Msk /******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Pos (0UL) #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP25R TAMP_BKP25R_Msk /******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Pos (0UL) #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP26R TAMP_BKP26R_Msk /******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Pos (0UL) #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP27R TAMP_BKP27R_Msk /******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Pos (0UL) #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP28R TAMP_BKP28R_Msk /******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Pos (0UL) #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP29R TAMP_BKP29R_Msk /******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Pos (0UL) #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP30R TAMP_BKP30R_Msk /******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Pos (0UL) #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ #define TAMP_BKP31R TAMP_BKP31R_Msk @@ -24836,44 +24833,44 @@ typedef struct /* */ /******************************************************************************/ /******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) +#define TSC_CR_TSCE_Pos (0UL) #define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!Release Notes for  STM32U5xx C

Update History

- +

Main Changes

  • General updates to fix known defects and implementation enhancements.
    • +
  • Remove the internal CRC registers from defined CMSIS CRC structure (CRC_TypeDef).
    • +
  • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.
    • +
  • Align the JPEG base address in Secure mode with the one defined for Non-Secure mode.
    • +
  • Add specific gcc linker files for STM32U5A5xx devices.
    • +
  • Increase the total SRAM size in STM32U5G9 linker file template to include SRAM6 size.
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
  • Fix TAMP_CR3_ITAMP7NOER bit definition to be aligned with reference manual.
  • Add missing USB_OTG_GINTSTS_RSTDET bit definition.
  • Align USB OTG bit definition with reference manual.
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -48,7 +66,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Add Bits definition for RNG_NSCR register for RNG noise source control
    • @@ -61,7 +79,7 @@

    Main Changes

  • Fix wrong declaration of g_pfnVectors size in GCC startup_stm32u5XXxx.s files
  • Update linker files to properly mark sections readonly for GCC12
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -70,12 +88,12 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -84,7 +102,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices: @@ -94,7 +112,7 @@

    Main Changes

  • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -103,7 +121,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices: @@ -156,7 +174,7 @@

    Main Changes

  • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -165,7 +183,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
      @@ -195,7 +213,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
      • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
        • @@ -207,7 +225,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld new file mode 100644 index 0000000000..f0bb40cd54 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH.ld @@ -0,0 +1,166 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 4096Kbytes FLASH +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4096K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld new file mode 100644 index 0000000000..e8e2b5c79d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_ns.ld @@ -0,0 +1,166 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 4096Kbytes FLASH +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x200D0000, LENGTH = 1664K /* Memory is divided. Actual start is 0x20000000 and actual length is 2496K */ + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x08200000, LENGTH = 2048K /* Memory is divided. Actual start is 0x08000000 and actual length is 4096K */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld new file mode 100644 index 0000000000..469ad194bb --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_FLASH_s.ld @@ -0,0 +1,174 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 4096Kbytes FLASH +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 832K /* Memory is divided. Actual start is 0x30000000 and actual length is 2512K */ + SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 2040K /* Memory is divided. Actual start is 0x0C000000 and actual length is 4096K */ + FLASH_NSC (rx) : ORIGIN = 0x0C1FE000, LENGTH = 8K /* Non-Secure Call-able region */ +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld new file mode 100644 index 0000000000..f87e1d7ff9 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM.ld @@ -0,0 +1,164 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld (debug in RAM dedicated) +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld new file mode 100644 index 0000000000..641948f7bf --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_ns.ld @@ -0,0 +1,164 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld (debug in RAM dedicated) +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x200D0000, LENGTH = 1664K /* Memory is divided. Actual start is 0x20000000 and actual length is 2496K */ + SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld new file mode 100644 index 0000000000..4f4f7a007c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5A5xx_RAM_s.ld @@ -0,0 +1,172 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld (debug in RAM dedicated) +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32U5A5xJ Device from STM32U5 series +** 2512Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 824K /* Memory is divided. Actual start is 0x30000000 and actual length is 2512K */ + RAM_NSC (xrw) : ORIGIN = 0x300CE000, LENGTH = 8K /* Non-Secure Call-able region */ + SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + KEEP(*(.isr_vector)) /* Startup code */ + } >RAM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + _etext = .; /* define a global symbols at end of code */ + } >RAM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } >RAM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + _edata = .; /* define a global symbol at data end */ + } >RAM + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >RAM_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld index da9f1c5940..e567b8cde2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH.ld @@ -45,7 +45,7 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 3008K SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4096K } diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld index 594c1e30ad..a61a1d5e19 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_ns.ld @@ -45,9 +45,9 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x200C0000, LENGTH = 1728K /* Memory is divided. Actual start is 0x20000000 and actual length is 2496K */ + RAM (xrw) : ORIGIN = 0x200D0000, LENGTH = 2176K /* Memory is divided. Actual start is 0x200D0000 and actual length is 2176K */ SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K /* Non-Secure SRAM4 */ - FLASH (rx) : ORIGIN = 0x08200000, LENGTH = 2048K /* Memory is divided. Actual start is 0x08000000 and actual length is 4096K */ + FLASH (rx) : ORIGIN = 0x08200000, LENGTH = 2048K /* Memory is divided. Actual start is 0x08200000 and actual length is 2048K */ } /* Sections */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld index 8e8708875c..d93c2da0a4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_FLASH_s.ld @@ -45,8 +45,8 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 768K /* Memory is divided. Actual start is 0x30000000 and actual length is 2512K */ - FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 2040K /* Memory is divided. Actual start is 0x0C000000 and actual length is 4096K */ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 832K /* Memory is divided. Actual start is 0x30000000 and actual length is 832K */ + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 2040K /* Memory is divided. Actual start is 0x0C000000 and actual length is 2040K */ FLASH_NSC (rx) : ORIGIN = 0x0C1FE000, LENGTH = 8K /* Non-Secure Call-able region */ SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K /* Secure SRAM4 */ } diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld index fb56881fd5..9c4d76d7e8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM.ld @@ -44,7 +44,7 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2496K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 3008K SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K } diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld index 4a93304254..0b950afe0c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_ns.ld @@ -44,7 +44,7 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x200C0000, LENGTH = 1728K /* Memory is divided. Actual start is 0x20000000 and actual length is 2496K */ + RAM (xrw) : ORIGIN = 0x200D0000, LENGTH = 2176K /* Memory is divided. Actual start is 0x200D0000 and actual length is 2176K */ SRAM4 (xrw) : ORIGIN = 0x28000000, LENGTH = 16K /* Non-Secure SRAM4 */ } diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld index 6320c1e7b0..c4e5f228a3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/gcc/linker/STM32U5G9xx_RAM_s.ld @@ -44,7 +44,7 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 760K /* Memory is divided. Actual start is 0x30000000 and actual length is 2512K */ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 832K /* Memory is divided. Actual start is 0x30000000 and actual length is 832K */ RAM_NSC (xrw) : ORIGIN = 0x300BE000, LENGTH = 8K /* Non-Secure Call-able region */ SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K /* Secure SRAM4 */ } diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.c b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.c index 7bb9ffd0f6..3d274115cc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.c @@ -135,8 +135,10 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ /******************************************************************************/ /** diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c index cd8d405ec4..6c77b0d173 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx_s.c @@ -149,8 +149,10 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ /******************************************************************************/ /** * @} diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index f181432c69..bec9198264 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.7.0 * STM32U0: 1.2.0 * STM32U3: 1.1.0 - * STM32U5: 1.4.1 + * STM32U5: 1.4.2 * STM32WB: 1.12.2 * STM32WB0: 1.3.0 * STM32WBA: 1.5.0 diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index cf3942e283..cc77833a0f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -538,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -560,6 +564,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -1299,22 +1306,22 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL #endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1481,7 +1488,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -3695,7 +3702,8 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3946,8 +3954,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ - defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h index af230a52b5..ac6a09c4ed 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h @@ -596,40 +596,40 @@ typedef struct * @brief DMAEx Private Constants * @{ */ -#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ +#define DMA_LINKEDLIST (0x0080UL) /* DMA channel linked-list mode */ -#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ -#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ -#define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */ -#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001UL) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002UL) /* DMA channel 2D addressing mode */ +#define DMA_CHANNEL_TYPE_LPDMA (0x0010UL) /* LPDMA channel node */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020UL) /* GPDMA channel node */ -#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ -#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ -#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ +#define NODE_TYPE_MASK (0x00FFUL) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700UL) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008UL) /* DMA channel node CLLR index position */ -#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ +#define NODE_MAXIMUM_SIZE (0x0008UL) /* Amount of registers of the node */ -#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ -#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ +#define NODE_STATIC_FORMAT (0x0000UL) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001UL) /* DMA channel node dynamic format */ -#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ -#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ +#define UPDATE_CLLR_POSITION (0x0000UL) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001UL) /* DMA channel update CLLR value */ -#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ -#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ +#define LASTNODE_ISNOT_CIRCULAR (0x0000UL) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001UL) /* Last node is first circular node */ -#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ -#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ +#define QUEUE_TYPE_STATIC (0x0000UL) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001UL) /* DMA channel dynamic queue */ -#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ -#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ -#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ -#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ -#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ -#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ -#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ -#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ -#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ +#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */ +#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */ +#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */ #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h index 13afdd2da3..5f0f16511f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h @@ -201,19 +201,19 @@ typedef struct /** * @brief EXTI Line property definition */ -#define EXTI_PROPERTY_SHIFT 24U -#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT) -#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_SHIFT 24UL +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ -#define EXTI_REG_SHIFT 16U -#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT) -#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT) +#define EXTI_REG_SHIFT 16UL +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) #define EXTI_PIN_MASK 0x0000001FU diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h index aea5c97da7..dc09856235 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h @@ -134,6 +134,9 @@ typedef struct /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ */ +#ifndef HAL_HCD_CHANNEL_NAK_COUNT +#define HAL_HCD_CHANNEL_NAK_COUNT 2U +#endif /* HAL_HCD_CHANNEL_NAK_COUNT */ /** @defgroup HCD_Speed HCD Speed * @{ @@ -232,6 +235,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num); #if defined (USB_DRD_FS) HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num); #endif /* defined (USB_DRD_FS) */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h index 4bd1ab8d9b..19067fcdb9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h @@ -102,54 +102,54 @@ typedef struct #define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ #define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ -#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) +#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000UL)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ -#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ -#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ -#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ -#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) +#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000UL)) /*!< HW Trigger signal is LPDMA_CH0_TRG */ -#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH1_TRG */ -#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH2_TRG */ -#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH3_TRG */ -#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM3_CH1_TRG */ -#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ -#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ -#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h index 1f124b5a7d..2f200ccec3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h @@ -71,7 +71,7 @@ typedef struct /** @defgroup ICACHE_WaysSelection Ways selection * @{ */ -#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */ #define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ /** * @} @@ -90,10 +90,10 @@ typedef struct /** @defgroup ICACHE_Region Remapped Region number * @{ */ -#define ICACHE_REGION_0 0U /*!< Region 0 */ -#define ICACHE_REGION_1 1U /*!< Region 1 */ -#define ICACHE_REGION_2 2U /*!< Region 2 */ -#define ICACHE_REGION_3 3U /*!< Region 3 */ +#define ICACHE_REGION_0 0UL /*!< Region 0 */ +#define ICACHE_REGION_1 1UL /*!< Region 1 */ +#define ICACHE_REGION_2 2UL /*!< Region 2 */ +#define ICACHE_REGION_3 3UL /*!< Region 3 */ /** * @} */ @@ -101,13 +101,13 @@ typedef struct /** @defgroup ICACHE_Region_Size Remapped Region size * @{ */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ /** * @} */ @@ -115,7 +115,7 @@ typedef struct /** @defgroup ICACHE_Traffic_Route Remapped Traffic route * @{ */ -#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */ #define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ /** * @} @@ -124,7 +124,7 @@ typedef struct /** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type * @{ */ -#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */ #define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h index 040e1ecd7b..557fb37489 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h @@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h index b63abb7675..8ad417eb6d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h @@ -656,7 +656,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); */ #if defined (OCTOSPIM) -/** @defgroup OSPI_IO_Manger_IOPort OSPI IO Manager IO Port +/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port * @{ */ #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ @@ -788,12 +788,12 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup OSPI_Exported_Functions OSPI Exported Functions +/** @addtogroup OSPI_Exported_Functions * @{ */ /* Initialization/de-initialization functions ********************************/ -/** @addtogroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup OSPI_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); @@ -806,7 +806,7 @@ void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi); */ /* IO operation functions *****************************************************/ -/** @addtogroup OSPI_Exported_Functions_Group2 Input and Output operation functions +/** @addtogroup OSPI_Exported_Functions_Group2 * @{ */ /* OSPI IRQ handler function */ @@ -862,7 +862,7 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL */ /* Peripheral Control and State functions ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions +/** @addtogroup OSPI_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); @@ -879,7 +879,7 @@ uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); #if defined (OCTOSPIM) /* OSPI IO Manager configuration function ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group4 IO Manager configuration function +/** @addtogroup OSPI_Exported_Functions_Group4 * @{ */ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); @@ -923,7 +923,7 @@ HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, H #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) -#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h index bfe659f16a..bf6097399c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_otfdec.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2020 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -350,7 +350,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t Attributes); @@ -365,9 +365,9 @@ HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi /** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions * @{ */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec); +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec); HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uint32_t *Attributes); -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h index 5d4e328317..a34515a936 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pssi.h @@ -200,14 +200,14 @@ typedef enum /** @defgroup ControlSignal_Configuration ControlSignal Configuration * @{ */ -#define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ -#define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ -#define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ -#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ -#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ -#define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ -#define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ -#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ +#define HAL_PSSI_DE_RDY_DISABLE (0x0UL << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ +#define HAL_PSSI_RDY_ENABLE (0x1UL << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ +#define HAL_PSSI_DE_ENABLE (0x2UL << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ +#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3UL << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ +#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4UL << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ +#define HAL_PSSI_RDY_MAP_ENABLE (0x5UL << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ +#define HAL_PSSI_DE_MAP_ENABLE (0x6UL << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ +#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ /** * @} @@ -261,7 +261,6 @@ typedef enum #define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/ - /** * @} */ @@ -278,7 +277,6 @@ typedef enum */ - /** * @} */ @@ -329,7 +327,6 @@ typedef enum #define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) - /* Interrupt & Flag management */ /** * @brief Get the PSSI pending flags. @@ -398,7 +395,6 @@ typedef enum ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE )) - /** * @brief Check whether the PSSI Bus Width is valid. * @param __BUSWIDTH__ PSSI Bush width @@ -512,7 +508,6 @@ void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h index dcf987bf23..d06704d16f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ramcfg.h @@ -168,8 +168,6 @@ typedef struct /** * @} */ - - /** * @} */ @@ -360,6 +358,7 @@ HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg) * @} */ + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h index 394d30d5f3..64a2ee38bc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h @@ -4705,10 +4705,10 @@ typedef struct * @arg @ref RCC_FLAG_LPWRRST Low Power reset * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) +#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5UL) == 1UL) ? RCC->CR : \ + ((((__FLAG__) >> 5UL) == 2UL) ? RCC->BDCR : \ + ((((__FLAG__) >> 5UL) == 3UL) ? RCC->CSR : RCC->CIFR)))) & \ + (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0UL) ? 1U : 0U) /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h index f51f6806b0..d04f3154ab 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h @@ -346,7 +346,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Enable the SDIO device interrupt. * @param __HANDLE__ SDIO Handle. * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. - * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. * @retval None */ #define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -355,7 +354,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Disable the SDIO device interrupt. * @param __HANDLE__ SDIO Handle. * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. - * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. * @retval None */ #define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -364,7 +362,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Check whether the specified SDIO flag is set or not. * @param __HANDLE__ SDIO Handle. * @param __FLAG__ specifies the flag to check. - * This parameter can be one of @ref SDMMC_LL_Flags. * @retval The new state of SDIO FLAG (SET or RESET). */ #define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) @@ -373,7 +370,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Clear the SDIO's pending flags. * @param __HANDLE__ SDIO Handle. * @param __FLAG__ specifies the flag to clear. - * This parameter can be one or a combination of @ref SDMMC_LL_Flags. * @retval None */ #define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) @@ -382,7 +378,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Check whether the specified SDIO interrupt has occurred or not. * @param __HANDLE__ SDIO Handle. * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. - * This parameter can be one of @ref SDMMC_LL_Interrupt_sources. * @retval The new state of SDIO IT (SET or RESET). */ #define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -434,19 +429,21 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI /** @defgroup SDIO_Exported_Functions_Group3 Process functions * @{ */ -HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); -HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t Data); -HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); -HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); -HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte); -HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h index 612eca067b..fe9e838618 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smartcard.h @@ -726,13 +726,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h index d479fb2211..ff13f9309f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_smbus_ex.h @@ -94,54 +94,54 @@ typedef struct #define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ #define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ -#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) +#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000UL)) /*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI9_TRG */ -#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM2_CH1_TRG */ -#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ -#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ -#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ -#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U)) +#define SMBUS_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000UL)) /*!< HW Trigger signal is LPDMA_CH0_TRG */ -#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH1_TRG */ -#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH2_TRG */ -#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPDMA_CH3_TRG */ -#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI5_TRG */ -#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is EXTI8_TRG */ -#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define SMBUS_GRP2_LPTIM3_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_LPTIM3_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is LPTIM3_CH1_TRG */ -#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP1_TRG */ -#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is COMP2_TRG */ -#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_ALRA_TRG */ -#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos)) /*!< HW Trigger signal is RTC_WUT_TRG */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h index 707bb07494..5b3cdbcb52 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h @@ -86,53 +86,53 @@ typedef struct /* HW Trigger signal is GPDMA_CH0_TRG */ #define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) /* HW Trigger signal is GPDMA_CH1_TRG */ -#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH2_TRG */ -#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is GPDMA_CH3_TRG */ -#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI9_TRG */ -#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM2_CH1_TRG */ -#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is COMP2_TRG */ -#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) #if defined(SPI3) /* HW Trigger signal is LPDMA_CH0_TRG */ #define SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) /* HW Trigger signal is LPDMA_CH1_TRG */ -#define SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPDMA_CH2_TRG */ -#define SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPDMA_CH3_TRG */ -#define SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is EXTI8_TRG */ -#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is LPTIM3_CH1_TRG */ -#define SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x7UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is COMP2_TRG */ -#define SPI_GRP2_COMP2_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_COMP2_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x9UL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAUL << SPI_AUTOCR_TRIGSEL_Pos)) /* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBUL << SPI_AUTOCR_TRIGSEL_Pos)) #endif /* GRP2_AVAILABILITY */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h index bbe19eb398..96a6eb4081 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h @@ -1834,7 +1834,8 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) /** * @} @@ -1881,7 +1882,7 @@ mode. ((__BASE__) == TIM_DMABASE_AF2) || \ ((__BASE__) == TIM_DMABASE_TISEL) || \ ((__BASE__) == TIM_DMABASE_DTR2) || \ - ((__BASE__) == TIM_DMABASE_ECR) || \ + ((__BASE__) == TIM_DMABASE_ECR) || \ ((__BASE__) == TIM_DMABASE_OR1)) #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) @@ -2205,20 +2206,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2232,16 +2228,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h index 240c76c5ae..7325f180af 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h index d08fef2034..78d947462c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h @@ -550,10 +550,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -575,10 +575,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h index 0e3e1edf2f..ad4b892c84 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h @@ -78,6 +78,8 @@ typedef struct to take in account external signal delays. This parameter can be a value of @ref XSPI_SampleShifting */ uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. + Note that for instances with internal calibration, this field is not used + during peripheral initialisation. This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and defines the boundary of bytes to release the chip select. @@ -182,6 +184,7 @@ typedef struct instruction will be sent only once. This parameter can be a value of @ref XSPI_SIOOMode */ } XSPI_RegularCmdTypeDef; + /** * @brief HAL XSPI Hyperbus Configuration Structure definition */ @@ -961,29 +964,30 @@ void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); /* XSPI command configuration functions */ -HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); -HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd); +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCfgTypeDef *pCfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCmdTypeDef *pCmd, uint32_t Timeout); /* XSPI indirect mode functions */ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout); HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); -HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); -HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData); /* XSPI status flag polling mode functions */ -HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg); /* XSPI memory-mapped mode functions */ -HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg); +uint32_t HAL_XSPI_IsMemoryMapped(XSPI_HandleTypeDef *hxspi); /* Callback functions in non-blocking modes ***********************************/ void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); @@ -1038,7 +1042,7 @@ uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); /** @addtogroup XSPI_Exported_Functions_Group4 IO Manager configuration function * @{ */ -HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout); /** * @} @@ -1050,10 +1054,10 @@ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_Cf * @{ */ -HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); -HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); +HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, const HAL_XSPI_DLYB_CfgTypeDef *pdlyb_cfg); +HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *pdlyb_cfg); HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, - HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg); + HAL_XSPI_DLYB_CfgTypeDef *pdlyb_cfg); /** * @} @@ -1064,8 +1068,8 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, /** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions * @{ */ -HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); -HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *pCfg); +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, const XSPI_HSCalTypeDef *pCfg); /** * @} @@ -1094,7 +1098,7 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSC #define IS_XSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_XSPI_MEMTYPE_MICRON) || \ ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX) || \ - ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ + ((TYPE) == HAL_XSPI_MEMTYPE_APMEM) || \ ((TYPE) == HAL_XSPI_MEMTYPE_MACRONIX_RAM) || \ ((TYPE) == HAL_XSPI_MEMTYPE_HYPERBUS) || \ ((TYPE) == HAL_XSPI_MEMTYPE_APMEM_16BITS)) @@ -1314,6 +1318,10 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSC #define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) +#define IS_XSPI_PROG_DATA(SET_DATA, REQ_DATA) ((SET_DATA) == (REQ_DATA)) + +#define IS_XSPI_PROG_ADDR(SET_ADDR, REQ_ADDR) ((SET_ADDR) == (REQ_ADDR)) + #if defined(OCTOSPIM) #define IS_XSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h index 9d72f9aed3..2b4341b580 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h @@ -483,7 +483,7 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x0BFA07A5UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ @@ -491,12 +491,12 @@ extern "C" { VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA0710UL)) /* Internal temperature sensor, address of parameter +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x0BFA0710UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32U5, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC),Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA0742UL)) /* Internal temperature sensor, address of parameter +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x0BFA0742UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32U5, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h index afae552ad3..f26eaf0423 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h @@ -942,7 +942,7 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attrib if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0 accordingly */ - MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else @@ -975,7 +975,7 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Att if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h index cb98f2fd44..622f55f3fc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h @@ -113,8 +113,8 @@ __STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx) * @{ */ -void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); -void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); +void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef *pdlyb_cfg); +void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h index 18bd575f08..cd2b362b5f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h @@ -80,6 +80,8 @@ extern "C" { #define DMA_CHANNEL14_OFFSET (0x00000750UL) #define DMA_CHANNEL15_OFFSET (0x000007D0UL) +#define LL_DMA_CHANNEL_MAX LL_DMA_CHANNEL_15 + /* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ static const uint32_t LL_DMA_CH_OFFSET_TAB[] = { @@ -1642,7 +1644,8 @@ __STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint3 uint32_t LinkedListBaseAddr) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLBAR, + DMA_CLBAR_LBA, (LinkedListBaseAddr & DMA_CLBAR_LBA)); } @@ -1711,7 +1714,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, u __STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); } @@ -1965,7 +1968,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR1, DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); } @@ -2001,7 +2004,7 @@ __STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t uint32_t DestBurstLength) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR1, (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); } @@ -3065,7 +3068,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), Configuration); } @@ -3102,7 +3105,8 @@ __STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TCEM, TransferEventMode); } @@ -3144,7 +3148,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, ui * @brief Set trigger polarity. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -3179,7 +3183,7 @@ __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t * @brief Get trigger polarity. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -3205,14 +3209,15 @@ __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGPOL)); } /** * @brief Set trigger Mode. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -3240,7 +3245,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint __STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGM, TriggerMode); } @@ -3591,7 +3597,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_REQSEL, Request); } /** @@ -3768,7 +3775,8 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_REQSEL)); } /** @@ -3897,7 +3905,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, + DMA_CTR2_TRIGSEL, (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); } @@ -4026,7 +4035,7 @@ __STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR2, DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); } @@ -4053,7 +4062,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); } @@ -4078,7 +4087,7 @@ __STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t uint32_t BlkRptCount) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); } @@ -4101,7 +4110,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uin uint32_t BlkRptDestAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRDDEC, BlkRptDestAddrUpdate); } @@ -4122,7 +4132,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uin __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRDDEC)); } /** @@ -4144,7 +4155,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint uint32_t BlkRptSrcAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRSDEC, BlkRptSrcAddrUpdate); } @@ -4165,7 +4177,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRSDEC)); } /** @@ -4186,7 +4199,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_DDEC, DestAddrUpdate); } @@ -4207,7 +4221,8 @@ __STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_DDEC)); } /** @@ -4228,7 +4243,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_SDEC, SrcAddrUpdate); } @@ -4249,7 +4265,8 @@ __STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_SDEC)); } /** @@ -4269,7 +4286,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BRC, (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); } @@ -4288,7 +4306,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); } @@ -4320,7 +4338,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BNDT, BlkDataLength); } @@ -4351,7 +4370,8 @@ __STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR1, + DMA_CBR1_BNDT)); } /** @@ -4386,8 +4406,8 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Ch DestAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR, DestAddress); } /** @@ -4418,7 +4438,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Ch __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR, SrcAddress); } /** @@ -4448,7 +4468,7 @@ __STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSAR)); } /** @@ -4479,7 +4499,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR, DestAddress); } /** @@ -4509,7 +4529,7 @@ __STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CDAR)); } /** @@ -4532,7 +4552,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint3 uint32_t DestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); } @@ -4552,7 +4572,8 @@ __STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_DAO, ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); } @@ -4571,7 +4592,7 @@ __STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); } @@ -4591,7 +4612,8 @@ __STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_SAO, SrcAddrOffset & DMA_CTR3_SAO); } @@ -4610,7 +4632,8 @@ __STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CTR3, + DMA_CTR3_SAO)); } /** @@ -4633,7 +4656,7 @@ __STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); } @@ -4654,7 +4677,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx uint32_t BlkRptDestAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRDAO, ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); } @@ -4673,7 +4697,7 @@ __STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx __STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); } @@ -4694,7 +4718,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t BlkRptSrcAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRSAO, BlkRptSrcAddrOffset); } @@ -4713,7 +4738,8 @@ __STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, __STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO)); + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CBR2, + DMA_CBR2_BRSAO)); } /** @@ -4762,7 +4788,7 @@ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t C uint32_t LinkedListAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); } @@ -4794,7 +4820,8 @@ __STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT1); } /** @@ -4824,7 +4851,8 @@ __STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT1); } /** @@ -4854,7 +4882,8 @@ __STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT1) == (DMA_CLLR_UT1)) ? 1UL : 0UL); } @@ -4885,7 +4914,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT2); } /** @@ -4915,7 +4945,8 @@ __STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT2); } /** @@ -4945,7 +4976,8 @@ __STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT2) == (DMA_CLLR_UT2)) ? 1UL : 0UL); } @@ -4976,7 +5008,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB1); } /** @@ -5006,7 +5039,8 @@ __STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB1); } /** @@ -5036,7 +5070,8 @@ __STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB1) == (DMA_CLLR_UB1)) ? 1UL : 0UL); } @@ -5067,7 +5102,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_USA); } /** @@ -5097,7 +5133,8 @@ __STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_USA); } /** @@ -5127,7 +5164,8 @@ __STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_USA) == (DMA_CLLR_USA)) ? 1UL : 0UL); } @@ -5158,7 +5196,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UDA); } /** @@ -5188,7 +5227,8 @@ __STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UDA); } /** @@ -5218,7 +5258,8 @@ __STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UDA) == (DMA_CLLR_UDA)) ? 1UL : 0UL); } @@ -5237,7 +5278,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT3); } /** @@ -5255,7 +5297,8 @@ __STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT3); } /** @@ -5273,7 +5316,8 @@ __STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UT3) == (DMA_CLLR_UT3)) ? 1UL : 0UL); } @@ -5292,7 +5336,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB2); } /** @@ -5310,7 +5355,8 @@ __STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB2); } /** @@ -5328,7 +5374,8 @@ __STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_UB2) == (DMA_CLLR_UB2)) ? 1UL : 0UL); } @@ -5359,7 +5406,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uin __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_ULL); } /** @@ -5389,7 +5437,8 @@ __STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t C __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_ULL); } /** @@ -5419,7 +5468,8 @@ __STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_ULL) == (DMA_CLLR_ULL)) ? 1UL : 0UL); } @@ -5452,7 +5502,8 @@ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uin uint32_t LinkedListAddrOffset) { uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, + DMA_CLLR_LA, (LinkedListAddrOffset & DMA_CLLR_LA)); } @@ -5483,7 +5534,7 @@ __STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uin __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CLLR, DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); } @@ -5514,7 +5565,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, __STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); } @@ -5792,7 +5843,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_TOF); } /** @@ -5822,7 +5873,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_SUSPF); } /** @@ -5852,7 +5903,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_USEF); } /** @@ -5882,7 +5933,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_ULEF); } /** @@ -5912,7 +5963,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_DTEF); } /** @@ -5942,7 +5993,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_HTF); } /** @@ -5972,7 +6023,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CFCR, DMA_CFCR_TCF); } /** @@ -6002,7 +6053,8 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_TOF) == (DMA_CSR_TOF)) ? 1UL : 0UL); } @@ -6033,7 +6085,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_SUSPF) == (DMA_CSR_SUSPF)) ? 1UL : 0UL); } @@ -6064,7 +6117,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_USEF) == (DMA_CSR_USEF)) ? 1UL : 0UL); } @@ -6095,7 +6149,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_ULEF) == (DMA_CSR_ULEF)) ? 1UL : 0UL); } @@ -6126,7 +6181,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_DTEF) == (DMA_CSR_DTEF)) ? 1UL : 0UL); } @@ -6157,7 +6213,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_HTF) == (DMA_CSR_HTF)) ? 1UL : 0UL); } @@ -6188,7 +6245,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_TCF) == (DMA_CSR_TCF)) ? 1UL : 0UL); } @@ -6219,7 +6277,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CSR, + DMA_CSR_IDLEF) == (DMA_CSR_IDLEF)) ? 1UL : 0UL); } @@ -6319,7 +6378,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint3 __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TOIE); } /** @@ -6349,7 +6409,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_SUSPIE); } /** @@ -6379,7 +6440,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_USEIE); } /** @@ -6409,7 +6471,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_ULEIE); } /** @@ -6439,7 +6502,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_DTEIE); } /** @@ -6469,7 +6533,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_HTIE); } /** @@ -6499,7 +6564,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TCIE); } /** @@ -6529,7 +6595,8 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channe __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TOIE); } /** @@ -6559,7 +6626,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_SUSPIE); } /** @@ -6589,7 +6657,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Cha __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_USEIE); } /** @@ -6619,7 +6688,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_ULEIE); } /** @@ -6649,7 +6719,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_DTEIE); } /** @@ -6679,7 +6750,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Chan __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_HTIE); } /** @@ -6709,7 +6781,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TCIE); } /** @@ -6739,7 +6812,8 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Chann __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TOIE) == DMA_CCR_TOIE) ? 1UL : 0UL); } @@ -6770,7 +6844,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_SUSPIE) == DMA_CCR_SUSPIE) ? 1UL : 0UL); } @@ -6801,7 +6876,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_USEIE) == DMA_CCR_USEIE) ? 1UL : 0UL); } @@ -6832,7 +6908,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_ULEIE) == DMA_CCR_ULEIE) ? 1UL : 0UL); } @@ -6863,7 +6940,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_DTEIE) == DMA_CCR_DTEIE) ? 1UL : 0UL); } @@ -6894,7 +6972,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_HTIE) == DMA_CCR_HTIE) ? 1UL : 0UL); } @@ -6925,7 +7004,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel & LL_DMA_CHANNEL_MAX]))->CCR, + DMA_CCR_TCIE) == DMA_CCR_TCIE) ? 1UL : 0UL); } /** @@ -6947,7 +7027,7 @@ uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h index 7df97093a7..99e77df745 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmc.h @@ -156,74 +156,75 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE */ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ + @note: This parameter is common to all NSBank. */ } FMC_NORSRAM_InitTypeDef; /** @@ -272,7 +273,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ @@ -790,11 +791,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -822,11 +823,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -837,7 +838,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -848,7 +849,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h index 1fa88dfdaa..f3e035d8b7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h @@ -69,21 +69,20 @@ static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = { - LPTIM_CCMR1_CC1E_Pos, /* CC1E */ - LPTIM_CCMR1_CC2E_Pos /* CC2E */ + (uint8_t)LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + (uint8_t)LPTIM_CCMR1_CC2E_Pos /* CC2E */ }; static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = { - {2, 7, 9, 13}, - {3, 5, 6, 8}, - {2, 3, 4, 5}, - {2, 2, 3, 3}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2}, - {2, 2, 2, 2} - + {2U, 7U, 9U, 13U}, + {3U, 5U, 6U, 8U}, + {2U, 3U, 4U, 5U}, + {2U, 2U, 3U, 3U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U}, + {2U, 2U, 2U, 2U} }; /** @@ -1218,7 +1217,8 @@ __STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, u */ __STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode) { - SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel], + CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h index ed3fb00a25..a0820042bc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h index a152ca2c3f..24ec089d56 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h @@ -45,9 +45,9 @@ extern "C" { */ /* Defines used to perform offsets*/ /* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */ -#define RCC_OFFSET_CCIPR1 0U -#define RCC_OFFSET_CCIPR2 0x04U -#define RCC_OFFSET_CCIPR3 0x08U +#define RCC_OFFSET_CCIPR1 0UL +#define RCC_OFFSET_CCIPR2 0x04UL +#define RCC_OFFSET_CCIPR3 0x08UL /* Defines used for security configuration extension */ #define RCC_SECURE_MASK 0x1FFFU @@ -2952,7 +2952,7 @@ __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \ + MODIFY_REG(*reg, 3UL << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \ (((I2CxSource & 0x00FF0000U) >> 16U) & \ 0x1FU))); } @@ -2981,7 +2981,7 @@ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \ + MODIFY_REG(*reg, 3UL << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \ (((SPIxSource & 0x00FF0000U) >> 16U) & \ 0x1FU))); } @@ -3009,7 +3009,7 @@ __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) { __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \ + MODIFY_REG(*reg, 3UL << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \ (((LPTIMxSource & 0x00FF0000U) >> 16U) & \ 0x1FU))); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h index ea33667602..031cf3308f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h @@ -160,7 +160,7 @@ static const uint8_t SHIFT_TAB_OISx[] = */ #define OCREF_CLEAR_SELECT_POS (28U) -#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ +#define OCREF_CLEAR_SELECT_MSK (0x1UL << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h index 2d18c5b844..d0dd06629f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h @@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h index ac1bb184ad..12e79790a0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h @@ -56,6 +56,7 @@ typedef enum USB_DRD_MODE = 2 } USB_ModeTypeDef; +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief URB States definition */ @@ -66,7 +67,8 @@ typedef enum URB_NOTREADY, URB_NYET, URB_ERROR, - URB_STALL + URB_STALL, + URB_NAK_WAIT } USB_URBStateTypeDef; /** @@ -85,6 +87,7 @@ typedef enum HC_BBLERR, HC_DATATGLERR } USB_HCStateTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** @@ -134,6 +137,7 @@ typedef struct #endif /* defined (USB_DRD_FS) */ } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -197,7 +201,9 @@ typedef struct uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ #endif /* defined (USB_DRD_FS) */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ +#if defined (HAL_HCD_MODULE_ENABLED) typedef struct { uint8_t dev_addr; /*!< USB device address. @@ -206,8 +212,6 @@ typedef struct uint8_t phy_ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t ch_dir; /*!< channel direction - This parameter store the physical channel direction IN/OUT/BIDIR */ #else uint8_t ch_num; /*!< Host channel number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ @@ -218,6 +222,9 @@ typedef struct uint8_t ep_num; /*!< Endpoint number. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint8_t ch_dir; /*!< channel direction + This parameter store the physical channel direction IN/OUT/BIDIR */ + uint8_t speed; /*!< USB Host Channel speed. This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ @@ -263,6 +270,8 @@ typedef struct #if defined (USB_OTG_FS) || defined (USB_OTG_HS) uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + + uint32_t NakCnt; /*!< Host channel NAK count. */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t ErrCnt; /*!< Host channel error count. */ @@ -287,22 +296,36 @@ typedef struct USB_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) typedef USB_EPTypeDef USB_OTG_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + #if defined (USB_DRD_FS) typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) typedef USB_EPTypeDef USB_DRD_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; typedef USB_HCTypeDef USB_DRD_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ #endif /* defined (USB_DRD_FS) */ /* Exported constants --------------------------------------------------------*/ @@ -377,9 +400,9 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency * @{ */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0UL << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1UL << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3UL << 1) /** * @} */ @@ -520,6 +543,12 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; #define TEST_PACKET 4U #define TEST_FORCE_EN 5U +#define USB_OTG_GAHBCFG_HBSTLEN_SINGLE (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR4 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR8 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR16 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) + #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) @@ -580,8 +609,8 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; * @} */ /******************** Bit definition for USB_COUNTn_RX register *************/ -#define USB_CNTRX_NBLK_MSK (0x1FU << 26) -#define USB_CNTRX_BLSIZE (0x1U << 31) +#define USB_CNTRX_NBLK_MSK (0x1FUL << 26) +#define USB_CNTRX_BLSIZE (0x1UL << 31) /*Set Channel/Endpoint to the USB Register */ @@ -1101,18 +1130,23 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); + HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); @@ -1128,13 +1162,17 @@ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, u uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); + +#if defined (HAL_HCD_MODULE_ENABLED) HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); @@ -1143,8 +1181,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -1176,16 +1215,21 @@ uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); + +#if defined (HAL_HCD_MODULE_ENABLED) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num); +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num); HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); +HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); -HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, - uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); @@ -1217,5 +1261,4 @@ void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, } #endif /* __cplusplus */ - #endif /* STM32U5xx_LL_USB_H */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index 22b823558e..3d71ba22a5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,7 +40,7 @@

        Purpose

        Update History

        - +

        Main Changes

          @@ -48,6 +48,116 @@

          Main Changes

        HAL/LL Drivers updates

          +
        • HAL Generic driver +
            +
          • Update HAL_SetTickFreq() API to restore current tick frequency when call to HAL_InitTick() fails.
            • +
          • +
        • HAL/LL GPIO driver +
            +
          • Update HAL_GPIO_Init() API to add Pull down capability in analog mode.
            • +
          • +
        • HAL/LL DMA driver +
            +
          • Remove extra unused parentheses in HAL_DMA_IRQHandler.
            • +
          • Add attribute ((no_inline)) to DMA_List_CheckNodesBaseAddresse() API to avoid warning with GCC compiler.
            • +
          • Add DMA XferSuspendCallback initialization before starting DMA transfers in HAL UART.
            • +
          • Add initialization of callbacks in HAL_DMA_Init() API.
            • +
          • +
        • HAL FLASH driver +
            +
          • Replace the timeout calculation in HAL_GetTick() to determine elapsed time instead of adding a fixed timeout value.
            • +
          • +
        • HAL/LL ADC driver +
            +
          • Remove assert in HAL_ADC_ConfigChannel() API.
            • +
          • Update ADC calibration values as addresses of const data.
            • +
          • +
        • HAL/LL TIM driver +
            +
          • Update TIM_CCER_CCxE_MASK to support internal TIM Channel5 and TIM Channel6.
            • +
          • +
        • HAL/LL LPTIM driver +
            +
          • Fix LL_LPTIM_CC_SetChannelMode() static function to manage properly on the fly channel mode changes.
            • +
          • +
        • HAL/LL UART driver +
            +
          • Provide accurate position in RxEventCallback when ReceptionToIdle mode is used with DMA, when UART and DMA interrupts process is delayed.
            • +
          • +
        • HAL/LL USART driver +
            +
          • Solve Coverity out-of-bound memory access warning in use of USART_PRESCALER_TAB array.
            • +
          • +
        • HAL OCTOSPI driver +
            +
          • Change ChipSelectHighTime max limits to 64 to feat with specification.
            • +
          • +
        • HAL/LL SPI driver +
            +
          • Clear auto suspend flag in HAL_SPI_Receive() API.
            • +
          • Fix buffer overflow in TX interrupt service routine.
            • +
          • +
        • HAL XSPI driver +
            +
          • Add asserts to inform user when data size or address requested is not compatible with current XSPI configuration.
            • +
          • Check BUSY flag instead of TC flag in indirect mode to be sure that command is well completed (FIFO flush).
            • +
          • +
        • LL LPUART driver +
            +
          • Solve Coverity out-of-bound memory access warning in use of LPUART_PRESCALER_TAB array.
            • +
          • +
        • HAL/LL RTC_BKP driver +
            +
          • Complete the check on the tamper trigger configuration in HAL_RTCEx_SetTamper_IT() API to be the same as in HAL_RTCEx_SetTamper() API.
            • +
          • Add an ‘else’ block to the ‘if’ statement that checks the RTC binary mode in HAL_RTC_Init() API.
            • +
          • Remove useless second write access to TAMP->IER register from HAL_RTCEx_SetActiveTampers() API.
            • +
          • +
        • HAL CRC driver +
            +
          • Replace successive ‘if’ statements by ‘else if’ to improve checksum calculation performance in CRC_Handle_8() function.
            • +
          • +
        • HAL FMAC driver +
            +
          • Complete DMA Abort sequence in HAL_FMAC_FilterStop()
            • +
          • +
        • HAL/LL PKA driver +
            +
          • Update PKA_ModExpFastMode_Set() function to solve the issue when data is not multiple of 4 bytes for PKA Modular Exponentiation Fast Mode.
            • +
          • Add specific LL PKA API to check the PKA initialization OK status: LL_PKA_IsActiveFlag_INITOK() API.
            • +
          • +
        • HAL/LL NAND driver +
            +
          • Update bug in HAL_NAND_Read_Page_8b(), HAL_NAND_Read_Page_16b(), HAL_NAND_Read_SpareArea_8b() and HAL_NAND_Read_SpareArea_16b() APIs to ensure correct data reads.
            • +
          • +
        • HAL JPEG driver +
            +
          • Update JPEG_DMA_ContinueProcess() function to use blocking DMA abort.
            • +
          • Remove multiple volatile reads in interrupt handler in JPEG_Process() and JPEG_DMA_ContinueProcess() functions.
            • +
          • +
        • HAL USB-FS driver +
            +
          • Fix USB PCD setup and data buffers overflow (SA0035).
            • +
          • +
        +

        Known Limitations

        +
          +
        • N/A
          • +
        +

        Backward compatibility

        +
          +
        • N/A
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • General updates to fix known defects and implementation enhancements.
          • +
        +

        HAL/LL Drivers updates

        +
        • HAL/LL ADC driver
          • Add LL_ADC_IsActiveFlag_LDORDY() macro to get ADC internal voltage regulator ready flag.
            • @@ -178,11 +288,11 @@

            HAL/LL Drivers updates

          • Fix the condition on EONUM flag of DOEPCTLx register in HAL_PCD_IRQHandler() to correctly check on the frame number parity.
        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -191,12 +301,12 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • Maintenance Release V1.6.0 of STM32CubeU5 Firmware Package to deploy the new HAL SDIO driver.
        • General updates to fix known defects and implementation enhancements.
        -

        HAL/LL Drivers updates

        +

        HAL/LL Drivers updates

        • HAL GENERIC driver
            @@ -220,11 +330,11 @@

            HAL/LL Drivers updates

          • Support new HAL SDIO driver.
        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -233,7 +343,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers Maintenance Release for STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U599xx/STM32U5A9xx, STM32U595xx/STM32U5A5xx, STM32U5F9xx/STM32U5G9xx and STM32U5F7xx/STM32U5G7xx devices
        • Add the HAL MMC replay protected memory block management feature
          • @@ -414,11 +524,11 @@

          LL Drivers updates

        • Rename LL_UTILS_PACKAGETYPE_WLCSP144_SMPS to LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS define
      -

      Known Limitations

      +

      Known Limitations

      • N/A
      -

      Backward compatibility

      +

      Backward compatibility

      • N/A
      @@ -427,7 +537,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • HAL and LL drivers Maintenance Release for STM32U5XX devices
      • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
        • @@ -451,11 +561,11 @@

        LL Drivers updates

      • Add new Helper macro for differential mode raw data to voltage conversion
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -464,7 +574,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
    • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
      • @@ -554,11 +664,11 @@

      LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -567,7 +677,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
  • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
    • @@ -767,11 +877,11 @@

    LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -780,7 +890,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
  • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
    • @@ -1007,11 +1117,11 @@

    LL Drivers updates

Backward compatibility ensured by legacy defines

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -1020,7 +1130,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
@@ -1036,11 +1146,11 @@

LL Drivers updates

  • Backward compatibility ensured by legacy defines
    • -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -1049,7 +1159,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    @@ -1098,11 +1208,11 @@

    LL Drivers updates

  • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
    • -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -1111,11 +1221,11 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index b587c12cca..cb2e9c1662 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,12 +52,12 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.6.1 + * @brief STM32U5xx HAL Driver version number 1.6.2 */ -#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ -#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32U5xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x02UL) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32U5xx_HAL_VERSION_SUB2 << 8U )\ @@ -359,16 +359,25 @@ uint32_t HAL_GetTickPrio(void) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); - - if (status == HAL_OK) + if (status != HAL_OK) { - uwTickFreq = Freq; + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c index daa4b1445b..dc8d8e7d28 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc.c @@ -3320,9 +3320,6 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff)); assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber)); assert_param(IS_ADC_RANGE(hadc->Instance, ADC_GET_RESOLUTION(hadc), pConfig->Offset)); - /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is - ignored (considered as reset) */ - assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c index 06ed059349..cf7374a1be 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc.c @@ -452,13 +452,13 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ } - if ((BufferLength % 4U) == 2U) + else if ((BufferLength % 4U) == 2U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } - if ((BufferLength % 4U) == 3U) + else if ((BufferLength % 4U) == 3U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ @@ -466,6 +466,10 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } + else + { + /* Nothing to do */ + } } /* Return the CRC computed value */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c index 58db907051..5207ddfde5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c @@ -273,6 +273,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Allocate lock resource */ __HAL_UNLOCK(hdma); + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -903,7 +914,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Data Transfer Error Interrupt management *************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) @@ -917,7 +928,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Update Linked-list Error Interrupt management ********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) @@ -931,7 +942,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* User Setting Error Interrupt management **************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) @@ -945,7 +956,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Trigger Overrun Interrupt management *****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) @@ -959,7 +970,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Half Transfer Complete Interrupt management **********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) @@ -977,7 +988,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Suspend Transfer Interrupt management ****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) @@ -1035,7 +1046,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Transfer Complete Interrupt management ***************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) @@ -1487,7 +1498,6 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *co return HAL_OK; } - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /** * @brief Lock the DMA channel security and privilege attribute(s). @@ -1529,7 +1539,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) { - DMA_TypeDef *p_dma_instance; + const DMA_TypeDef *p_dma_instance; uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c index 92df0abed5..11580366af 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma2d.c @@ -118,7 +118,7 @@ and a pointer to the user callback function. (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -130,16 +130,16 @@ (+) MspDeInitCallback : DMA2D MspDeInit. (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init + reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Exception as well for Transfer Completion and Transfer Error callbacks that are not defined - as weak (surcharged) functions. They must be defined by the user to be resorted to. + as weak (overridden) functions. They must be defined by the user to be resorted to. Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered @@ -151,7 +151,7 @@ When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. [..] (@) You can refer to the DMA2D HAL driver header file for more useful macros @@ -431,7 +431,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief Register a User DMA2D Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -530,7 +530,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM /** * @brief Unregister a DMA2D Callback - * DMA2D Callback is redirected to the weak (surcharged) predefined callback + * DMA2D Callback is redirected to the weak (overridden) predefined callback * @param hdma2d DMA2D handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -571,11 +571,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ break; case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ break; default : @@ -591,11 +591,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ switch (CallbackID) { case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ break; case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ break; default : diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c index d60eca23d8..12bfe615a5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -537,9 +537,15 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, DMA_NodeTypeDef *const pNode); static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3); +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3); +#endif /* __GNUC__ && !__CC_ARM */ static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3); @@ -3897,19 +3903,6 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ - - - /* Update CLLR register value *************************************************************************************/ - /* Reset CLLR Register value : channel linked-list address register offset */ - pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; - /********************************************************************************* CLLR register value is cleared */ - } - else - { - /* Update CLLR register value *************************************************************************************/ - /* Reset CLLR Register value : channel linked-list address register offset */ - pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; - /********************************************************************************* CLLR register value is cleared */ } /* Update node information value ************************************************************************************/ @@ -4095,9 +4088,15 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, \ + DMA_NodeTypeDef const *const pNode2, \ + DMA_NodeTypeDef const *const pNode3) +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3) +#endif /* __GNUC__ && !__CC_ARM */ { uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); uint32_t ref = 0U; @@ -4466,7 +4465,7 @@ static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, uint32_t contextnode_reg_counter = 0U; uint32_t cllr_idx; uint32_t cllr_mask; - DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c index 5a8d835d43..7a8ab2cb0b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c @@ -626,7 +626,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset. Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t tickstart = HAL_GetTick(); uint32_t error; __IO uint32_t *reg_sr; @@ -637,7 +637,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if (Timeout != HAL_MAX_DELAY) { - if (HAL_GetTick() >= timeout) + if(((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c index 0e65908df9..9a20587dab 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c @@ -1226,14 +1226,20 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) { - /* Disable the DMA stream managing FMAC input data */ - status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + if (HAL_DMA_GetState(hfmac->hdmaIn) != HAL_DMA_STATE_READY) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } } if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) { - /* Disable the DMA stream managing FMAC output data */ - status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + if (HAL_DMA_GetState(hfmac->hdmaOut) != HAL_DMA_STATE_READY) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } } /* Reset FMAC unit (internal pointers) */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c index 7208911bec..289a3abc8f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c @@ -301,7 +301,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) p_gpio->OTYPER = tmp; } - if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) + if ((pGPIO_Init->Mode != GPIO_MODE_ANALOG) || + ((pGPIO_Init->Mode == GPIO_MODE_ANALOG) && (pGPIO_Init->Pull != GPIO_PULLUP))) { /* Check the Pull parameters */ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c index ad79d6e82e..f14b6670da 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c @@ -50,6 +50,9 @@ (#)Enable HCD transmission and reception: (##) HAL_HCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -1249,6 +1252,24 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu return HAL_OK; } + + +/** @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} /** * @} */ @@ -1372,6 +1393,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + hhcd->hc[chnum].NakCnt = 0U; + if (hhcd->hc[chnum].do_ssplit == 1U) { hhcd->hc[chnum].do_csplit = 1U; @@ -1384,6 +1407,14 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + tmpreg = USBx_HC(chnum)->HCCHAR; + + if ((tmpreg & USB_OTG_HCCHAR_CHDIS) != 0U) + { + /* Halt received while channel disable still in progress */ + return; + } + if (hhcd->hc[chnum].state == HC_XFRC) { hhcd->hc[chnum].state = HC_HALTED; @@ -1398,19 +1429,38 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (hhcd->hc[chnum].state == HC_DATATGLERR)) { hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].ErrCnt > 2U) + + if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].do_ssplit == 1U) + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[chnum].do_csplit = 0U; - hhcd->hc[chnum].ep_ss_schedule = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].urb_state = URB_ERROR; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } } else { @@ -1501,11 +1551,24 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; +#if defined (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE) && (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE == 1) + hhcd->hc[chnum].NakCnt++; + + if (hhcd->hc[chnum].NakCnt >= HAL_HCD_CHANNEL_NAK_COUNT) + { + hhcd->hc[chnum].state = HC_IDLE; + hhcd->hc[chnum].urb_state = URB_NAK_WAIT; + hhcd->hc[chnum].NakCnt = 0U; + } + else +#endif /* defined (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE) && (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE == 1) */ + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } } else if (hhcd->hc[chnum].state == HC_BBLERR) @@ -2260,7 +2323,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, else { /* This is a dual EP0 PMA allocation */ - hhcd->ep0_PmaAllocState |= (0x1U << 12); + hhcd->ep0_PmaAllocState |= (0x1UL << 12); /* PMA Dynamic Allocation for EP0 OUT direction */ hhcd->hc[ch_num & 0xFU].ch_dir = CH_OUT_DIR; @@ -3477,6 +3540,24 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu return HAL_OK; } +/** + * @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} + #if (USE_USB_DOUBLE_BUFFER == 1U) /** * @brief Handle Host Channel OUT Double Buffer Bulk requests. @@ -4478,7 +4559,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) while ((j <= 31U) && (FreeBlocks != NbrReqBlocks)) { /* check if block j is free */ - if ((Entry & ((uint32_t)1U << j)) == 0U) + if ((Entry & ((uint32_t)1UL << j)) == 0U) { if (FreeBlocks == 0U) { @@ -4489,7 +4570,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) j++; /* Parse Column PMALockTable */ - while ((j <= 31U) && ((Entry & ((uint32_t)1U << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) + while ((j <= 31U) && ((Entry & ((uint32_t)1UL << j)) == 0U) && (FreeBlocks < NbrReqBlocks)) { FreeBlocks++; j++; @@ -4497,7 +4578,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) /* Free contiguous Blocks not found */ if (((FreeBlocks < NbrReqBlocks) && (j < 31U)) || - ((j == 31U) && ((Entry & ((uint32_t)1U << j)) != 0U))) + ((j == 31U) && ((Entry & ((uint32_t)1UL << j)) != 0U))) { FreeBlocks = 0U; } @@ -4515,7 +4596,7 @@ static uint16_t HAL_HCD_GetFreePMA(HCD_HandleTypeDef *hhcd, uint16_t mps) { for (uint8_t j = ColIndex; j <= 31U; j++) { - hhcd->PMALookupTable[i] |= ((uint32_t)1U << j); + hhcd->PMALookupTable[i] |= ((uint32_t)1UL << j); if (--FreeBlocks == 0U) { break; @@ -4574,7 +4655,7 @@ HAL_StatusTypeDef HAL_HCD_PMAlloc(HCD_HandleTypeDef *hhcd, uint8_t ch_num, { hhcd->ep0_PmaAllocState &= 0xFFF0U; hhcd->ep0_PmaAllocState |= ch_num; - hhcd->ep0_PmaAllocState |= (1U << 8); + hhcd->ep0_PmaAllocState |= (1UL << 8); } /* Configure the PMA */ @@ -4707,7 +4788,7 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd) /* Allocate a Space for buffer descriptor table depending on the Host channel number */ for (uint8_t i = 0U; i < hhcd->Init.Host_channels; i++) { - hhcd->PMALookupTable[0] |= ((uint32_t)1U << i); + hhcd->PMALookupTable[0] |= ((uint32_t)1UL << i); } return HAL_OK; @@ -4769,12 +4850,12 @@ static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_ for (uint8_t j = ColIndex; j <= 31U; j++) { /* Check if the block is not already reserved or it was already closed */ - if ((hhcd->PMALookupTable[i] & ((uint32_t)1U << j)) == 0U) + if ((hhcd->PMALookupTable[i] & ((uint32_t)1UL << j)) == 0U) { return HAL_ERROR; } /* Free the reserved block by resetting the corresponding bit */ - hhcd->PMALookupTable[i] &= ~(1U << j); + hhcd->PMALookupTable[i] &= ~(1UL << j); if (--block_nbr == 0U) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c index 3b1a2ee7f0..eab49cd8cc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -6665,7 +6665,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6821,7 +6821,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -7329,7 +7329,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7369,7 +7369,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7408,7 +7408,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7486,7 +7486,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c index b1c88eacc7..5c14cd9f30 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c @@ -298,7 +298,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) #if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) /** * @brief Register a User IWDG Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hiwdg IWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_ /** * @brief Unregister a IWDG Callback - * IWDG Callback is redirected to the weak (surcharged) predefined callback + * IWDG Callback is redirected to the weak (overridden) predefined callback * @param hiwdg IWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c index 73de85eb06..65f06eb629 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_jpeg.c @@ -353,6 +353,7 @@ typedef struct * @{ */ +/* The following Huffman tables, are based on the JPEG standard as defined by the ITU-T Recommendation T.81. */ static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable = { { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/ @@ -3368,11 +3369,12 @@ static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { uint32_t tmpContext; + uint32_t itflag = hjpeg->Instance->SR; /*End of header processing flag */ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) + if ((itflag & JPEG_FLAG_HPDF) != 0UL) { /*Call Header parsing complete callback */ (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); @@ -3398,13 +3400,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) /*Input FIFO status handling*/ if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL) + if ((itflag & JPEG_FLAG_IFTF) != 0UL) { /*Input FIFO threshold flag */ /*JPEG_FIFO_TH_SIZE words can be written in */ JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE); } - else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL) + else if ((itflag & JPEG_FLAG_IFNFF) != 0UL) { /*Input FIFO Not Full flag */ /*32-bit value can be written in */ @@ -3416,17 +3418,16 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) } } - /*Output FIFO flag handling*/ if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL) + if ((itflag & JPEG_FLAG_OFTF) != 0UL) { /*Output FIFO threshold flag */ /*JPEG_FIFO_TH_SIZE words can be read out */ JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE); } - else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) + else if ((itflag & JPEG_FLAG_OFNEF) != 0UL) { /*Output FIFO Not Empty flag */ /*32-bit value can be read out */ @@ -3439,7 +3440,7 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) } /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/ - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF) + if ((itflag & (JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF)) == JPEG_FLAG_EOCF) { /*Stop Encoding/Decoding*/ hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; @@ -3498,7 +3499,6 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) return JPEG_PROCESS_DONE; } - return JPEG_PROCESS_ONGOING; } @@ -3690,6 +3690,9 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord /** * @brief Start the JPEG DMA process (encoding/decoding) + * @note The DMA interrupt must have a higher priority than the JPEG + * interrupt to prevent the JPEG interrupt from preempting the DMA interrupt + * before the DMA state is updated to ready. * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING @@ -3824,10 +3827,12 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) */ static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) { + uint32_t itflag = hjpeg->Instance->SR; + /*End of header processing flag rises*/ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) + if ((itflag & JPEG_FLAG_HPDF) != 0UL) { /*Call Header parsing complete callback */ (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); @@ -3852,9 +3857,9 @@ static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) } /*End of Conversion handling*/ - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != 0UL) + if ((itflag & JPEG_FLAG_EOCF) != 0UL) { - /*Disabkle JPEG In/Out DMA Requests*/ + /*Disable JPEG In/Out DMA Requests*/ JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA); hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA; @@ -3870,19 +3875,19 @@ static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) if (hjpeg->hdmain->State == HAL_DMA_STATE_BUSY) { /* Stop the DMA In Xfer*/ - (void) HAL_DMA_Abort(hjpeg->hdmain); + (void) HAL_DMA_Abort_IT(hjpeg->hdmain); } if (hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY) { /* Stop the DMA out Xfer*/ - (void) HAL_DMA_Abort(hjpeg->hdmaout); + (void) HAL_DMA_Abort_IT(hjpeg->hdmaout); + } + else + { + JPEG_DMA_EndProcess(hjpeg); } - - JPEG_DMA_EndProcess(hjpeg); } - - } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c index 3ea9aaea58..b395a3c149 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c @@ -486,7 +486,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) { uint32_t errorstate; - MMC_InitTypeDef Init; + MMC_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for MMC card initialization */ @@ -3368,7 +3368,7 @@ HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) { /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, - ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U))); + ((hmmc->MmcCard.RelCardAdd << 16UL) | (0x1UL << 15UL))); if (errorstate == HAL_MMC_ERROR_NONE) { /* Wait that the device is ready by checking the D0 line */ @@ -3986,7 +3986,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) uint32_t response = 0U; uint32_t count; uint32_t sdmmc_clk; - SDMMC_InitTypeDef Init; + SDMMC_InitTypeDef Init = {0U}; if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c index 416c295792..b6ef53653c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_nand.c @@ -495,7 +495,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; @@ -638,7 +638,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceaddress; + *buff = *(__IO uint8_t *)deviceaddress; buff++; } @@ -806,7 +806,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceaddress; + *buff = *(__IO uint16_t *)deviceaddress; buff++; } @@ -1288,7 +1288,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceaddress; + *buff = *(__IO uint8_t *)deviceaddress; buff++; } @@ -1453,7 +1453,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceaddress; + *buff = *(__IO uint16_t *)deviceaddress; buff++; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c index 02447f6ea9..a67f01d8c5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_otfdec.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2021 STMicroelectronics. + * Copyright (c) 2020 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -780,16 +780,16 @@ HAL_StatusTypeDef HAL_OTFDEC_ConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, uin * @param pKey pointer at set of keys * @retval CRC value */ -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey) { uint8_t crc7_poly = 0x7; - uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; + const uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; uint8_t i; uint8_t crc = 0; uint32_t j; uint32_t keyval; uint32_t k; - uint32_t *temp = pKey; + const uint32_t *temp = pKey; for (j = 0U; j < 4U; j++) { @@ -890,9 +890,6 @@ HAL_StatusTypeDef HAL_OTFDEC_Cipher(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance)); assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex)); - /* Prevent unused argument(s) compilation warning */ - UNUSED(RegionIndex); - if ((input == NULL) || (output == NULL) || (size == 0U)) { return HAL_ERROR; @@ -1025,7 +1022,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 * the configuration information for OTFDEC module * @retval HAL state */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec) { return hotfdec->State; } @@ -1064,9 +1061,9 @@ HAL_StatusTypeDef HAL_OTFDEC_GetConfigAttributes(OTFDEC_HandleTypeDef *hotfdec, * @param RegionIndex index of region the keys CRC of which is read * @retval Key CRC */ -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef *region; + const OTFDEC_Region_TypeDef *region; uint32_t address; uint32_t keycrc; @@ -1123,7 +1120,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint Config->EndAddress = READ_REG(region->REG_END_ADDR); /* Read Version */ - Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & + Config->Version = (READ_REG(region->REG_CONFIGR) & OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; /* Release Lock */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c index bed0c62be8..d9216a6dff 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c @@ -51,6 +51,9 @@ (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -1450,8 +1453,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) { - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + /* disable the EP */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); } } } @@ -1485,7 +1489,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1UL << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -2301,6 +2305,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7UL << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; @@ -2602,6 +2607,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -2622,26 +2639,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else + { + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -2707,7 +2725,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -2720,6 +2737,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c index 1e61af7f86..c6c953447e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c @@ -324,7 +324,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { PCD_EPTypeDef *ep; - /* initialize ep structure*/ + /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; @@ -339,6 +339,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Single Buffer */ ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } @@ -347,6 +348,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; + /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); @@ -366,13 +368,11 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USB_DRD_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 1U; - /* Enable BCD feature */ - USBx->BCDR |= USB_BCDR_BCDEN; - - /* Enable DCD : Data Contact Detect */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_SDEN); - USBx->BCDR |= USB_BCDR_DCDEN; + + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; return HAL_OK; } @@ -404,21 +404,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) uint32_t tickstart = HAL_GetTick(); /* Wait for Min DCD Timeout */ - HAL_Delay(300U); + HAL_Delay(350U); - /* Data Pin Contact ? Check Detect flag */ - if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - HAL_Delay(50U); USBx->BCDR |= (USB_BCDR_PDEN); HAL_Delay(50U); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c index c03abefccb..f8228c9fd4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ramcfg.c @@ -76,8 +76,11 @@ call HAL_RAMCFG_GetDoubleErrorAddress() to get the address of the last fail RAM word detected (only for double error). - (+) Call HAL_RAMCFG_IsECCErrorDetected() to check if an ECC single/double - error was detected. This API is used in silent mode (No ECC interrupt + (+) Call HAL_RAMCFG_IsECCSingleErrorDetected() to check if an ECC single + error was detected. + Call HAL_RAMCFG_IsECCDoubleErrorDetected() to check if an ECC double + error was detected. + These APIs are used in silent mode (No ECC interrupt is enabled). *** Wait State feature *** @@ -227,7 +230,7 @@ HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg) /* Clear RAMCFG monitor flags */ __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAGS_ALL); - /* Initialise the RAMCFG error code */ + /* Initialize the RAMCFG error code */ hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE; /* Initialize the RAMCFG state */ @@ -339,8 +342,10 @@ __weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg) The HAL_RAMCFG_DisableNotification() function allows disabling interrupts for single ECC error, double ECC error. When NMI interrupt is enabled it can only be disabled by a global peripheral reset or by a system reset. - The HAL_RAMCFG_IsECCErrorDetected() function allows to check if an ECC error - has occurred. + The HAL_RAMCFG_IsECCSingleErrorDetected() function allows to check if an + single ECC error has occurred. + The HAL_RAMCFG_IsECCDoubleErrorDetected() function allows to check if an + double ECC error has occurred. The HAL_RAMCFG_GetSingleErrorAddress() function allows to get the address of the last single ECC error detected. The HAL_RAMCFG_GetDoubleErrorAddress() function allows to get the address of diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c index 236e5ca5ee..b0c5e03394 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c @@ -66,8 +66,10 @@ =================================================================== [..] (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. + (+) Configure the RTC prescalers (asynchronous and synchronous), the RTC mode + (binary, BCD or mix) and the RTC hour format using the HAL_RTC_Init() function. + (+) In order to reconfigure the RTC peripheral, it is necessary to use HAL_RTC_DeInit() + first, then use HAL_RTC_Init() again. *** Time and Date configuration *** =================================== @@ -401,11 +403,15 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } + else + { + /* The calendar does not need to be initialized as the 'binary only' mode is selected */ + status = HAL_OK; + } } else { - /* Calendar is already initialized */ - /* Set flag to OK */ + /* The calendar is already initialized */ status = HAL_OK; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c index c3212591e6..3332178e8c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc_ex.c @@ -28,8 +28,10 @@ ============================================================================== [..] (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. + (+) Configure the RTC prescalers (asynchronous and synchronous), the RTC mode + (binary, BCD or mix) and the RTC hour format using the HAL_RTC_Init() function. + (+) In order to reconfigure the RTC peripheral, it is necessary to use HAL_RTC_DeInit() + first, then use HAL_RTC_Init() again. *** RTC Wakeup configuration *** ================================ @@ -87,10 +89,6 @@ with interrupt mode using HAL_RTCEx_SetTamper_IT() function. (+) The default configuration of the Tamper erases the backup registers. To avoid erase, enable the NoErase field on the RTC_TAMPCR register. - (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to - perform TAMP base address offset calculation. - (+) If you do not intend to have tamper using RTC clock, you can bypass its initialization - by setting ClockEnable inti field to RTC_CLOCK_DISABLE. (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using setting Interrupt field. @@ -1591,7 +1589,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | \ (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); - if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) { tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); } @@ -1756,7 +1754,6 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active } } - WRITE_REG(TAMP->IER, IER); WRITE_REG(TAMP->IER, IER); WRITE_REG(TAMP->ATCR1, ATCR1); WRITE_REG(TAMP->ATCR2, ATCR2); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c index ff309d5e65..43fe1362e8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sai_ex.c @@ -39,7 +39,7 @@ /** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines * @{ */ -#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_MASK 0x77UL #define SAI_PDM_DELAY_OFFSET 8U #define SAI_PDM_RIGHT_DELAY_OFFSET 4U /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c index af08837d2c..c9e8b610ab 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c @@ -465,7 +465,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; - SD_InitTypeDef Init; + SD_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for SD card initialization */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c index 83b3e70525..eda719c34c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c @@ -256,18 +256,18 @@ #define IS_SDIO_FUNCTION(FN) (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7)) -#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) +#define IS_SDIO_SUPPORTED_BLOCK_SIZE(SDIO_BLOCKSIZE) (((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) /* Private functions -------------------------------------------------------------------------------------------------*/ /** @defgroup SDIO_Private_Functions SDIO Private Functions @@ -277,10 +277,10 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio); static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, - uint8_t *pData); + const uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, uint8_t *pData, uint16_t Size_byte); -static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size); +static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size); static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); /** * @} @@ -312,7 +312,7 @@ static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); */ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) { - SDIO_InitTypeDef Init; + SDIO_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; uint8_t data; @@ -376,8 +376,15 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) (void)SDMMC_PowerState_ON(hsdio->Instance); /* wait 74 Cycles: required power up waiting time before starting the SDIO initialization sequence */ - sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); - HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } if (hsdio->SDIO_IdentifyCard == NULL) { @@ -805,7 +812,8 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI * @param pData: pointer to the buffer that will contain the received data. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData) +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t *pData) { uint32_t cmd; uint32_t errorstate; @@ -870,7 +878,8 @@ HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Direct * @param Data: pointer to the buffer that will contain the received data. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data) +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t Data) { uint32_t cmd; uint32_t errorstate; @@ -934,7 +943,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Direc * @param Timeout_Ms: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) { uint32_t cmd; @@ -1032,10 +1041,10 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (regCount = 0U; regCount < 8U; regCount++) + for (regCount = 0U; regCount < (SDMMC_FIFO_SIZE / 4U); regCount++) { data = SDMMC_ReadFIFO(hsdio->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -1047,11 +1056,11 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } - else if (dataremaining < 32U) + else if (dataremaining < SDMMC_FIFO_SIZE) { - while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE))) + while (!(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE)) && (dataremaining > 0U)) { data = SDMMC_ReadFIFO(hsdio->Instance); for (byteCount = 0U; byteCount < 4U; byteCount++) @@ -1143,7 +1152,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte * @param Timeout_Ms: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) { uint32_t cmd; @@ -1236,19 +1245,20 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Ext SDMMC_FLAG_DATAEND)) { - if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (regCount = 0U; regCount < 8U; regCount++) + for (regCount = 0U; regCount < (SDMMC_FIFO_SIZE / 4U); regCount++) { hsdio->Instance->FIFO = *u32tempbuff; u32tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } - else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + else if ((__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)) && + (dataremaining < SDMMC_FIFO_SIZE)) { - uint8_t *u8buff = (uint8_t *)u32tempbuff; + const uint8_t *u8buff = (uint8_t *)u32tempbuff; while (dataremaining > 0U) { data = 0U; @@ -1335,7 +1345,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Ext * @param Size_byte: Block size to write. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte) { SDMMC_DataInitTypeDef config; @@ -1467,7 +1477,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ * @param Size_byte: Block size to write. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte) { uint32_t cmd; @@ -1665,7 +1675,6 @@ void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio) } hsdio->Context = SDIO_CONTEXT_NONE; - hsdio->State = HAL_SDIO_STATE_READY; } if (hsdio->remaining_data != 0U) @@ -2606,7 +2615,7 @@ static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t add * @retval HAL status */ static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, - uint32_t function_nbr, uint8_t *pData) + uint32_t function_nbr, const uint8_t *pData) { uint32_t errorstate; uint32_t cmd; @@ -2719,18 +2728,20 @@ static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && + (dataremaining >= SDMMC_FIFO_SIZE)) { - for (regCount = 8U; regCount > 0U; regCount--) + for (regCount = SDMMC_FIFO_SIZE / 4U; regCount > 0U; regCount--) { SDMMCx->FIFO = *u32tempbuff; u32tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } - else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + else if ((__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)) && + (dataremaining < SDMMC_FIFO_SIZE)) { - uint8_t *u8buff = (uint8_t *)u32tempbuff; + const uint8_t *u8buff = (uint8_t *)u32tempbuff; while (dataremaining > 0U) { data = 0U; @@ -2801,7 +2812,7 @@ static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ * @param block_size: block size in bytes * @retval block size as DBLOCKSIZE[3:0] bits format */ -static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size) +static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size) { UNUSED(hsdio); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c index 7cbe69b9a3..c4508ad72d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smbus.c @@ -1965,7 +1965,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2393,7 +2393,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c index 86f93668e9..69e27c0c32 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c @@ -62,17 +62,17 @@ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. Function HAL_SPI_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) SuspendCallback : SPI Suspend callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) SuspendCallback : SPI Suspend callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -82,17 +82,17 @@ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) SuspendCallback : SPI Suspend callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) SuspendCallback : SPI Suspend callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET all callbacks are set to the corresponding weak functions: @@ -3819,13 +3819,15 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 8 Bit mode */ - *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->TxXferCount == 0UL) + if (hspi->TxXferCount != 0UL) + { + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + else { + /* Disable IT if no more data expected */ /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); } @@ -3840,19 +3842,21 @@ static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ + if (hspi->TxXferCount != 0UL) + { #if defined (__GNUC__) - __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->TxXferCount == 0UL) + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else { + /* Disable IT if no more data expected */ /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); } @@ -3867,13 +3871,15 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 32 Bit mode */ - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->TxXferCount == 0UL) + if (hspi->TxXferCount != 0UL) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + } + else { + /* Disable IT if no more data expected */ /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c index 608f284e3b..b817b75128 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sram.c @@ -1162,6 +1162,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1184,6 +1185,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1206,6 +1208,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c index 48d7aa5653..5b7027e1fa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c @@ -7343,12 +7343,13 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 1N: Reset the CC1NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC1NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7419,12 +7420,13 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 2N: Reset the CC2NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC2NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7494,12 +7496,13 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 3N: Reset the CC3NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC3NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7570,12 +7573,13 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 4N: Reset the CC4NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC4NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC4NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 12U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC4NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7870,9 +7874,18 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7916,9 +7929,18 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7960,9 +7982,18 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7999,9 +8030,18 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -8043,9 +8083,18 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 3: Reset the CC3E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; + /* Disable the Channel 3N: Reset the CC3NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + TIMx->CCER &= ~TIM_CCER_CC3NE; + } + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -8091,9 +8140,18 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 4: Reset the CC4E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; + /* Disable the Channel 4N: Reset the CC4NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) + { + TIMx->CCER &= ~TIM_CCER_CC4NE; + } + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -8186,10 +8244,10 @@ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c index 186beac392..220b847991 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c @@ -3302,10 +3302,10 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) @@ -3458,10 +3458,10 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c index 0281da35c2..3727cf0271 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c @@ -1014,75 +1014,76 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -3838,12 +3839,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3876,12 +3889,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c index e276ee185f..560dd357d7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -253,12 +253,11 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -323,19 +322,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -343,13 +342,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -939,17 +938,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c index f7dcc45345..f8869391f4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c @@ -135,6 +135,7 @@ [..] After the configuration, the OctoSPI/HSPI will be used as soon as an access on the AHB is done on the address range. HAL_XSPI_TimeOutCallback() will be called when the timeout expires. + HAL_XSPI_IsMemoryMapped() can be used to verify whether memory-mapped mode is configured or not. *** Errors management and abort functionality *** ================================================= @@ -234,7 +235,7 @@ (+) MspInitCallback : XSPI MspInit. (+) MspDeInitCallback : XSPI MspDeInit. [..] - This function) takes as parameters the HAL peripheral handle and the Callback ID. + This function takes as parameters the HAL peripheral handle and the Callback ID. [..] By default, after the HAL_XSPI_Init() and if the state is HAL_XSPI_STATE_RESET @@ -314,9 +315,9 @@ static void XSPI_DMAError(DMA_HandleTypeDef *hdma); static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd); #if defined(OCTOSPIM) -static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg); +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg); #endif /* OCTOSPIM */ /** @endcond @@ -853,7 +854,7 @@ void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t state; @@ -955,9 +956,10 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp if (pCmd->DataMode == HAL_XSPI_DATA_NONE) { /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + so wait until BUSY flag is reset to go back in idle state. */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + /* Clear TC flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); } else @@ -1017,7 +1019,7 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1138,7 +1140,7 @@ HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmd * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCfgTypeDef *pCfg, uint32_t Timeout) { HAL_StatusTypeDef status; @@ -1189,7 +1191,7 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusC * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCmdTypeDef *pCmd, uint32_t Timeout) { HAL_StatusTypeDef status; @@ -1354,7 +1356,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pD * @note This function is used only in Indirect Read Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1493,7 +1495,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t * @note This function is used only in Indirect Read Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t addr_reg = hxspi->Instance->AR; @@ -1748,7 +1750,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t * of data and the fifo threshold should be aligned on word * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t data_size = hxspi->Instance->DLR + 1U; @@ -1948,7 +1950,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const * @note This function is used only in Automatic Polling Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, uint32_t Timeout) { HAL_StatusTypeDef status; @@ -2029,7 +2031,7 @@ HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPolli * @note This function is used only in Automatic Polling Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -2102,7 +2104,7 @@ HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPo * @note This function is used only in Memory mapped Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -2148,6 +2150,29 @@ HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMa return status; } +/** + * @brief Check whether the XSPI is configured in Memory-mapped mode or not. + * @param hxspi : XSPI handle + * @retval Status (0: Memory-mapped disabled or XSPI not initialized, 1: Memory-mapped enabled) + */ +uint32_t HAL_XSPI_IsMemoryMapped(XSPI_HandleTypeDef *hxspi) +{ + /* Check the XSPI handle allocation */ + if (hxspi == NULL) + { + return (0UL); + } + /* Check if driver is in Reset state */ + else if (hxspi->State == HAL_XSPI_STATE_RESET) + { + return (0UL); + } + else + { + return ((READ_BIT(hxspi->Instance->CR, OCTOSPI_CR_FMODE) == OCTOSPI_CR_FMODE) ? 1UL : 0UL); + } +} + /** * @brief Transfer Error callback. * @param hxspi : XSPI handle @@ -2902,7 +2927,7 @@ uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; uint32_t instance; @@ -3165,7 +3190,7 @@ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTyp * @param pdlyb_cfg: Pointer to DLYB configuration structure. * @retval HAL status. */ -HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg) +HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, const HAL_XSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; @@ -3215,7 +3240,7 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DL * @param pdlyb_cfg: Pointer to DLYB configuration structure. * @retval HAL status. */ -HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg) +HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; @@ -3245,7 +3270,7 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DL * @param pdlyb_cfg: Pointer to DLYB configuration structure. * @retval HAL status. */ -HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *const pdlyb_cfg) +HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *pdlyb_cfg) { HAL_StatusTypeDef status = HAL_ERROR; @@ -3303,6 +3328,7 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XS * @} */ +#if defined(HSPI1) /** @defgroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions * @brief XSPI high-speed interface and calibration functions * @@ -3318,7 +3344,6 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XS @endverbatim * @{ */ -#if defined(HSPI1) /** * @brief Get the delay values of the high-speed interface DLLs. @@ -3326,7 +3351,7 @@ HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XS * @param pCfg : Current delay values corresponding to the DelayValueType field. * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *pCfg) { HAL_StatusTypeDef status = HAL_OK; __IO uint32_t reg = 0; @@ -3378,7 +3403,7 @@ HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTy * @param pCfg : Configuration of delay value specified in DelayValueType field. * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, const XSPI_HSCalTypeDef *pCfg) { HAL_StatusTypeDef status = HAL_OK; @@ -3427,10 +3452,10 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTy return status; } -#endif /* HSPI1 */ /** * @} */ +#endif /* HSPI1 */ /** @cond 0 @@ -3598,7 +3623,7 @@ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxsp * @param pCmd : structure that contains the command configuration information * @retval HAL status */ -static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) { HAL_StatusTypeDef status = HAL_OK; __IO uint32_t *ccr_reg; @@ -3745,6 +3770,12 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the AR register with the address value */ hxspi->Instance->AR = pCmd->Address; + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Verify if programmed address fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); + } } else { @@ -3804,6 +3835,12 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the AR register with the instruction value */ hxspi->Instance->AR = pCmd->Address; + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Verify if programmed address fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); + } } else { @@ -3813,6 +3850,18 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hxspi->Instance->DLR = (pCmd->DataLength - 1U); + + /* Verify if programmed data fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_DATA(hxspi->Instance->DLR, (pCmd->DataLength - 1U))); + } + } + return status; } @@ -3823,7 +3872,7 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC * @param pCfg : configuration of the IO Manager for the instance * @retval HAL status */ -static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg) +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg) { uint32_t reg; uint32_t value = 0U; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c index 1459562d11..7a5112e91c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c @@ -107,7 +107,7 @@ * - SUCCESS: the Delay value is set. * - ERROR: the Delay value is not set. */ -void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, const LL_DLYB_CfgTypeDef *pdlyb_cfg) { /* Check the DelayBlock instance */ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); @@ -130,7 +130,7 @@ void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) * - SUCCESS: the Delay value is received. * - ERROR: the Delay value is not received. */ -void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) +void LL_DLYB_GetDelay(const DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) { /* Check the DelayBlock instance */ assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c index 1ff6e2e7f2..08e1d51cad 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c @@ -837,7 +837,7 @@ void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) * LL_DMA_LinkNodeTypeDef parameters. * @retval None */ -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) { uint32_t reg_counter = 0U; @@ -875,6 +875,7 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); } + /* Check non 2D addressing settings */ if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE) { @@ -1061,7 +1062,6 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM reg_counter++; } - /* Update CTR3 register fields for 2D addressing channels */ if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c index 91b74d507e..1281f5d1b9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmc.c @@ -59,7 +59,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -176,7 +176,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -364,7 +364,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -394,7 +394,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FUL) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } @@ -415,7 +415,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -564,7 +564,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -597,7 +597,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -611,10 +611,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - Device->PMEM =(Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime )<< FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -628,7 +628,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -642,10 +642,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - Device->PATT =(Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -749,7 +749,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -789,7 +789,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui #endif /* FMC_BANK3 */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c index 1ffe57c1f6..5b2e594bb0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c @@ -33,6 +33,9 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** @@ -96,7 +99,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if (cfg.dma_enable == 1U) { - USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG &= ~(USB_OTG_GAHBCFG_HBSTLEN); + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_INCR4; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; } @@ -585,6 +589,7 @@ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) return speed; } +#if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint * @param USBx Selected device @@ -770,7 +775,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef if (ep->xfer_len == 0U) { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1UL << 19)); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else @@ -790,7 +795,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef ep->xfer_len = ep->maxpacket; } - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1UL << 19)); } else { @@ -816,7 +821,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U) { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } @@ -844,7 +849,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U) { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } @@ -877,14 +882,14 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef ep->xfer_size = ep->maxpacket; USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)); } else { if (ep->xfer_len == 0U) { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)); } else { @@ -906,7 +911,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U) { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; } @@ -929,11 +934,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t dma_enable = (USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) >> 0x5U; + uint32_t RegVal; /* IN endpoint */ if (ep->is_in == 1U) @@ -948,37 +955,145 @@ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy { count++; - if (count > 10000U) + if (count > 0xF0000U) { ret = HAL_ERROR; break; } - } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); } } else /* OUT endpoint */ { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + } + if (dma_enable == 0U) + { do { count++; - if (count > 10000U) + if (count > 0xF0000U) { ret = HAL_ERROR; break; } - } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } while (((USBx->GINTSTS & USB_OTG_GINTSTS_RXFLVL) & USB_OTG_GINTSTS_RXFLVL) != USB_OTG_GINTSTS_RXFLVL); + + /* POP the RX status register to generate the NAK Effective interrupt */ + RegVal = USBx->GRXSTSP; + UNUSED(RegVal); } + + /* Wait for Global NAK effective to be set */ + count = 0U; + + do + { + count++; + + if (count > 0xF0000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) + & USB_OTG_GINTSTS_BOUTNAKEFF) != USB_OTG_GINTSTS_BOUTNAKEFF); + + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + /* Wait for EP disable to take effect */ + count = 0U; + + do + { + count++; + + if (count > 0xF0000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_EPDISD) + & USB_OTG_DOEPINT_EPDISD) != USB_OTG_DOEPINT_EPDISD); + + /* Clear OUT EP disable interrupt */ + USBx_OUTEP(ep->num)->DOEPINT |= USB_OTG_DOEPINT_EPDISD; + + /* Clear Global OUT NAK */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; } return ret; } +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated @@ -1060,67 +1175,6 @@ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t return ((void *)pDest); } -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - /** * @brief USB_StopDevice : Stop the usb device mode * @param USBx Selected device @@ -1331,8 +1385,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { @@ -1380,7 +1434,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dm } USBx_OUTEP(0U)->DOEPTSIZ = 0U; - USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)); USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; @@ -1414,8 +1468,15 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + count = 10U; + + /* few cycles before setting core reset */ + while (count > 0U) + { + count--; + } + /* Core Soft Reset */ - count = 0U; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do @@ -1520,16 +1581,16 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x200U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); - USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100UL << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0UL << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); } else #endif /* defined (USB_OTG_HS) */ { /* set Rx FIFO size */ USBx->GRXFSIZ = 0x80U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); - USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60UL << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40UL << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); } /* Enable the common interrupts */ @@ -1635,13 +1696,13 @@ HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state } /** - * @brief Return Host Core speed + * @brief Return Host Port speed * @param USBx Selected device - * @retval speed : Host speed + * @retval speed : Host port device speed * This parameter can be one of these values: - * @arg HCD_SPEED_HIGH: High speed mode - * @arg HCD_SPEED_FULL: Full speed mode - * @arg HCD_SPEED_LOW: Low speed mode + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode */ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) { @@ -1664,6 +1725,7 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel * @param USBx Selected device @@ -1777,7 +1839,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, /* Program the HCCHAR register */ if ((epnum & 0x80U) == 0x80U) { - HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + HCcharEpDir = (0x1UL << 15) & USB_OTG_HCCHAR_EPDIR; } else { @@ -1789,7 +1851,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, /* LS device plugged to HUB */ if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) { - HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + HCcharLowSpeed = (0x1UL << 17) & USB_OTG_HCCHAR_LSDEV; } else { @@ -2123,7 +2185,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) { - if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + if ((USBx->HNPTXSTS & (0xFFUL << 16)) == 0U) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; @@ -2151,7 +2213,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + if ((USBx_HOST->HPTXSTS & (0xFFUL << 16)) == 0U) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; @@ -2174,6 +2236,34 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) return HAL_OK; } +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param ch_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir) +{ + UNUSED(ch_dir); + + __IO uint32_t tmpreg; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + + if ((tmpreg & USB_OTG_HCCHAR_CHDIS) == 0U) + { + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + + return HAL_OK; +} +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + /** * @brief Initiate Do Ping protocol * @param USBx Selected device @@ -2301,6 +2391,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) #if defined (USB_DRD_FS) static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); +#if defined (HAL_HCD_MODULE_ENABLED) #if (USE_USB_DOUBLE_BUFFER == 1U) static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc, @@ -2311,6 +2402,7 @@ static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc, uint32_t len); #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** * @brief Reset the USB Core (needed after USB clock settings change) @@ -3305,33 +3397,7 @@ uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) return USBx->FNR & 0x7FFU; } -/** - * @brief Set the channel Kind (Single/double buffer mode) - * @param USBx Selected device - * @param phy_ch_num Selected device - * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, - uint8_t phy_ch_num, uint8_t db_state) -{ - uint32_t tmp; - - if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) - { - tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; - } - else - { - tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; - } - - /* Set the device speed in case using HUB FS with device LS */ - USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); - - return HAL_OK; -} - +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel * @param USBx Selected device @@ -3399,7 +3465,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, USB_CHEP_KIND | USB_CHEP_ERRTX | USB_CHEP_ERRRX | - (0xFU << 27)); + (0xFUL << 27)); /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | @@ -3420,6 +3486,33 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, return ret; } +/** + * @brief Set the channel Kind (Single/double buffer mode) + * @param USBx Selected device + * @param phy_ch_num Selected device + * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, + uint8_t phy_ch_num, uint8_t db_state) +{ + uint32_t tmp; + + if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) + { + tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; + } + else + { + tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; + } + + /* Set the device speed in case using HUB FS with device LS */ + USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); + + return HAL_OK; +} + /** * @brief Start a transfer over a host channel * @param USBx Selected device @@ -3660,14 +3753,13 @@ static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, /** * @brief Halt a host channel in * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 + * @param phy_ch_num Host Channel number * @retval HAL state */ -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num) { /* Set disable to Channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS); + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_DIS); return HAL_OK; } @@ -3676,17 +3768,40 @@ HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) /** * @brief Halt a host channel out * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 + * @param phy_ch_num Host Channel number * @retval HAL state */ -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) +HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num) { /* Set disable to Channel */ - USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS); + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_DIS); + + return HAL_OK; +} + +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param phy_ch_num Host Channel number + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t ch_dir) +{ + if (ch_dir == CH_IN_DIR) + { + /* Enable TX host Channel */ + USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch_num, USB_CH_TX_VALID); + } + else + { + /* Enable RX host Channel */ + USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); + } return HAL_OK; } +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** * @brief Stop Host Core diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index d62333c761..456e403fc1 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -18,7 +18,7 @@ * STM32MP1: 1.7.0 * STM32U0: 1.2.0 * STM32U3: 1.1.0 - * STM32U5: 1.6.1 + * STM32U5: 1.6.2 * STM32WB: 1.14.5 * STM32WB0: 1.3.0 * STM32WBA: 1.5.0