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fpistmfpistm
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system(u5) update STM32U5xx HAL Drivers to v1.6.2
Included in STM32CubeU5 FW v1.8.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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69 files changed

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‎system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -538,6 +538,10 @@ extern "C" {
538538
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
539539
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
540540
#endif /* STM32H7 */
541+
#if defined(STM32H7RS)
542+
#define FLASH_OPTKEY1 FLASH_OPT_KEY1
543+
#define FLASH_OPTKEY2 FLASH_OPT_KEY2
544+
#endif /* STM32H7RS */
541545
#if defined(STM32U5)
542546
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
543547
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
@@ -560,6 +564,9 @@ extern "C" {
560564
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
561565
#define OB_nBOOT0_SET OB_NBOOT0_SET
562566
#endif /* STM32U0 */
567+
#if defined(STM32H5)
568+
#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1
569+
#endif /* STM32H5 */
563570

564571
/**
565572
* @}
@@ -1299,22 +1306,22 @@ extern "C" {
12991306
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
13001307
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
13011308

1302-
#if defined(STM32F7)
1309+
#if defined(STM32F7) || defined(STM32WB)
13031310
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
13041311
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1305-
#endif /* STM32F7 */
1312+
#endif /* STM32F7 || STM32WB */
13061313

13071314
#if defined(STM32H7)
13081315
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
13091316
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
13101317
#endif /* STM32H7 */
13111318

1312-
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
1319+
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB)
13131320
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
13141321
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
13151322
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
13161323
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1317-
#endif /* STM32F7 || STM32H7 || STM32L0 */
1324+
#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */
13181325

13191326
/**
13201327
* @}
@@ -1481,7 +1488,7 @@ extern "C" {
14811488
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
14821489
#endif
14831490

1484-
#if defined(STM32U5)
1491+
#if defined(STM32U5) || defined(STM32MP2)
14851492
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
14861493
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
14871494
#endif
@@ -3695,7 +3702,8 @@ extern "C" {
36953702
#endif
36963703

36973704
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3698-
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0)
3705+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3706+
defined(STM32U0)
36993707
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
37003708
#else
37013709
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3946,8 +3954,8 @@ extern "C" {
39463954
*/
39473955
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39483956
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3949-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \
3950-
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
3957+
defined (STM32WBA) || defined (STM32H5) || \
3958+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39513959
#else
39523960
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39533961
#endif

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -596,40 +596,40 @@ typedef struct
596596
* @brief DMAEx Private Constants
597597
* @{
598598
*/
599-
#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */
599+
#define DMA_LINKEDLIST (0x0080UL) /* DMA channel linked-list mode */
600600

601-
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */
602-
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */
603-
#define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */
604-
#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */
601+
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001UL) /* DMA channel linear addressing mode */
602+
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002UL) /* DMA channel 2D addressing mode */
603+
#define DMA_CHANNEL_TYPE_LPDMA (0x0010UL) /* LPDMA channel node */
604+
#define DMA_CHANNEL_TYPE_GPDMA (0x0020UL) /* GPDMA channel node */
605605

606-
#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */
607-
#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
608-
#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
606+
#define NODE_TYPE_MASK (0x00FFUL) /* DMA channel node type */
607+
#define NODE_CLLR_IDX (0x0700UL) /* DMA channel node CLLR index mask */
608+
#define NODE_CLLR_IDX_POS (0x0008UL) /* DMA channel node CLLR index position */
609609

610-
#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */
610+
#define NODE_MAXIMUM_SIZE (0x0008UL) /* Amount of registers of the node */
611611

612-
#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
613-
#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
612+
#define NODE_STATIC_FORMAT (0x0000UL) /* DMA channel node static format */
613+
#define NODE_DYNAMIC_FORMAT (0x0001UL) /* DMA channel node dynamic format */
614614

615-
#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */
616-
#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */
615+
#define UPDATE_CLLR_POSITION (0x0000UL) /* DMA channel update CLLR position */
616+
#define UPDATE_CLLR_VALUE (0x0001UL) /* DMA channel update CLLR value */
617617

618-
#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */
619-
#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */
618+
#define LASTNODE_ISNOT_CIRCULAR (0x0000UL) /* Last node is not first circular node */
619+
#define LASTNODE_IS_CIRCULAR (0x0001UL) /* Last node is first circular node */
620620

621-
#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
622-
#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
621+
#define QUEUE_TYPE_STATIC (0x0000UL) /* DMA channel static queue */
622+
#define QUEUE_TYPE_DYNAMIC (0x0001UL) /* DMA channel dynamic queue */
623623

624-
#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
625-
#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
626-
#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
627-
#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
628-
#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
629-
#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
630-
#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
631-
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
632-
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
624+
#define NODE_CTR1_DEFAULT_OFFSET (0x0000UL) /* CTR1 default offset */
625+
#define NODE_CTR2_DEFAULT_OFFSET (0x0001UL) /* CTR2 default offset */
626+
#define NODE_CBR1_DEFAULT_OFFSET (0x0002UL) /* CBR1 default offset */
627+
#define NODE_CSAR_DEFAULT_OFFSET (0x0003UL) /* CSAR default offset */
628+
#define NODE_CDAR_DEFAULT_OFFSET (0x0004UL) /* CDAR default offset */
629+
#define NODE_CTR3_DEFAULT_OFFSET (0x0005UL) /* CTR3 2D addressing default offset */
630+
#define NODE_CBR2_DEFAULT_OFFSET (0x0006UL) /* CBR2 2D addressing default offset */
631+
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007UL) /* CLLR 2D addressing default offset */
632+
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005UL) /* CLLR linear addressing default offset */
633633

634634
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
635635
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -201,19 +201,19 @@ typedef struct
201201
/**
202202
* @brief EXTI Line property definition
203203
*/
204-
#define EXTI_PROPERTY_SHIFT 24U
205-
#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT)
206-
#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT)
207-
#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
208-
#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT)
204+
#define EXTI_PROPERTY_SHIFT 24UL
205+
#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT)
206+
#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT)
207+
#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
208+
#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT)
209209
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
210210

211211
/**
212212
* @brief EXTI Register and bit usage
213213
*/
214-
#define EXTI_REG_SHIFT 16U
215-
#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT)
216-
#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT)
214+
#define EXTI_REG_SHIFT 16UL
215+
#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT)
216+
#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT)
217217
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
218218
#define EXTI_PIN_MASK 0x0000001FU
219219

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hcd.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,9 @@ typedef struct
134134
/** @defgroup HCD_Exported_Constants HCD Exported Constants
135135
* @{
136136
*/
137+
#ifndef HAL_HCD_CHANNEL_NAK_COUNT
138+
#define HAL_HCD_CHANNEL_NAK_COUNT 2U
139+
#endif /* HAL_HCD_CHANNEL_NAK_COUNT */
137140

138141
/** @defgroup HCD_Speed HCD Speed
139142
* @{
@@ -232,6 +235,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
232235
uint8_t speed, uint8_t ep_type, uint16_t mps);
233236

234237
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
238+
HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
235239
#if defined (USB_DRD_FS)
236240
HAL_StatusTypeDef HAL_HCD_HC_Close(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
237241
#endif /* defined (USB_DRD_FS) */

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -102,54 +102,54 @@ typedef struct
102102
#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */
103103
#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */
104104

105-
#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U))
105+
#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000UL))
106106
/*!< HW Trigger signal is GPDMA_CH0_TRG */
107-
#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
107+
#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
108108
/*!< HW Trigger signal is GPDMA_CH1_TRG */
109-
#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
109+
#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
110110
/*!< HW Trigger signal is GPDMA_CH2_TRG */
111-
#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
111+
#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
112112
/*!< HW Trigger signal is GPDMA_CH3_TRG */
113-
#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
113+
#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
114114
/*!< HW Trigger signal is EXTI5_TRG */
115-
#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
115+
#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
116116
/*!< HW Trigger signal is EXTI9_TRG */
117-
#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
117+
#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos))
118118
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
119-
#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
119+
#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos))
120120
/*!< HW Trigger signal is LPTIM2_CH1_TRG */
121-
#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
121+
#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos))
122122
/*!< HW Trigger signal is COMP1_TRG */
123-
#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
123+
#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos))
124124
/*!< HW Trigger signal is COMP2_TRG */
125-
#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
125+
#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos))
126126
/*!< HW Trigger signal is RTC_ALRA_TRG */
127-
#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
127+
#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos))
128128
/*!< HW Trigger signal is RTC_WUT_TRG */
129129

130-
#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U))
130+
#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000UL))
131131
/*!< HW Trigger signal is LPDMA_CH0_TRG */
132-
#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos))
132+
#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1UL << I2C_AUTOCR_TRIGSEL_Pos))
133133
/*!< HW Trigger signal is LPDMA_CH1_TRG */
134-
#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos))
134+
#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2UL << I2C_AUTOCR_TRIGSEL_Pos))
135135
/*!< HW Trigger signal is LPDMA_CH2_TRG */
136-
#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos))
136+
#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3UL << I2C_AUTOCR_TRIGSEL_Pos))
137137
/*!< HW Trigger signal is LPDMA_CH3_TRG */
138-
#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos))
138+
#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4UL << I2C_AUTOCR_TRIGSEL_Pos))
139139
/*!< HW Trigger signal is EXTI5_TRG */
140-
#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos))
140+
#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5UL << I2C_AUTOCR_TRIGSEL_Pos))
141141
/*!< HW Trigger signal is EXTI8_TRG */
142-
#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos))
142+
#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6UL << I2C_AUTOCR_TRIGSEL_Pos))
143143
/*!< HW Trigger signal is LPTIM1_CH1_TRG */
144-
#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos))
144+
#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7UL << I2C_AUTOCR_TRIGSEL_Pos))
145145
/*!< HW Trigger signal is LPTIM3_CH1_TRG */
146-
#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos))
146+
#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8UL << I2C_AUTOCR_TRIGSEL_Pos))
147147
/*!< HW Trigger signal is COMP1_TRG */
148-
#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos))
148+
#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9UL << I2C_AUTOCR_TRIGSEL_Pos))
149149
/*!< HW Trigger signal is COMP2_TRG */
150-
#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos))
150+
#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAUL << I2C_AUTOCR_TRIGSEL_Pos))
151151
/*!< HW Trigger signal is RTC_ALRA_TRG */
152-
#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos))
152+
#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBUL << I2C_AUTOCR_TRIGSEL_Pos))
153153
/*!< HW Trigger signal is RTC_WUT_TRG */
154154
/**
155155
* @}

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ typedef struct
7171
/** @defgroup ICACHE_WaysSelection Ways selection
7272
* @{
7373
*/
74-
#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
74+
#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */
7575
#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
7676
/**
7777
* @}
@@ -90,32 +90,32 @@ typedef struct
9090
/** @defgroup ICACHE_Region Remapped Region number
9191
* @{
9292
*/
93-
#define ICACHE_REGION_0 0U /*!< Region 0 */
94-
#define ICACHE_REGION_1 1U /*!< Region 1 */
95-
#define ICACHE_REGION_2 2U /*!< Region 2 */
96-
#define ICACHE_REGION_3 3U /*!< Region 3 */
93+
#define ICACHE_REGION_0 0UL /*!< Region 0 */
94+
#define ICACHE_REGION_1 1UL /*!< Region 1 */
95+
#define ICACHE_REGION_2 2UL /*!< Region 2 */
96+
#define ICACHE_REGION_3 3UL /*!< Region 3 */
9797
/**
9898
* @}
9999
*/
100100

101101
/** @defgroup ICACHE_Region_Size Remapped Region size
102102
* @{
103103
*/
104-
#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
105-
#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
106-
#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
107-
#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
108-
#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
109-
#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
110-
#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
104+
#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */
105+
#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */
106+
#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */
107+
#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */
108+
#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */
109+
#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */
110+
#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */
111111
/**
112112
* @}
113113
*/
114114

115115
/** @defgroup ICACHE_Traffic_Route Remapped Traffic route
116116
* @{
117117
*/
118-
#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */
118+
#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */
119119
#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
120120
/**
121121
* @}
@@ -124,7 +124,7 @@ typedef struct
124124
/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type
125125
* @{
126126
*/
127-
#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
127+
#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */
128128
#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
129129
/**
130130
* @}

‎system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_nand.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
194194
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
195195
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
196196

197-
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
197+
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig);
198198

199199
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
200200

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