From 0f394505612de4f8f8cdf79e5253615ebd99b1a5 Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Tue, 8 Jul 2025 08:36:41 +0200 Subject: [PATCH 1/4] fix whitespace in `aarch64.spec.yml` --- .../spec/neon/aarch64.spec.yml | 54 +++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index b4ddd46889..ca00e3cc83 100644 --- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -5383,7 +5383,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - *neon-fp16 + - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] safety: safe @@ -5436,7 +5436,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] - - *neon-fp16 + - *neon-fp16 - *neon-unstable-f16 static_defs: ["const LANE: i32"] safety: safe @@ -5460,7 +5460,7 @@ intrinsics: return_type: "{neon_type[0]}" attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx]]}]] - - *neon-fp16 + - *neon-fp16 - *neon-unstable-f16 safety: safe types: @@ -5544,7 +5544,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] return_type: "{neon_type[0]}" attr: - - *neon-fp16 + - *neon-fp16 - *neon-unstable-f16 assert_instr: [fmla] safety: safe @@ -12095,7 +12095,7 @@ intrinsics: - [uint8x8_t, 'uint8x8_t', 'b'] - [poly8x8_t, 'uint8x8_t', 'b'] compose: - - FnCall: + - FnCall: - 'vqtbl1{neon_type[0].no}' - - FnCall: - 'vcombine{neon_type[0].no}' @@ -12165,7 +12165,7 @@ intrinsics: - '{type[2]}_t' - - FnCall: ['vcombine{neon_type[1].no}', ['a.0', 'a.1']] - FnCall: ['vcombine{neon_type[1].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - - FnCall: + - FnCall: - transmute - - FnCall: - vqtbl2 @@ -12184,7 +12184,7 @@ intrinsics: types: - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + big_endian_inverse: true compose: - Let: - x @@ -12192,7 +12192,7 @@ intrinsics: - '{type[2]}_t' - - FnCall: ['vcombine{neon_type[3].no}', ['a.0', 'a.1']] - FnCall: ['vcombine{neon_type[3].no}', ['a.2', 'unsafe {{ crate::mem::zeroed() }}']] - - FnCall: + - FnCall: - transmute - - FnCall: - vqtbl2 @@ -12290,7 +12290,7 @@ intrinsics: - FnCall: [transmute, [b]] - c - Identifier: [x, Symbol] - + - name: "vtbx1{neon_type[0].no}" doc: "Extended table look-up" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] @@ -12312,7 +12312,7 @@ intrinsics: - FnCall: [transmute, ["{type[3]}"]] - FnCall: - transmute - - - FnCall: + - - FnCall: - "vqtbx1" - - "transmute(a)" - FnCall: @@ -12466,7 +12466,7 @@ intrinsics: - x - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[2]}' - - FnCall: [transmute, ['a']] - b @@ -12502,7 +12502,7 @@ intrinsics: compose: - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[2]}' - - FnCall: [transmute, ['a.0']] - FnCall: [transmute, ['a.1']] @@ -12538,7 +12538,7 @@ intrinsics: compose: - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[3]}' - - FnCall: [transmute, [a]] - FnCall: [transmute, ['b.0']] @@ -12575,7 +12575,7 @@ intrinsics: compose: - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[3]}' - - FnCall: [transmute, ['a.0']] - FnCall: [transmute, ['a.1']] @@ -12612,7 +12612,7 @@ intrinsics: compose: - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[3]}' - - FnCall: [transmute, [a]] - FnCall: [transmute, ['b.0']] @@ -12650,7 +12650,7 @@ intrinsics: compose: - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[2]}' - - FnCall: [transmute, ['a.0']] - FnCall: [transmute, ['a.1']] @@ -12688,7 +12688,7 @@ intrinsics: compose: - FnCall: - transmute - - - FnCall: + - - FnCall: - '{type[3]}' - - FnCall: [transmute, [a]] - FnCall: [transmute, ['b.0']] @@ -13195,7 +13195,7 @@ intrinsics: assert_instr: [addp] safety: safe types: - - [int32x2_t, i32] + - [int32x2_t, i32] compose: - LLVMLink: name: "vaddv{neon_type[0].no}" @@ -13250,7 +13250,7 @@ intrinsics: assert_instr: [addp] safety: safe types: - - [uint32x2_t, u32, i32] + - [uint32x2_t, u32, i32] compose: - LLVMLink: name: "vaddv{neon_type[0].no}" @@ -13326,7 +13326,7 @@ intrinsics: types: - [int8x8_t, i8, 'smaxv'] - [int16x4_t, i16, 'smaxv'] - - [int32x2_t, i32, 'smaxp'] + - [int32x2_t, i32, 'smaxp'] - [int8x16_t, i8, 'smaxv'] - [int16x8_t, i16, 'smaxv'] - [int32x4_t, i32, 'smaxv'] @@ -13348,7 +13348,7 @@ intrinsics: types: - [uint8x8_t, u8, 'umaxv'] - [uint16x4_t, u16, 'umaxv'] - - [uint32x2_t, u32, 'umaxp'] + - [uint32x2_t, u32, 'umaxp'] - [uint8x16_t, u8, 'umaxv'] - [uint16x8_t, u16, 'umaxv'] - [uint32x4_t, u32, 'umaxv'] @@ -13370,7 +13370,7 @@ intrinsics: types: - [float32x2_t, f32, 'fmaxp'] - [float32x4_t, f32, 'fmaxv'] - - [float64x2_t, f64, 'fmaxp'] + - [float64x2_t, f64, 'fmaxp'] compose: - LLVMLink: name: "vmaxv{neon_type[0].no}" @@ -13389,7 +13389,7 @@ intrinsics: types: - [int8x8_t, i8, 'sminv'] - [int16x4_t, i16, 'sminv'] - - [int32x2_t, i32, 'sminp'] + - [int32x2_t, i32, 'sminp'] - [int8x16_t, i8, 'sminv'] - [int16x8_t, i16, 'sminv'] - [int32x4_t, i32, 'sminv'] @@ -13411,7 +13411,7 @@ intrinsics: types: - [uint8x8_t, u8, 'uminv'] - [uint16x4_t, u16, 'uminv'] - - [uint32x2_t, u32, 'uminp'] + - [uint32x2_t, u32, 'uminp'] - [uint8x16_t, u8, 'uminv'] - [uint16x8_t, u16, 'uminv'] - [uint32x4_t, u32, 'uminv'] @@ -13433,7 +13433,7 @@ intrinsics: types: - [float32x2_t, f32, 'fminp'] - [float32x4_t, f32, 'fminv'] - - [float64x2_t, f64, 'fminp'] + - [float64x2_t, f64, 'fminp'] compose: - LLVMLink: name: "vminv{neon_type[0].no}" @@ -13489,7 +13489,7 @@ intrinsics: safety: safe types: - float32x4_t - - float64x2_t + - float64x2_t compose: - LLVMLink: name: "vpmin{neon_type.no}" @@ -13545,7 +13545,7 @@ intrinsics: safety: safe types: - float32x4_t - - float64x2_t + - float64x2_t compose: - LLVMLink: name: "vpmax{neon_type.no}" From 1c3b0ebb2f74f089bb98346a76fa8ee689efc628 Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Tue, 8 Jul 2025 08:41:09 +0200 Subject: [PATCH 2/4] remote intermediate assignment --- .../core_arch/src/aarch64/neon/generated.rs | 40 ++++--------------- .../spec/neon/aarch64.spec.yml | 34 +++++++--------- 2 files changed, 23 insertions(+), 51 deletions(-) diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index d5ff9ea554..c23dd1c8a1 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -19495,10 +19495,7 @@ pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t { #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { - unsafe { - let x = transmute(vqtbl1(transmute(a), b)); - x - } + unsafe { transmute(vqtbl1(transmute(a), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"] @@ -19507,10 +19504,7 @@ pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t { #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { - let x = transmute(vqtbl1q(transmute(a), b)); - x - } + unsafe { transmute(vqtbl1q(transmute(a), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"] @@ -19519,10 +19513,7 @@ pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { - unsafe { - let x = transmute(vqtbl1(transmute(a), b)); - x - } + unsafe { transmute(vqtbl1(transmute(a), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"] @@ -19531,10 +19522,7 @@ pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t { #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t { - unsafe { - let x = transmute(vqtbl1q(transmute(a), b)); - x - } + unsafe { transmute(vqtbl1q(transmute(a), b)) } } #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"] @@ -20397,10 +20385,7 @@ pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t { #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { - unsafe { - let x = transmute(vqtbx1(transmute(a), transmute(b), c)); - x - } + unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"] @@ -20409,10 +20394,7 @@ pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t { #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - unsafe { - let x = transmute(vqtbx1q(transmute(a), transmute(b), c)); - x - } + unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"] @@ -20421,10 +20403,7 @@ pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { - unsafe { - let x = transmute(vqtbx1(transmute(a), transmute(b), c)); - x - } + unsafe { transmute(vqtbx1(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"] @@ -20433,10 +20412,7 @@ pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t { #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t { - unsafe { - let x = transmute(vqtbx1q(transmute(a), transmute(b), c)); - x - } + unsafe { transmute(vqtbx1q(transmute(a), transmute(b), c)) } } #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"] diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index ca00e3cc83..b4b98f0924 100644 --- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -12279,17 +12279,15 @@ intrinsics: - [poly8x8_t, "poly8x16_t", uint8x8_t, "vqtbx1", "_p8"] - [uint8x16_t, "uint8x16_t", uint8x16_t, "vqtbx1q", "q_u8"] - [poly8x16_t, "poly8x16_t", uint8x16_t, "vqtbx1q", "q_p8"] + big_endian_inverse: false compose: - - Let: - - x - - FnCall: - - transmute - - - FnCall: - - "{type[3]}" - - - FnCall: [transmute, [a]] - - FnCall: [transmute, [b]] - - c - - Identifier: [x, Symbol] + - FnCall: + - transmute + - - FnCall: + - "{type[3]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + - c - name: "vtbx1{neon_type[0].no}" doc: "Extended table look-up" @@ -12461,16 +12459,14 @@ intrinsics: - ['poly8x16_t', uint8x8_t, 'vqtbl1', 'poly8x8_t'] - ['uint8x16_t', uint8x16_t, 'vqtbl1q', 'uint8x16_t'] - ['poly8x16_t', uint8x16_t, 'vqtbl1q', 'poly8x16_t'] + big_endian_inverse: false compose: - - Let: - - x - - FnCall: - - transmute - - - FnCall: - - '{type[2]}' - - - FnCall: [transmute, ['a']] - - b - - Identifier: [x, Symbol] + - FnCall: + - transmute + - - FnCall: + - '{type[2]}' + - - FnCall: [transmute, ['a']] + - b - name: "vqtbl2{neon_type[3].no}" doc: "Table look-up" From 9a41bdb03810ad96bb455cc92a985c9bc8e1dd7e Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Tue, 8 Jul 2025 08:45:56 +0200 Subject: [PATCH 3/4] shorten array literals --- .../src/arm_shared/neon/generated.rs | 104 +++--------------- .../spec/neon/arm_shared.spec.yml | 28 ++--- 2 files changed, 28 insertions(+), 104 deletions(-) diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs index 286f186885..4df1b74148 100644 --- a/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/crates/core_arch/src/arm_shared/neon/generated.rs @@ -40758,16 +40758,7 @@ pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")] fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; } - unsafe { - _vqshlu_n_s8( - a, - const { - int8x8_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) - } + unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] @@ -40783,17 +40774,7 @@ pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")] fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; } - unsafe { - _vqshluq_n_s8( - a, - const { - int8x16_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) - } + unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] @@ -40809,12 +40790,7 @@ pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")] fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; } - unsafe { - _vqshlu_n_s16( - a, - const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, - ) - } + unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] @@ -40830,16 +40806,7 @@ pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")] fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; } - unsafe { - _vqshluq_n_s16( - a, - const { - int16x8_t([ - N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, - ]) - }, - ) - } + unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] @@ -40855,7 +40822,7 @@ pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")] fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; } - unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) } + unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] @@ -40871,12 +40838,7 @@ pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")] fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; } - unsafe { - _vqshluq_n_s32( - a, - const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, - ) - } + unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] @@ -40908,7 +40870,7 @@ pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")] fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; } - unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) } + unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] @@ -40927,16 +40889,7 @@ pub fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { )] fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t; } - unsafe { - _vqshlu_n_s8( - a, - const { - int8x8_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) - } + unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] @@ -40955,17 +40908,7 @@ pub fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { )] fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t; } - unsafe { - _vqshluq_n_s8( - a, - const { - int8x16_t([ - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, - ]) - }, - ) - } + unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] @@ -40984,12 +40927,7 @@ pub fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { )] fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t; } - unsafe { - _vqshlu_n_s16( - a, - const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, - ) - } + unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] @@ -41008,16 +40946,7 @@ pub fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { )] fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t; } - unsafe { - _vqshluq_n_s16( - a, - const { - int16x8_t([ - N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, - ]) - }, - ) - } + unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] @@ -41036,7 +40965,7 @@ pub fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { )] fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t; } - unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) } + unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] @@ -41055,12 +40984,7 @@ pub fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { )] fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t; } - unsafe { - _vqshluq_n_s32( - a, - const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, - ) - } + unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) } } #[doc = "Signed saturating shift left unsigned"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] @@ -41098,7 +41022,7 @@ pub fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { )] fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t; } - unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) } + unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) } } #[doc = "Signed saturating shift right narrow"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 118f5808f7..07959cf380 100644 --- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -11447,14 +11447,14 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] - - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }'] - - [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N as i32, N as i32]) }'] + - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8; 8]) }'] + - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16; 4]) }'] + - [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N; 2]) }'] - [int64x1_t, uint64x1_t, '6', 'const { int64x1_t([N as i64]) }'] - - [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] - - [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }'] - - [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }'] - - [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64, N as i64]) }'] + - [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8; 16]) }'] + - [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16; 8]) }'] + - [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N; 4]) }'] + - [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64; 2]) }'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] - LLVMLink: @@ -11479,14 +11479,14 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] - - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }'] - - [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N as i32, N as i32]) }'] + - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8; 8]) }'] + - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16; 4]) }'] + - [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N; 2]) }'] - [int64x1_t, uint64x1_t, '6', 'const { int64x1_t([N as i64]) }'] - - [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] - - [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }'] - - [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }'] - - [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64, N as i64]) }'] + - [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8; 16]) }'] + - [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16; 8]) }'] + - [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N; 4]) }'] + - [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64; 2]) }'] compose: - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] - LLVMLink: From ed6e3f9399e4f2018470175f94ed3f14278d57c4 Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Tue, 8 Jul 2025 08:48:13 +0200 Subject: [PATCH 4/4] remove unneeded cast --- crates/core_arch/src/aarch64/neon/generated.rs | 4 ++-- crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index c23dd1c8a1..32f144bc7a 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -17158,7 +17158,7 @@ pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c)); - x as i64 + x } #[doc = "Signed saturating doubling multiply-subtract long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"] @@ -17324,7 +17324,7 @@ pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c)); - x as i64 + x } #[doc = "Vector saturating doubling multiply high by scalar"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"] diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index b4b98f0924..f0dce681d9 100644 --- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -7312,7 +7312,7 @@ intrinsics: - ["i64", "i32", "i32", "i64"] compose: - Let: [x, i64, {FnCall: [vqaddd_s64, [a, {FnCall: [vqdmulls_s32, [b, c]]}]]}] - - Identifier: ['x as i64', Symbol] + - Identifier: ['x', Symbol] - name: "vqdmlal{type[4]}" doc: "Signed saturating doubling multiply-add long" @@ -7426,7 +7426,7 @@ intrinsics: - ["i64", "i32", "i32", "i64"] compose: - Let: [x, i64, {FnCall: [vqsubd_s64, [a, {FnCall: [vqdmulls_s32, [b, c]]}]]}] - - Identifier: ['x as i64', Symbol] + - Identifier: ['x', Symbol] - name: "vqdmlsl{type[4]}" doc: "Signed saturating doubling multiply-subtract long"