From 9be0e62329a1f3437350731d99c16074fc932584 Mon Sep 17 00:00:00 2001 From: Kees Jongenburger Date: Wed, 30 Jan 2019 13:59:27 +0100 Subject: [PATCH] soc_core:allocate correct size for ROM. The wishbone and memory allocation code for ROM validated that the CPU reset address was witin the ROM address range. This however only really worked when the cpu_reset_address was 0. A second issue was that the size of the allocated memory mapping was wrongly calculated. Signed-off-by: Kees Jongenburger --- misoc/integration/soc_core.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py index 146ae988e..656db5ad0 100644 --- a/misoc/integration/soc_core.py +++ b/misoc/integration/soc_core.py @@ -135,9 +135,11 @@ def register_mem(self, name, origin, length, interface): def register_rom(self, interface, rom_size=0xa000): self.add_wb_slave(self.mem_map["rom"], rom_size, interface) - assert self.cpu_reset_address < rom_size - self.add_memory_region("rom", self.cpu_reset_address, - rom_size-self.cpu_reset_address) + if not self.mem_map["rom"] == self.cpu_reset_address: + raise ValueError( + "CPU reset address 0x{:x} is not equal to the rom start addres 0x{:x}" + .format(self.cpu_reset_address,self.mem_map["rom"])) + self.add_memory_region("rom", self.mem_map["rom"],rom_size) def get_memory_regions(self): return self._memory_regions