duc - Pipeline PhasedAccu for n>8 and allow non-log(2) values of n when n>8 #170
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Looks good to me, nice to see tests extended as well. |
Spaqin
approved these changes
Jul 17, 2025
| @@ -205,11 +205,13 @@ def __init__(self, width, constants): | |||
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| self.latency = 2 if n > 8 else 1 | |||
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Latency should be 0 for comb.
| @@ -223,11 +225,25 @@ def __init__(self, width, constants): | |||
| if n > 5: | |||
| ctx += o[5].eq(i + (i << 2)) | |||
| if n > 6: | |||
| ctx += o[6].eq(o[3] << 1) | |||
| ctx += o[6].eq((i << 2) + (i << 1)) | |||
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Does this actually make a difference?
| if n > 14: | ||
| ctx += o[14].eq((i << 3) + (i << 2) + (i << 1)) | ||
| if n > 15: | ||
| ctx += o[15].eq(i + (i << 3) + (i << 2) + (i << 1)) |
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Can the entire list be generated programmatically?
Also I'd have thought Vivado would do these optimizations already if you simply write *3, *4, *5, etc.
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Are these modifications compatible with https://github.com/quartiq/phaser ? |
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This patch was added with the Artiq EFC LTC2K variant in order to get timing closure for n>8. We also needed non-log(2) phases so that requirement is also lifted with the patch.