From 54bb2eb003da32b69d3cdd610e9f481e1d29f61c Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:16:54 +0100 Subject: [PATCH 1/7] Add core file for UHDM flow Signed-off-by: Rafal Kapuscik --- examples/fpga/artya7/top_artya7_surelog.core | 79 ++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 examples/fpga/artya7/top_artya7_surelog.core diff --git a/examples/fpga/artya7/top_artya7_surelog.core b/examples/fpga/artya7/top_artya7_surelog.core new file mode 100644 index 0000000000..c1dc0c1e65 --- /dev/null +++ b/examples/fpga/artya7/top_artya7_surelog.core @@ -0,0 +1,79 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:ibex:top_artya7_surelog:0.1" +description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)" +filesets: + files_rtl_artya7: + depend: + - lowrisc:ibex:ibex_top + - lowrisc:ibex:fpga_xilinx_shared + files: + - rtl/top_artya7.sv + file_type: systemVerilogSource + + files_constraints: + files: + - data/pins_artya7.xdc + file_type: xdc + + files_tcl: + files: + - util/vivado_setup_hooks.tcl : { file_type: tclSource } + - util/vivado_hook_write_bitstream_pre.tcl : { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl } + +parameters: + # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1 + # directory. It's best to pass it as absolute path when invoking fusesoc, e.g. + # --SRAMInitFile=$PWD/sw/led/led.vmem + # XXX: The VMEM file should be added to the sources of the Vivado project to + # make the Vivado dependency tracking work. However this requires changes to + # fusesoc first. + SRAMInitFile: + datatype: str + description: SRAM initialization file in vmem hex format + default: "../../../../../examples/sw/led/led.vmem" + paramtype: vlogparam + + # For value definition, please see ip/prim/rtl/prim_pkg.sv + PRIM_DEFAULT_IMPL: + datatype: str + paramtype: vlogdefine + description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric". + + FPGAPowerAnalysis: + datatype: int + paramtype: vlogparam + description: Enables custom power analysis scripts for Vivado. + +targets: + synth: + default_tool: vivado + filesets: + - files_rtl_artya7 + - files_constraints + toplevel: top_artya7 + parameters: + - SRAMInitFile + - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx + - FPGAPowerAnalysis + tools: + vivado: + part: "xc7a100tcsg324-1" # Default to Arty A7-100 + synth: "yosys" + yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"] + yosys_read_options: ['-noassert'] + surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS'] + yosys: + arch: "xilinx" + yosys_synth_options: ['-iopad', '-family xc7', '-run :check', "frontend=surelog"] + yosys_read_options: ['-noassert'] + surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS'] + symbiflow: + package: "csg324-1" + part: "xc7a35t" + pnr: "vtr" + vendor: "xilinx" + yosys_read_options: ['-noassert'] + surelog_options: ['--disable-feature=parametersubstitution', '-DSYNTHESIS'] From 285cf4e165ffb33c02306cfb9d3954e48c5b128d Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:17:18 +0100 Subject: [PATCH 2/7] Add workflow file for yosys synthesis Signed-off-by: Rafal Kapuscik --- .github/workflows/yosys_synth.yml | 58 +++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 .github/workflows/yosys_synth.yml diff --git a/.github/workflows/yosys_synth.yml b/.github/workflows/yosys_synth.yml new file mode 100644 index 0000000000..1f7d81fe1f --- /dev/null +++ b/.github/workflows/yosys_synth.yml @@ -0,0 +1,58 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: yosys-synthesis + +on: + push: + branches: + - master + pull_request: + +jobs: + yosys-uhdm-synthesis: + runs-on: ubuntu-latest + env: + CC: gcc-9 + CXX: g++-9 + steps: + - name: Install dependencies + run: | + apt-get update -qq + apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev uuid uuid-dev tcl-dev flex libfl-dev git python3-pip + update-alternatives --install /usr/bin/python python /usr/bin/python3 1 + update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 + + - uses: actions/checkout@v2 + with: + submodules: recursive + fetch-depth: 1 + + - uses: robinraju/release-downloader@v1.3 + with: + repository: "antmicro/yosys-uhdm-plugin-integration" + fileName: "yosys-uhdm-integration-*" + latest: true + tarBall: true + + - name: Extract yosys and UHDM plugin + steps: + tar -xzf yosys-uhdm-integration-*.tar.gz + echo "$GITHUB_WORKSPACE/image" >> $GITHUB_PATH + + + - name: Get memory file for Ibex + steps: + # TODO: Build it from source + wget https://raw.githubusercontent.com/antmicro/yosys-uhdm-plugin-integration/master/uhdm-tests/ibex/led.vmem + + - name: Build & Test + run: | + pip install -r python-requirements.txt + fusesoc --cores-root=. run --build --tool=yosys --target=synth lowrisc:ibex:top_artya7_surelog --SRAMInitFile=$GITHUB_WORKSPACE/led.vmem + + - uses: actions/upload-artifact@v2 + with: + name: lowrisc_ibex_top_artya7_surelog_0.1.edif + path: UHDM-integration-tests/build/lowrisc_ibex_top_artya7_surelog_0.1/synth-yosys/lowrisc_ibex_top_artya7_surelog_0.1.edif + From 35db45d5dee5a09f24ee52273019d19ca0d291a9 Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:22:30 +0100 Subject: [PATCH 3/7] [WIP] Use Antmicro Edalize fork Signed-off-by: Rafal Kapuscik --- python-requirements.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/python-requirements.txt b/python-requirements.txt index 6fa63fbd8e..2bdffa8ef6 100644 --- a/python-requirements.txt +++ b/python-requirements.txt @@ -3,7 +3,8 @@ # SPDX-License-Identifier: Apache-2.0 # Development version of edalize until all our changes are upstream -git+https://github.com/lowRISC/edalize.git@ot +# FIXME: Restore original fork after UHDM support is merged +git+https://github.com/antmicro/edalize.git@rk/ibex-uhdm-support # Development version with OT-specific changes git+https://github.com/lowRISC/fusesoc.git@ot From e236c3ce50263a1352b9eb39582f988c70bdf0af Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:31:52 +0100 Subject: [PATCH 4/7] Fix workflow syntax Signed-off-by: Rafal Kapuscik --- .github/workflows/yosys_synth.yml | 87 +++++++++++++++---------------- 1 file changed, 43 insertions(+), 44 deletions(-) diff --git a/.github/workflows/yosys_synth.yml b/.github/workflows/yosys_synth.yml index 1f7d81fe1f..ad84758b68 100644 --- a/.github/workflows/yosys_synth.yml +++ b/.github/workflows/yosys_synth.yml @@ -11,48 +11,47 @@ on: jobs: yosys-uhdm-synthesis: - runs-on: ubuntu-latest - env: - CC: gcc-9 - CXX: g++-9 - steps: - - name: Install dependencies - run: | - apt-get update -qq - apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev uuid uuid-dev tcl-dev flex libfl-dev git python3-pip - update-alternatives --install /usr/bin/python python /usr/bin/python3 1 - update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 - - - uses: actions/checkout@v2 - with: - submodules: recursive - fetch-depth: 1 - - - uses: robinraju/release-downloader@v1.3 - with: - repository: "antmicro/yosys-uhdm-plugin-integration" - fileName: "yosys-uhdm-integration-*" - latest: true - tarBall: true - - - name: Extract yosys and UHDM plugin + runs-on: ubuntu-latest + env: + CC: gcc-9 + CXX: g++-9 steps: - tar -xzf yosys-uhdm-integration-*.tar.gz - echo "$GITHUB_WORKSPACE/image" >> $GITHUB_PATH - - - - name: Get memory file for Ibex - steps: - # TODO: Build it from source - wget https://raw.githubusercontent.com/antmicro/yosys-uhdm-plugin-integration/master/uhdm-tests/ibex/led.vmem - - - name: Build & Test - run: | - pip install -r python-requirements.txt - fusesoc --cores-root=. run --build --tool=yosys --target=synth lowrisc:ibex:top_artya7_surelog --SRAMInitFile=$GITHUB_WORKSPACE/led.vmem - - - uses: actions/upload-artifact@v2 - with: - name: lowrisc_ibex_top_artya7_surelog_0.1.edif - path: UHDM-integration-tests/build/lowrisc_ibex_top_artya7_surelog_0.1/synth-yosys/lowrisc_ibex_top_artya7_surelog_0.1.edif - + - name: Install dependencies + run: | + apt-get update -qq + apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev uuid uuid-dev tcl-dev flex libfl-dev git python3-pip + update-alternatives --install /usr/bin/python python /usr/bin/python3 1 + update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 + + - uses: actions/checkout@v2 + with: + submodules: recursive + fetch-depth: 1 + + - uses: robinraju/release-downloader@v1.3 + with: + repository: "antmicro/yosys-uhdm-plugin-integration" + fileName: "yosys-uhdm-integration-*" + latest: true + tarBall: true + + - name: Extract yosys and UHDM plugin + run: | + tar -xzf yosys-uhdm-integration-*.tar.gz + echo "$GITHUB_WORKSPACE/image" >> $GITHUB_PATH + + + - name: Get memory file for Ibex + run: | + # TODO: Build it from source + wget https://raw.githubusercontent.com/antmicro/yosys-uhdm-plugin-integration/master/uhdm-tests/ibex/led.vmem + + - name: Build & Test + run: | + pip install -r python-requirements.txt + fusesoc --cores-root=. run --build --tool=yosys --target=synth lowrisc:ibex:top_artya7_surelog --SRAMInitFile=$GITHUB_WORKSPACE/led.vmem + + - uses: actions/upload-artifact@v2 + with: + name: lowrisc_ibex_top_artya7_surelog_0.1.edif + path: UHDM-integration-tests/build/lowrisc_ibex_top_artya7_surelog_0.1/synth-yosys/lowrisc_ibex_top_artya7_surelog_0.1.edif From a972ae399c27e9cf6f6028578c51049cf40ac0fc Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:42:48 +0100 Subject: [PATCH 5/7] [WIP] Disable other workflows for testing Signed-off-by: Rafal Kapuscik --- .github/workflows/pr_trigger.yml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.github/workflows/pr_trigger.yml b/.github/workflows/pr_trigger.yml index b969698b2c..35c6e74533 100644 --- a/.github/workflows/pr_trigger.yml +++ b/.github/workflows/pr_trigger.yml @@ -4,7 +4,10 @@ name: pr-trigger on: - pull_request: + # FIXME: Restore to all PRs + push: + branches: + - master jobs: upload: From 19a8e087462cf301919a2661b7685f75f828ecc5 Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:45:59 +0100 Subject: [PATCH 6/7] Fix apt calls in workflow Signed-off-by: Rafal Kapuscik --- .github/workflows/yosys_synth.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/yosys_synth.yml b/.github/workflows/yosys_synth.yml index ad84758b68..aa87a70ec5 100644 --- a/.github/workflows/yosys_synth.yml +++ b/.github/workflows/yosys_synth.yml @@ -18,10 +18,10 @@ jobs: steps: - name: Install dependencies run: | - apt-get update -qq - apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev uuid uuid-dev tcl-dev flex libfl-dev git python3-pip - update-alternatives --install /usr/bin/python python /usr/bin/python3 1 - update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 + sudo apt-get update -qq + sudo apt install -y g++-9 build-essential cmake tclsh ant default-jre swig google-perftools libgoogle-perftools-dev python3 python3-dev uuid uuid-dev tcl-dev flex libfl-dev git python3-pip + sudo update-alternatives --install /usr/bin/python python /usr/bin/python3 1 + sudo update-alternatives --install /usr/bin/pip pip /usr/bin/pip3 1 - uses: actions/checkout@v2 with: From 64eeb419d60a095209d87058a2e03ae190343e8a Mon Sep 17 00:00:00 2001 From: Rafal Kapuscik Date: Thu, 23 Dec 2021 10:56:58 +0100 Subject: [PATCH 7/7] Fix workflow Signed-off-by: Rafal Kapuscik --- .github/workflows/yosys_synth.yml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/.github/workflows/yosys_synth.yml b/.github/workflows/yosys_synth.yml index aa87a70ec5..9c0b9cef22 100644 --- a/.github/workflows/yosys_synth.yml +++ b/.github/workflows/yosys_synth.yml @@ -31,21 +31,25 @@ jobs: - uses: robinraju/release-downloader@v1.3 with: repository: "antmicro/yosys-uhdm-plugin-integration" - fileName: "yosys-uhdm-integration-*" + fileName: "*" latest: true tarBall: true - name: Extract yosys and UHDM plugin run: | tar -xzf yosys-uhdm-integration-*.tar.gz - echo "$GITHUB_WORKSPACE/image" >> $GITHUB_PATH - + echo "$GITHUB_WORKSPACE/image/bin" >> $GITHUB_PATH - name: Get memory file for Ibex run: | # TODO: Build it from source wget https://raw.githubusercontent.com/antmicro/yosys-uhdm-plugin-integration/master/uhdm-tests/ibex/led.vmem + - name: Display environment + run: | + ls -l + echo $PATH + - name: Build & Test run: | pip install -r python-requirements.txt @@ -54,4 +58,4 @@ jobs: - uses: actions/upload-artifact@v2 with: name: lowrisc_ibex_top_artya7_surelog_0.1.edif - path: UHDM-integration-tests/build/lowrisc_ibex_top_artya7_surelog_0.1/synth-yosys/lowrisc_ibex_top_artya7_surelog_0.1.edif + path: build/lowrisc_ibex_top_artya7_surelog_0.1/synth-yosys/lowrisc_ibex_top_artya7_surelog_0.1.edif