From f6757755644923831e1867e7183e737a7a7c68cd Mon Sep 17 00:00:00 2001
From: Rose <gfunni234@gmail.com>
Date: Wed, 9 Jul 2025 17:20:48 -0400
Subject: [PATCH 1/2] Pre-commit tests (NFC)

---
 llvm/test/CodeGen/X86/freeze-simplify.ll | 49 ++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/freeze-simplify.ll

diff --git a/llvm/test/CodeGen/X86/freeze-simplify.ll b/llvm/test/CodeGen/X86/freeze-simplify.ll
new file mode 100644
index 0000000000000..fc35a122ab201
--- /dev/null
+++ b/llvm/test/CodeGen/X86/freeze-simplify.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=X86ASM
+
+define i32 @sub_freeze(i32 %x, i32 %y) {
+; X86ASM-LABEL: sub_freeze:
+; X86ASM:       # %bb.0:
+; X86ASM-NEXT:    xorl %eax, %eax
+; X86ASM-NEXT:    retq
+  %a = udiv i32 %x, %y
+  %b = freeze i32 %a
+  %c = sub i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @sub_freeze_2(i32 %x, i32 %y) {
+; X86ASM-LABEL: sub_freeze_2:
+; X86ASM:       # %bb.0:
+; X86ASM-NEXT:    xorl %eax, %eax
+; X86ASM-NEXT:    retq
+  %a = add nuw i32 %x, %y
+  %b = freeze i32 %a
+  %c = sub i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @xor_freeze(i32 %x, i32 %y) {
+; X86ASM-LABEL: xor_freeze:
+; X86ASM:       # %bb.0:
+; X86ASM-NEXT:    movl %edi, %eax
+; X86ASM-NEXT:    xorl %edx, %edx
+; X86ASM-NEXT:    divl %esi
+; X86ASM-NEXT:    xorl %eax, %eax
+; X86ASM-NEXT:    retq
+  %a = udiv i32 %x, %y
+  %b = freeze i32 %a
+  %c = xor i32 %a, %b
+  ret i32 %c
+}
+
+define i32 @xor_freeze_2(i32 %x, i32 %y) {
+; X86ASM-LABEL: xor_freeze_2:
+; X86ASM:       # %bb.0:
+; X86ASM-NEXT:    xorl %eax, %eax
+; X86ASM-NEXT:    retq
+  %a = add nuw i32 %x, %y
+  %b = freeze i32 %a
+  %c = xor i32 %a, %b
+  ret i32 %c
+}

From 6c81196e73a8f419970a8a5f2fa63a3c68087dc2 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234@gmail.com>
Date: Wed, 9 Jul 2025 16:19:47 -0400
Subject: [PATCH 2/2] [SelectionDAG] Peek through freeze to see XOR

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 ++++++++-
 llvm/test/CodeGen/X86/freeze-simplify.ll      | 3 ---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 9ffdda28f7899..b10a6cc9a6678 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10016,8 +10016,15 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
     }
   }
 
+  auto PeekThroughFreeze = [](SDValue N) {
+    if (N->getOpcode() == ISD::FREEZE && N.hasOneUse())
+      return N->getOperand(0);
+    return N;
+  };
+
   // fold (xor x, x) -> 0
-  if (N0 == N1)
+  // FIXME: Refactor this and sub and other similar operations together.
+  if (PeekThroughFreeze(N0) == PeekThroughFreeze(N1))
     return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
 
   // fold (xor (shl 1, x), -1) -> (rotl ~1, x)
diff --git a/llvm/test/CodeGen/X86/freeze-simplify.ll b/llvm/test/CodeGen/X86/freeze-simplify.ll
index fc35a122ab201..02a1f03d1af5a 100644
--- a/llvm/test/CodeGen/X86/freeze-simplify.ll
+++ b/llvm/test/CodeGen/X86/freeze-simplify.ll
@@ -26,9 +26,6 @@ define i32 @sub_freeze_2(i32 %x, i32 %y) {
 define i32 @xor_freeze(i32 %x, i32 %y) {
 ; X86ASM-LABEL: xor_freeze:
 ; X86ASM:       # %bb.0:
-; X86ASM-NEXT:    movl %edi, %eax
-; X86ASM-NEXT:    xorl %edx, %edx
-; X86ASM-NEXT:    divl %esi
 ; X86ASM-NEXT:    xorl %eax, %eax
 ; X86ASM-NEXT:    retq
   %a = udiv i32 %x, %y