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[DAG] SelectionDAG::canCreateUndefOrPoison - Mark AVGFLOORS and AVGCEILS as safe
This patch updates `SelectionDAG::canCreateUndefOrPoison` to indicate that `ISD::AVGFLOORS` and `ISD::AVGCEILS` do not introduce poison or undef values. | Opcode | Operation Type | Alive2 Proof Link | |--------------|-------------------|--------------------| | `AVGFLOORS` | Signed Floor Avg | [Alive2 Link](https://alive2.llvm.org/ce/z/Dwy8a5) | | `AVGCEILS` | Signed Ceil Avg | [Alive2 Link](https://alive2.llvm.org/ce/z/_JKF8A) | | `AVGFLOORU` | Unsigned Floor Avg| [Alive2 Link](https://alive2.llvm.org/ce/z/2-B6RM) | | `AVGCEILU` | Unsigned Ceil Avg | [Alive2 Link](https://alive2.llvm.org/ce/z/t5WZ6K) | These patterns are safe due to the use of `sext i8` into `i32`, which ensures no signed overflow occurs. The arithmetic is done in the wider domain before truncating safely back to `i8`. Includes test coverage to ensure correctness.
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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

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@@ -5542,6 +5542,10 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
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case ISD::UADDSAT:
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case ISD::SSUBSAT:
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case ISD::USUBSAT:
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case ISD::AVGFLOORS:
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case ISD::AVGFLOORU:
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case ISD::AVGCEILS:
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case ISD::AVGCEILU:
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case ISD::MULHU:
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case ISD::MULHS:
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case ISD::SMIN:

‎llvm/test/CodeGen/AArch64/neon-hadd-freeze.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -march=arm64 -mattr=+neon | FileCheck %s
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; Test that the presence of 'freeze' does not block instruction selection of:
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; - uhadd
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; - urhadd
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; - shadd
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; - srhadd
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declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
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;===---------------------------------------------------------------------===;
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; Test: freeze does not block uhadd instruction selection
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;===---------------------------------------------------------------------===;
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define <8 x i16> @uhadd_freeze(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: uhadd_freeze:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.8h, #15
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: movi v2.8h, #31
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; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%m0 = and <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%m1 = and <8 x i16> %a1, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%avg = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
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%frozen = freeze <8 x i16> %avg
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%masked = and <8 x i16> %frozen, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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ret <8 x i16> %masked
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}
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;===---------------------------------------------------------------------===;
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; Test: freeze does not block urhadd instruction selection
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;===---------------------------------------------------------------------===;
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define <8 x i16> @urhadd_freeze(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: urhadd_freeze:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.8h, #15
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: movi v2.8h, #31
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; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%m0 = and <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%m1 = and <8 x i16> %a1, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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%avg = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
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%frozen = freeze <8 x i16> %avg
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%masked = and <8 x i16> %frozen, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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ret <8 x i16> %masked
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}
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;===---------------------------------------------------------------------===;
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; Test: freeze does not block shadd instruction selection
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;===---------------------------------------------------------------------===;
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define <8 x i16> @shadd_freeze(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: shadd_freeze:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.8h, #15
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; CHECK-NEXT: bic v1.8h, #15
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; CHECK-NEXT: movi v2.8h, #63
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; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%m0 = and <8 x i16> %a0, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16>
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%m1 = and <8 x i16> %a1, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16>
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%avg = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
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%frozen = freeze <8 x i16> %avg
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%masked = and <8 x i16> %frozen, <i16 63, i16 63, i16 63, i16 63, i16 63, i16 63, i16 63, i16 63>
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ret <8 x i16> %masked
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}
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;===---------------------------------------------------------------------===;
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; Test: freeze does not block srhadd instruction selection
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;===---------------------------------------------------------------------===;
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define <8 x i16> @srhadd_freeze(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: srhadd_freeze:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v0.8h, #15
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; CHECK-NEXT: bic v1.8h, #15
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; CHECK-NEXT: movi v2.8h, #63
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; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%m0 = and <8 x i16> %a0, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16>
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%m1 = and <8 x i16> %a1, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16>
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%avg = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)
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%frozen = freeze <8 x i16> %avg
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%masked = and <8 x i16> %frozen, <i16 63, i16 63, i16 63, i16 63, i16 63, i16 63, i16 63, i16 63>
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ret <8 x i16> %masked
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}

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