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[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. The extension includes only two instructions: one for converting from f32 to f16, and another for converting from f16 to f32. This patch only implements MC support for XAndesBFHCvt.
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -158,6 +158,7 @@
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// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
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// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
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// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
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// CHECK-NEXT: xandesbfhcvt 5.0 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)
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// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)
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// CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension)

‎clang/test/Preprocessor/riscv-target-features-andes.c

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@@ -4,6 +4,7 @@
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// RUN: -o - | FileCheck %s
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// CHECK-NOT: __riscv_xandesperf {{.*$}}
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// CHECK-NOT: __riscv_xandesbfhcvt {{.*$}}
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// CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}}
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// CHECK-NOT: __riscv_xandesvsintload {{.*$}}
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// CHECK-NOT: __riscv_xandesvpackfph {{.*$}}
@@ -17,6 +18,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESPERF %s
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// CHECK-XANDESPERF: __riscv_xandesperf 5000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32i_xandesbfhcvt -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESBFHCVT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64i_xandesbfhcvt -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESBFHCVT %s
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// CHECK-XANDESBFHCVT: __riscv_xandesbfhcvt 5000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32i_xandesvbfhcvt -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s

‎llvm/docs/RISCVUsage.rst

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@@ -516,6 +516,9 @@ The current vendor extensions supported are:
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``XAndesPerf``
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LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesBFHCvt``
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LLVM implements `version 5.0.0 of the Andes Scalar BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesVBFHCvt``
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LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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‎llvm/docs/ReleaseNotes.md

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@@ -214,6 +214,7 @@ Changes to the RISC-V Backend
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* `-mcpu=andes-ax45mpv` was added.
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* Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints.
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* Adds assembler support for the Andes `XAndesvsintload` (Andes Vector INT4 Load extension).
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* Adds assembler support for the Andes `XAndesbfhcvt` (Andes Scalar BFLOAT16 Conversion extension).
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -774,7 +774,8 @@ static constexpr FeatureBitset XTHeadGroup = {
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RISCV::FeatureVendorXTHeadVdot};
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static constexpr FeatureBitset XAndesGroup = {
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RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt,
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RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
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RISCV::FeatureVendorXAndesVBFHCvt,
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RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
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RISCV::FeatureVendorXAndesVDot};
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‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1599,6 +1599,14 @@ def HasVendorXAndesPerf
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AssemblerPredicate<(all_of FeatureVendorXAndesPerf),
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"'XAndesPerf' (Andes Performance Extension)">;
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def FeatureVendorXAndesBFHCvt
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: RISCVExtension<5, 0, "Andes Scalar BFLOAT16 Conversion Extension",
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[FeatureStdExtF]>;
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def HasVendorXAndesBFHCvt
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: Predicate<"Subtarget->hasVendorXAndesBFHCvt()">,
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AssemblerPredicate<(all_of FeatureVendorXAndesBFHCvt),
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"'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)">;
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def FeatureVendorXAndesVBFHCvt
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: RISCVExtension<5, 0, "Andes Vector BFLOAT16 Conversion Extension",
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[FeatureStdExtZve32f]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

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@@ -348,6 +348,17 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr>
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let mayStore = 1;
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}
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class NDSRVInstBFHCvt<bits<7> funct7, bits<5> rs1val, DAGOperand rdty,
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DAGOperand rs2ty, string opcodestr>
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: RVInstR<funct7, 0b100, OPC_CUSTOM_2, (outs rdty:$rd),
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(ins rs2ty:$rs2), opcodestr, "$rd, $rs2"> {
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let rs1 = rs1val;
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 0;
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let mayRaiseFPException = 1;
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}
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class NDSRVInstVFPMAD<bits<6> funct6, string opcodestr>
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: RVInst<(outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),
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opcodestr # "." # "vf", "$vd, $rs1, $vs2$vm", [], InstFormatR>,
@@ -630,6 +641,19 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">;
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def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;
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} // Predicates = [HasVendorXAndesPerf, IsRV64]
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//===----------------------------------------------------------------------===//
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// XAndesBFHCvt
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXAndesBFHCvt] in {
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def NDS_FCVT_S_BF16 : NDSRVInstBFHCvt<0b0000000, 0b00010,
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FPR32, FPR16, "nds.fcvt.s.bf16">,
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Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
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def NDS_FCVT_BF16_S : NDSRVInstBFHCvt<0b0000000, 0b00011,
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FPR16, FPR32, "nds.fcvt.bf16.s">,
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Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
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}
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//===----------------------------------------------------------------------===//
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// XAndesVBFHCvt
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -106,6 +106,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESBFHCVT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV32XANDESVSINTLOAD %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESBFHCVT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV64XANDESVSINTLOAD %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s
@@ -462,6 +464,7 @@
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p3"
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; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
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; RV32XANDESBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"
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; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
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; RV32XANDESVSINTLOAD: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0"
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; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
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; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
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; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
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; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
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; RV64XANDESBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0"
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; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
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; RV64XANDESVSINTLOAD: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0"
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; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"

‎llvm/test/CodeGen/RISCV/features-info.ll

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; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.
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; CHECK-NEXT: vl-dependent-latency - Latency of vector instructions is dependent on the dynamic value of vl.
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; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
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; CHECK-NEXT: xandesbfhcvt - 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension).
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; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension).
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; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).
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; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension).

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1129,6 +1129,7 @@ R"(All available -march extensions for RISC-V
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svnapot 1.0
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svpbmt 1.0
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svvptc 1.0
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xandesbfhcvt 5.0
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xandesperf 5.0
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xandesvbfhcvt 5.0
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xandesvdot 5.0

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