From 76467f2e056cc1b429cd4c2d762bb81996e104dd Mon Sep 17 00:00:00 2001 From: Hari Prasath Gujulan Elango Date: Wed, 14 May 2025 15:31:06 +0530 Subject: [PATCH 1/2] Makefile: Prepare 4.0.11-rc2 Signed-off-by: Hari Prasath Gujulan Elango --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b22a93cc..a87c8d6b 100644 --- a/Makefile +++ b/Makefile @@ -54,7 +54,7 @@ else BUILD_DATE := $(shell $(DATE) "$(DATE_FMT)") endif endif -export VERSION := v4.0.11-rc1 +export VERSION := v4.0.11-rc2 REVISION := ifdef NIX_SHELL SCMINFO := $(shell (host-utilities/setlocalversion)) From f18f0a926e167021a37a3380268a78689ad69647 Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Wed, 4 Jun 2025 11:09:38 +0200 Subject: [PATCH 2/2] device: sam9x60: add flexcom spi support Add image loading support from spi flash connnected to flexcom. Signed-off-by: Zixun LI --- device/sam9x60/Config.in.device | 6 +++ device/sam9x60/sam9x60.c | 66 +++++++++++++++++++++++++++++- device/sam9x60/sam9x60_board.h | 72 +++++++++++++++++++++++++++++++-- 3 files changed, 138 insertions(+), 6 deletions(-) diff --git a/device/sam9x60/Config.in.device b/device/sam9x60/Config.in.device index e0cc588d..acaebf76 100644 --- a/device/sam9x60/Config.in.device +++ b/device/sam9x60/Config.in.device @@ -14,6 +14,8 @@ config SAM9X60 select CPU_HAS_WDT2 select CPU_HAS_SCLK_BYPASS select CPU_HAS_AES + select CPU_HAS_SPI + select CPU_HAS_SPI_IOSET select CPU_HAS_FLEXCOM0 select CPU_HAS_FLEXCOM1 select CPU_HAS_FLEXCOM2 @@ -33,5 +35,9 @@ config SAM9X60 select ALLOW_CRYSTAL_24_000MHZ select SUPPORT_BUS_SPEED_200MHZ select CPU_HAS_XDMAC + select ALLOW_BOOT_FROM_DATAFLASH_CS0 + select ALLOW_BOOT_FROM_DATAFLASH_CS1 + select ALLOW_BOOT_FROM_DATAFLASH_CS2 + select ALLOW_BOOT_FROM_DATAFLASH_CS3 bool "SAM9X60" diff --git a/device/sam9x60/sam9x60.c b/device/sam9x60/sam9x60.c index a4b8a5ae..6b2e5bc8 100644 --- a/device/sam9x60/sam9x60.c +++ b/device/sam9x60/sam9x60.c @@ -41,7 +41,7 @@ __attribute__((weak)) void wilc_pwrseq(); #define FLEXCOM_USART_INDEX (CONFIG_CONSOLE_INDEX - 1) -#if defined(CONFIG_TWI) || CONFIG_CONSOLE_INDEX != 0 +#if defined(CONFIG_TWI) || CONFIG_CONSOLE_INDEX != 0 || defined(CONFIG_SPI) static struct at91_flexcom flexcoms[] = { {AT91C_ID_FLEXCOM0, FLEXCOM_TWI, AT91C_BASE_FLEXCOM0}, {AT91C_ID_FLEXCOM1, FLEXCOM_TWI, AT91C_BASE_FLEXCOM1}, @@ -279,6 +279,68 @@ void twi_init() } #endif +#if defined CONFIG_SPI +void at91_spi0_hw_init() +{ + const struct pio_desc flx_pins[][5] = { + { // FLEXCOM0 + {"FLX_IO0", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO1", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO2", AT91C_PIN_PA(4), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO3", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }, + { // FLEXCOM1 + {"FLX_IO0", AT91C_PIN_PA(5), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO1", AT91C_PIN_PA(6), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO2", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_C}, + {"FLX_IO3", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }, + { // FLEXCOM2 + {"FLX_IO0", AT91C_PIN_PA(7), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO1", AT91C_PIN_PA(8), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO2", AT91C_PIN_PB(2), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO3", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }, + { // FLEXCOM3 + {"FLX_IO0", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO1", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO2", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO3", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }, + { // FLEXCOM4 + {"FLX_IO0", AT91C_PIN_PA(12), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO1", AT91C_PIN_PA(11), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO2", AT91C_PIN_PA(13), 0, PIO_DEFAULT, PIO_PERIPH_A}, + {"FLX_IO3", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + }, + { // FLEXCOM5 + {"FLX_IO0", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO1", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO2", AT91C_PIN_PA(23), 0, PIO_DEFAULT, PIO_PERIPH_B}, + {"FLX_IO3", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT}, + {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, + } + }; + + if (CONFIG_CONSOLE_INDEX == CONFIG_SPI_BUS + 1) { + dbg_very_loud("\nFLEXCOM %d is used in UART mode, config to SPI mode ignored!\n\n", CONFIG_SPI_BUS); + return; + } + + pio_configure(flx_pins[CONFIG_SPI_BUS]); + + pmc_enable_periph_clock(flexcoms[CONFIG_SPI_BUS].id, PMC_PERIPH_CLK_DIVIDER_NA); + + flexcoms[CONFIG_SPI_BUS].mode = FLEXCOM_SPI; + flexcom_init(CONFIG_SPI_BUS); +} +#endif + void hw_init(void) { unsigned int reg; @@ -302,7 +364,7 @@ void hw_init(void) pmc_mck_cfg_set(0, BOARD_PRESCALER_PLLA, AT91C_PMC_PRES | AT91C_PMC_MDIV | AT91C_PMC_CSS); -#if defined(CONFIG_TWI) || CONFIG_CONSOLE_INDEX != 0 +#if defined(CONFIG_TWI) || CONFIG_CONSOLE_INDEX != 0 || defined(CONFIG_SPI) flexcoms_init(flexcoms); #endif diff --git a/device/sam9x60/sam9x60_board.h b/device/sam9x60/sam9x60_board.h index eef69eea..eb88e992 100644 --- a/device/sam9x60/sam9x60_board.h +++ b/device/sam9x60/sam9x60_board.h @@ -33,10 +33,74 @@ #define CONFIG_SYS_SPI_CLOCK AT91C_SPI_CLK #define CONFIG_SYS_SPI_MODE SPI_MODE0 -#if defined(CONFIG_SPI_BUS0) -#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI0 -#elif defined(CONFIG_SPI_BUS1) -#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI1 +#if defined(CONFIG_SPI) +#include "flexcom.h" +#define CONFIG_SYS_BASE_SPI flexcom_get_regmap(CONFIG_SPI_BUS) +#if CONFIG_SPI_BUS == 0 +#if defined(CONFIG_SPI_BOOT_CS0) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(3) +#elif defined(CONFIG_SPI_BOOT_CS1) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(2) +#else +#error "Invalid SPI chip select configuration!" +#endif +#elif CONFIG_SPI_BUS == 1 +#if defined(CONFIG_SPI_BOOT_CS0) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PC(28) +#elif defined(CONFIG_SPI_BOOT_CS1) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PC(27) +#else +#error "Invalid SPI chip select configuration!" +#endif +#elif CONFIG_SPI_BUS == 2 +#if defined(CONFIG_SPI_BOOT_CS0) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PB(1) +#elif defined(CONFIG_SPI_BOOT_CS1) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PB(0) +#else +#error "Invalid SPI chip select configuration!" +#endif +#elif CONFIG_SPI_BUS == 3 +#if defined(CONFIG_SPI_BOOT_CS0) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PC(25) +#elif defined(CONFIG_SPI_BOOT_CS1) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PC(24) +#else +#error "Invalid SPI chip select configuration!" +#endif +#elif CONFIG_SPI_BUS == 4 +#if defined(CONFIG_SPI_BOOT_CS0) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(14) +#elif defined(CONFIG_SPI_BOOT_CS1) && CONFIG_SPI_IOSET == 1 +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(7) +#elif defined(CONFIG_SPI_BOOT_CS1) && CONFIG_SPI_IOSET == 2 +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(0) +#elif defined(CONFIG_SPI_BOOT_CS2) && CONFIG_SPI_IOSET == 1 +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(1) +#elif defined(CONFIG_SPI_BOOT_CS2) && CONFIG_SPI_IOSET == 2 +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(8) +#elif defined(CONFIG_SPI_BOOT_CS3) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PB(3) +#else +#error "Invalid SPI chip select configuration!" +#endif +#elif CONFIG_SPI_BUS == 5 +#if defined(CONFIG_SPI_BOOT_CS0) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(8) +#elif defined(CONFIG_SPI_BOOT_CS1) && CONFIG_SPI_IOSET == 1 +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(0) +#elif defined(CONFIG_SPI_BOOT_CS1) && CONFIG_SPI_IOSET == 2 +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(7) +#elif defined(CONFIG_SPI_BOOT_CS2) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(31) +#elif defined(CONFIG_SPI_BOOT_CS3) +#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(30) +#else +#error "Invalid SPI chip select configuration!" +#endif +#else +#error "Invalid SPI bus configuration!" +#endif #endif #if defined(CONFIG_QSPI)