Skip to content

Commit 853301d

Browse files
author
Peter Kazanzides
committed
Reverted change from PR #34 (Dallas interface)
1 parent 6da0c36 commit 853301d

File tree

1 file changed

+15
-17
lines changed

1 file changed

+15
-17
lines changed

FPGA1394_QLA/Verilog/DS2505.v

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -154,24 +154,22 @@ reg[3:0] progCnt; // Program counter
154154
// next programmer state.
155155
// bits 25:21 -> current state indication
156156
// Programmer funtions:
157-
// 0 -> Calibrate baud rate
158-
// 1 -> 1-wire reset
159-
// 2 -> Enter DATA mode
160-
// 3 -> Skip ROM check
161-
// 4 -> Read memory command
162-
// 5 -> Memory read start addr, upper byte
163-
// 6 -> Memory read start addr, lower byte
164-
// 7 -> Enter CMD mode
165-
// 8 -> Flush & reset DS2480B, 1-wire reset
157+
// 0 -> Reset 1-wire in CMD mode
158+
// 1 -> Enter DATA mode
159+
// 2 -> Skip ROM check
160+
// 3 -> Read memory command
161+
// 4 -> Memory read start addr, upper byte
162+
// 5 -> Memory read start addr, lower byte
163+
// 6 -> Enter CMD mode
164+
// 7 -> Flush & reset DS2480B, 1-wire reset
166165
assign ds_program[0] = { DS_PROGRAMMER, DS_PROGRAMMER , 8'hC1, 8'h00 };
167-
assign ds_program[1] = { DS_READ_BYTE, DS_PROGRAMMER , 8'hC1, 8'h00 };
168-
assign ds_program[2] = { DS_PROGRAMMER, DS_PROGRAMMER , 8'hE1, 8'h00 };
169-
assign ds_program[3] = { DS_READ_BYTE , DS_TEST_FAMILY , 8'h33, 8'h33 };
170-
assign ds_program[4] = { DS_READ_BYTE , DS_PROGRAMMER , 8'hF0, 8'hF0 };
171-
assign ds_program[5] = { DS_READ_BYTE , DS_PROGRAMMER , mem_addr[7:0], mem_addr[7:0] };
172-
assign ds_program[6] = { DS_READ_BYTE , DS_READ_MEM_REQUEST, {5'd0, mem_addr[10:8]}, {5'd0, mem_addr[10:8]} };
173-
assign ds_program[7] = { DS_PROGRAMMER, DS_PROGRAMMER , 8'hE3, 8'h00 };
174-
assign ds_program[8] = { DS_IDLE , DS_IDLE , 8'hC1, 8'hCD };
166+
assign ds_program[1] = { DS_PROGRAMMER, DS_PROGRAMMER , 8'hE1, 8'h00 };
167+
assign ds_program[2] = { DS_READ_BYTE , DS_TEST_FAMILY , 8'h33, 8'h33 };
168+
assign ds_program[3] = { DS_READ_BYTE , DS_PROGRAMMER , 8'hF0, 8'hF0 };
169+
assign ds_program[4] = { DS_READ_BYTE , DS_PROGRAMMER , mem_addr[7:0], mem_addr[7:0] };
170+
assign ds_program[5] = { DS_READ_BYTE , DS_READ_MEM_REQUEST, {5'd0, mem_addr[10:8]}, {5'd0, mem_addr[10:8]} };
171+
assign ds_program[6] = { DS_PROGRAMMER, DS_PROGRAMMER , 8'hE3, 8'h00 };
172+
assign ds_program[7] = { DS_IDLE , DS_IDLE , 8'hC1, 8'hCD };
175173

176174
// UART instantiation
177175
wire recv_done; // recv data loading done flag

0 commit comments

Comments
 (0)