SPI Driver & I2C Patch for sun8i-h3/sun50i-h5

arch/arm/dts/sun8i-h3.dtsi

@@ -52,6 +52,8 @@
 
 	aliases {
 		ethernet0 = &emac;
+		spi0 = &spi0;
+		i2c0 = &i2c0;
 	};
 
 	cpus {
@@ -478,6 +480,22 @@
 			status = "disabled";
 		};
 
+		spi0: spi@01c68000 {
+			compatible = "allwinner,sun8i-h3-spi";
+			reg = <0x01c68000 0x1000>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c0: i2c@01c2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		gic: interrupt-controller@01c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,

arch/arm/include/asm/arch-sunxi/clock_sun6i.h

@@ -302,6 +302,9 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_DMA		6
 #define AHB_GATE_OFFSET_SS		5
 
+#define AHB_GATE_OFFSET_SPI0		20
+#define AHB_GATE_OFFSET_SPI1		21
+
 /* ahb_gate1 offsets */
 #define AHB_GATE_OFFSET_DRC0		25
 #define AHB_GATE_OFFSET_DE_FE0		14

arch/arm/include/asm/arch-sunxi/spi.h

@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
+ * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_SPI_H
+#define _SUNXI_SPI_H
+
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+	defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
+#include <asm/arch/spi_sun6i.h>
+#else
+#include <asm/arch/spi_sun4i.h>
+#endif
+
+#define SUNXI_SPI_BURST_CNT(cnt)	((cnt) & 0xffffff)
+#define SUNXI_SPI_XMIT_CNT(cnt)		((cnt) & 0xffffff)
+
+#define SUNXI_SPI_CLK_CTL_CDR2_MASK	0xff
+#define SUNXI_SPI_CLK_CTL_CDR2(div)	((div) & SUNXI_SPI_CLK_CTL_CDR2_MASK)
+#define SUNXI_SPI_CLK_CTL_CDR1_MASK	0xf
+#define SUNXI_SPI_CLK_CTL_CDR1(div)		\
+	(((div) & SUNXI_SPI_CLK_CTL_CDR1_MASK) << 8)
+#define SUNXI_SPI_CLK_CTL_DRS		BIT(12)
+
+#endif /* _SUNXI_SPI_H */

arch/arm/include/asm/arch-sunxi/spi_sun4i.h

@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
+ * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_SPI_SUN4I_H
+#define _SUNXI_SPI_SUN4I_H
+
+struct sunxi_spi_regs {
+	uint32_t rx_data;	/* 0x00 */
+	uint32_t tx_data;	/* 0x04 */
+	union {
+		uint32_t glb_ctl;
+		uint32_t xfer_ctl;
+		uint32_t fifo_ctl;
+		uint32_t burst_ctl;
+	};			/* 0x08 */
+	uint32_t int_ctl;	/* 0x0c */
+	uint32_t int_sta;	/* 0x10 */
+	uint32_t dma_ctl;	/* 0x14 */
+	uint32_t wait;		/* 0x18 */
+	uint32_t clk_ctl;	/* 0x1c */
+	uint32_t burst_cnt;	/* 0x20 */
+	uint32_t xmit_cnt;	/* 0x24 */
+	uint32_t fifo_sta;	/* 0x28 */
+};
+
+#define SUNXI_SPI_CTL_SRST		0
+
+#define SUNXI_SPI_CTL_ENABLE		BIT(0)
+#define SUNXI_SPI_CTL_MASTER		BIT(1)
+#define SUNXI_SPI_CTL_CPHA		BIT(2)
+#define SUNXI_SPI_CTL_CPOL		BIT(3)
+#define SUNXI_SPI_CTL_CS_ACTIVE_LOW	BIT(4)
+#define SUNXI_SPI_CTL_TF_RST		BIT(8)
+#define SUNXI_SPI_CTL_RF_RST		BIT(9)
+#define SUNXI_SPI_CTL_XCH		BIT(10)
+#define SUNXI_SPI_CTL_CS_MASK		0x3000
+#define SUNXI_SPI_CTL_CS(cs)		(((cs) << 12) & SUNXI_SPI_CTL_CS_MASK)
+#define SUNXI_SPI_CTL_DHB		BIT(15)
+#define SUNXI_SPI_CTL_CS_MANUAL		BIT(16)
+#define SUNXI_SPI_CTL_CS_LEVEL		BIT(17)
+#define SUNXI_SPI_CTL_TP		BIT(18)
+
+#define SUNXI_SPI_FIFO_RF_CNT_MASK	0x7f
+#define SUNXI_SPI_FIFO_RF_CNT_BITS	0
+#define SUNXI_SPI_FIFO_TF_CNT_MASK	0x7f
+#define SUNXI_SPI_FIFO_TF_CNT_BITS	16
+
+#endif /* _SUNXI_SPI_SUN4I_H */

arch/arm/include/asm/arch-sunxi/spi_sun6i.h

@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
+ * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
+ * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_SPI_SUN6I_H
+#define _SUNXI_SPI_SUN6I_H
+
+struct sunxi_spi_regs {
+	uint32_t unused0[1];
+	uint32_t glb_ctl;	/* 0x04 */
+	uint32_t xfer_ctl;	/* 0x08 */
+	uint32_t unused1[1];
+	uint32_t int_ctl;	/* 0x10 */
+	uint32_t int_sta;	/* 0x14 */
+	uint32_t fifo_ctl;	/* 0x18 */
+	uint32_t fifo_sta;	/* 0x1c */
+	uint32_t wait;		/* 0x20 */
+	uint32_t clk_ctl;	/* 0x24 */
+	uint32_t unused2[2];
+	uint32_t burst_cnt;	/* 0x30 */
+	uint32_t xmit_cnt;	/* 0x34 */
+	uint32_t burst_ctl;	/* 0x38 */
+	uint32_t unused3[113];
+	uint32_t tx_data;	/* 0x200 */
+	uint32_t unused4[63];
+	uint32_t rx_data;	/* 0x300 */
+};
+
+#define SUNXI_SPI_CTL_ENABLE		BIT(0)
+#define SUNXI_SPI_CTL_MASTER		BIT(1)
+#define SUNXI_SPI_CTL_TP		BIT(7)
+#define SUNXI_SPI_CTL_SRST		BIT(31)
+
+#define SUNXI_SPI_CTL_CPHA		BIT(0)
+#define SUNXI_SPI_CTL_CPOL		BIT(1)
+#define SUNXI_SPI_CTL_CS_ACTIVE_LOW	BIT(2)
+#define SUNXI_SPI_CTL_CS_MASK		0x30
+#define SUNXI_SPI_CTL_CS(cs)		(((cs) << 4) & SUNXI_SPI_CTL_CS_MASK)
+#define SUNXI_SPI_CTL_CS_MANUAL		BIT(6)
+#define SUNXI_SPI_CTL_CS_LEVEL		BIT(7)
+#define SUNXI_SPI_CTL_DHB		BIT(8)
+#define SUNXI_SPI_CTL_XCH		BIT(31)
+
+#define SUNXI_SPI_CTL_RF_RST		BIT(15)
+#define SUNXI_SPI_CTL_TF_RST		BIT(31)
+
+#define SUNXI_SPI_FIFO_RF_CNT_MASK	0x7f
+#define SUNXI_SPI_FIFO_RF_CNT_BITS	0
+#define SUNXI_SPI_FIFO_TF_CNT_MASK	0x7f
+#define SUNXI_SPI_FIFO_TF_CNT_BITS	16
+
+#endif /* _SUNXI_SPI_SUN6I_H */

board/sunxi/board.c

@@ -94,9 +94,15 @@ void i2c_init_board(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
 	clock_twi_onoff(0, 1);
 #elif defined(CONFIG_MACH_SUN8I)
+#ifndef CONFIG_MACH_SUNXI_H3_H5
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
 	clock_twi_onoff(0, 1);
+#else
+	sunxi_gpio_set_cfgpin(SUNXI_GPA(11), 2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPA(12), 2);
+	clock_twi_onoff(0, 1);
+#endif /* !CONFIG_MACH_SUNXI_H3_H5 */
 #endif
 #endif
 
@@ -116,9 +122,15 @@ void i2c_init_board(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
 	clock_twi_onoff(1, 1);
 #elif defined(CONFIG_MACH_SUN8I)
+#ifndef CONFIG_MACH_SUNXI_H3_H5
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
 	clock_twi_onoff(1, 1);
+#else
+	sunxi_gpio_set_cfgpin(SUNXI_GPA(18), 3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPA(19), 3);
+	clock_twi_onoff(1, 1);
+#endif /* !CONFIG_MACH_SUNXI_H3_H5 */
 #endif
 #endif
 

drivers/spi/Kconfig

@@ -132,6 +132,12 @@ config STM32_QSPI
 	  used to access the SPI NOR flash chips on platforms embedding
 	  this ST IP core.
 
+config SUNXI_SPI
+	bool "Allwinner SoCs SPI controller"
+	select DM_GPIO
+	help
+	  SPI driver for Allwinner sun4i, sun5i, sun6i, sun7i and sun8i SoCs
+
 config TEGRA114_SPI
 	bool "nVidia Tegra114 SPI driver"
 	help

drivers/spi/Makefile

@@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
 obj-$(CONFIG_SH_SPI) += sh_spi.o
 obj-$(CONFIG_SH_QSPI) += sh_qspi.o
 obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
+obj-$(CONFIG_SUNXI_SPI) += sunxi_spi.o
 obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
 obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
 obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o