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Verilog: consolidate code that computes width of given type #562

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Jun 19, 2024
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45 changes: 38 additions & 7 deletions src/verilog/verilog_typecheck_base.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -157,7 +157,7 @@ mp_integer verilog_typecheck_baset::array_offset(const array_typet &type)

/*******************************************************************\

Function: verilog_typecheck_baset::get_width
Function: verilog_typecheck_baset::get_width_opt

Inputs:

Expand All @@ -167,7 +167,8 @@ Function: verilog_typecheck_baset::get_width

\*******************************************************************/

mp_integer verilog_typecheck_baset::get_width(const typet &type)
std::optional<mp_integer>
verilog_typecheck_baset::get_width_opt(const typet &type)
{
if(type.id()==ID_bool)
return 1;
Expand All @@ -178,16 +179,24 @@ mp_integer verilog_typecheck_baset::get_width(const typet &type)

if(type.id()==ID_array)
{
mp_integer element_width = get_width(to_array_type(type).element_type());
return (array_size(to_array_type(type)) * element_width).to_ulong();
auto element_width = get_width_opt(to_array_type(type).element_type());
if(element_width.has_value())
return array_size(to_array_type(type)) * element_width.value();
else
return {};
}

if(type.id() == ID_struct)
{
// add them up
mp_integer sum = 0;
for(auto &component : to_struct_type(type).components())
sum += get_width(component.type());
{
auto component_width = get_width_opt(component.type());
if(!component_width.has_value())
return {};
sum += *component_width;
}
return sum;
}

Expand All @@ -202,8 +211,30 @@ mp_integer verilog_typecheck_baset::get_width(const typet &type)
else if(type.id() == ID_verilog_time)
return 64;

throw errort().with_location(type.source_location())
<< "type `" << type.id() << "' has unknown width";
return {};
}

/*******************************************************************\

Function: verilog_typecheck_baset::get_width

Inputs:

Outputs:

Purpose:

\*******************************************************************/

mp_integer verilog_typecheck_baset::get_width(const typet &type)
{
auto width_opt = get_width_opt(type);

if(width_opt.has_value())
return std::move(width_opt.value());
else
throw errort().with_location(type.source_location())
<< "type `" << type.id() << "' has unknown width";
}

/*******************************************************************\
Expand Down
12 changes: 7 additions & 5 deletions src/verilog/verilog_typecheck_base.h
Original file line number Diff line number Diff line change
Expand Up @@ -44,14 +44,16 @@ class verilog_typecheck_baset:public typecheckt
const namespacet &ns;
const irep_idt mode;

mp_integer get_width(const exprt &expr)
static mp_integer get_width(const exprt &expr)
{
return get_width(expr.type());
}
mp_integer get_width(const typet &type);
mp_integer array_size(const array_typet &);
mp_integer array_offset(const array_typet &);
typet index_type(const array_typet &);

static mp_integer get_width(const typet &);
static std::optional<mp_integer> get_width_opt(const typet &);
static mp_integer array_size(const array_typet &);
static mp_integer array_offset(const array_typet &);
static typet index_type(const array_typet &);
};

#endif
53 changes: 1 addition & 52 deletions src/verilog/verilog_typecheck_expr.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -434,7 +434,7 @@ Function: verilog_typecheck_exprt::bits

exprt verilog_typecheck_exprt::bits(const exprt &expr)
{
auto width_opt = bits_rec(expr.type());
auto width_opt = get_width_opt(expr.type());

if(!width_opt.has_value())
{
Expand All @@ -447,57 +447,6 @@ exprt verilog_typecheck_exprt::bits(const exprt &expr)

/*******************************************************************\

Function: verilog_typecheck_exprt::bits_rec

Inputs:

Outputs:

Purpose:

\*******************************************************************/

std::optional<mp_integer>
verilog_typecheck_exprt::bits_rec(const typet &type) const
{
if(type.id() == ID_bool)
return 1;
else if(type.id() == ID_unsignedbv)
return to_unsignedbv_type(type).get_width();
else if(type.id() == ID_signedbv)
return to_signedbv_type(type).get_width();
else if(type.id() == ID_integer)
return 32;
else if(type.id() == ID_array)
{
auto &array_type = to_array_type(type);
auto size_int =
numeric_cast_v<mp_integer>(to_constant_expr(array_type.size()));
auto element_bits_opt = bits_rec(array_type.element_type());
if(element_bits_opt.has_value())
return element_bits_opt.value() * size_int;
else
return {};
}
else if(type.id() == ID_struct)
{
auto &struct_type = to_struct_type(type);
mp_integer sum = 0;
for(auto &component : struct_type.components())
{
auto component_bits_opt = bits_rec(component.type());
if(!component_bits_opt.has_value())
return component_bits_opt.value();
sum += component_bits_opt.value();
}
return sum;
}
else
return {};
}

/*******************************************************************\

Function: verilog_typecheck_exprt::convert_system_function

Inputs:
Expand Down