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2 parents 0b3b4d7 + fb8e0b9 commit c516ad1Copy full SHA for c516ad1
.gitignore
@@ -1 +1,29 @@
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.DS_Store
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+
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+# generated files
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+src/smvlang/lex.yy.cpp
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+src/smvlang/smv_y.output
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+src/smvlang/smv_y.tab.cpp
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+src/smvlang/smv_y.tab.h
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+src/verilog/verilog_main_parser_lex.yy.cpp
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+src/verilog/verilog_preprocessor_lex.yy.cpp
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+src/verilog/verilog_y.output
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+src/verilog/verilog_y.tab.cpp
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+src/verilog/verilog_y.tab.h
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+src/vhdl/vhdl_y.tab.cpp
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+src/vhdl/vhdl_y.tab.h
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+# compiler outputs
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+src/**/*.a
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+src/**/*.d
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+src/**/*.o
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+src/ebmc/ebmc
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+src/hw-cbmc/hw-cbmc
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+src/vlindex/vlindex
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+unit/**/*.d
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+unit/**/*.o
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+unit/unit_tests
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+# test outputs
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+regression/**/*.log
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+regression/**/*.out
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