Initial upload existing code

src/FacultyDataset-idx/fwd/config.toml

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+dataset = "compiled_bios"
+corpus = "file.toml"
+prefix = "./data/"
+index = "FacultyDataset-idx"
+[[analyzers]]
+	method = "ngram-word"
+	ngram = 1
+	[[analyzers.filter]]
+		type = "icu-tokenizer"
+	[[analyzers.filter]]
+		type = "lowercase"
+[query-runner]
+	query-id-start = 0
+	query-path = "FacultyDataset-queries.txt"
+	timeout = 120

src/FacultyDataset-idx/fwd/corpus.uniqueterms

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+141119

src/FacultyDataset-idx/fwd/labelids.mapping

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+[None] 1

src/FacultyDataset-idx/inv/config.toml

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+corpus = "file.toml"
+dataset = "compiled_bios"
+prefix = "./data/"
+index = "FacultyDataset-idx"
+[[analyzers]]
+	method = "ngram-word"
+	ngram = 1
+	[[analyzers.filter]]
+		type = "icu-tokenizer"
+	[[analyzers.filter]]
+		type = "lowercase"
+[query-runner]
+	query-id-start = 0
+	query-path = "FacultyDataset-queries.txt"
+	timeout = 120

src/FacultyDataset-idx/inv/labelids.mapping

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+[None] 1

src/README.md

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+# ExpertSearch
+
+To run the code, run the following command from `ExpertSearch` (tested with Python2.7 on MacOS and Linux):
+
+`gunicorn server:app -b 127.0.0.1:8095` 
+
+The site should be available at http://localhost:8095/

src/config.json

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+{
+    "development": {
+        "rootpath": "./data/",
+        "datasetpath": "./data/compiled_bios/",
+        "searchconfig": "./data/compiled_bios/config.toml",
+        "unispath": "./data/filter_data/unis.json",
+        "locspath": "./data/filter_data/locs.json"
+    },
+    "production": {
+        "rootpath": "./data/",
+        "datasetpath": "./data/compiled_bios/",
+        "searchconfig": "./data/compiled_bios/config.toml"
+    }
+}

src/data/FacultyDataset/config.toml

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+index = "/Users/AaronGreen/Desktop/CS410/expertsearch/data/idx/FacultyDataset-idx"
+query-judgements = "/Users/AaronGreen/Desktop/CS410/expertsearch/data/FacultyDataset/FacultyDataset-qrels.txt"
+prefix = "/Users/AaronGreen/Desktop/CS410/expertsearch/data"
+corpus = "file.toml"
+dataset = "FacultyDataset"
+
+[query-runner]
+timeout = 120
+query-path = "/Users/AaronGreen/Desktop/CS410/expertsearch/data/FacultyDataset/FacultyDataset-queries.txt"
+query-id-start = 0
+
+[[analyzers]]
+ngram = 1
+method = "ngram-word"
+
+[[analyzers.filter]]
+type = "icu-tokenizer"
+
+[[analyzers.filter]]
+type = "lowercase"

src/data/FacultyDataset/dataset-full-corpus.txt

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+[None] doc1.txt
+[None] doc2.txt
+[None] doc3.txt
+[None] doc4.txt
+[None] doc5.txt

src/data/FacultyDataset/doc1.txt

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+doc 1 content
+here is another line
+one more line
+blah

src/data/FacultyDataset/doc2.txt

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+doc 2 content
+here is another line
+one more line
+blsh aarongg2@illinois.edu goob
+blah

src/data/FacultyDataset/doc3.txt

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+doc 3 content
+here is another line
+one more line
+blah

src/data/FacultyDataset/doc4.txt

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+doc 4 content
+here is another line
+one more line
+blah

src/data/FacultyDataset/doc5.txt

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+doc 5 content
+here is another line
+one more line
+blah

src/data/FacultyDataset/file.toml

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+type = "file-corpus"
+list = "dataset"

src/data/FacultyDataset/metadata.data

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+doc1.txt 1
+doc2.txt 2
+doc3.txt 3
+doc4.txt 4
+doc5.txt 5

src/data/compiled_bios/0.txt

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+ Tarek's Home Page Tarek F. Abdelzaher Professor and Willett Faculty Scholar Department of Computer Science University of Illinois at Urbana Champaign Urbana, IL 61801 Tel: (217) 265-6793 Fax: (217) 244-6500 I received my Ph.D. from the University of Michigan , Ann Arbor, in 1999, under Professor Kang Shin . I was an Asistant Professor at the University of Virginia from August 1999 to August 2005. I then joined the University of Illinois at Urbana Champaign as an Associate Professor with tenure, where I became Full Professor in 2011. My interests lie primarily in systems, including operating systems, networking, sensor networks, distributed systems, and embedded real-time systems. I am especially interested in developing theory, architectural support, and computing abstractions for predictability in software systems, motivated by the increasing software complexity and the growing sources of non-determinism. Applications range from sensor networks to large-scale server farms, and from transportation systems to medicine. New in Navigation: Green GPS . Brief Biosketch . Research: Cyber Physical Computing Group . Papers . Professional Activities . Teaching examples: Cyber-physical Systems , CS 423: Operating Systems , Web Architecture , Advanced Operating Systems , Computer Networks , Deeply Embedded Networks , E-mail: (last five letters of my last name) at cs dot uiuc dot edu. Thank you for visiting my webpage. 

src/data/compiled_bios/1.txt

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+ Sarita Adve University of Illinois at Urbana-Champaign Teaching Research Publications Students Contact Info for Students Fun Stuff Sarita V. Adve Richard T. Cheng Professor Department of Computer Science University of Illinois at Urbana-Champaign sadve@illinois.edu Sarita V. Adve is the Richard T. Cheng Professor of Computer Science at the University of Illinois at Urbana-Champaign . Her primary research interest is at the hardware-software interface with work spanning computer architecture, programming languages, operating systems, and applications. Her current research is on scalable system specialization and approximate computing. Sheco-developed the memory consistency models for the C++ and Java programming languages, which are based on her early work on data-race-free (DRF) models.More recently, her work questioned the conventional wisdom for memory models for heterogeneous systems and showed that DRF is a superior model even for such systems. She is also known for her contributions to cache coherence (she co-developed the simple and efficient DeNovo coherence protocol); hardware reliability (she co-developed software-driven approaches for hardware reliability in the SWAT project and the concept of lifetime reliability aware architectures and dynamic reliability management in the RAMP project); power management (she led the design of GRACE, one of the first systems to implement cross-layer energy management); exploiting instruction-level parallelism (ILP) for memory system performance (she co-authored some of the first papers on exploiting ILP for memory level parallelism); and evaluation techniques for shared-memory multiprocessors with ILP processors (she led the development of the RSIM architecture simulator). Professor Adve received the ACM/IEEE-CS Ken Kennedy award in 2018, was named a Woman of Vision in innovation by the Anita Borg Institute for Women in Technology in 2012, an IEEE fellow in 2012, an ACM fellow in 2010, received the ACM SIGARCH Maurice Wilkes award in 2008, an IBM faculty award in 2005, was named a UIUC University Scholar in 2004, received an Alfred P. Sloan Research Fellowship in 1998, an IBM University Partnership award in 1997 and 1998, and a National Science Foundation CAREER award in 1995. For three of the last five years (2014-18), Illinois CS has selected her students'PhD theses as one of the department's two nominations for the ACM doctoral dissertation award. She currently serves as the chair of ACM SIGARCH , on the DARPA/ISAT study group, and on ACM Council. She previously served on the board of directors of the Computing Research Association (CRA) (2009-18), on the National Science Foundation's CISE directorate's advisory committee (2003-05), on the expert group to revise the Java memory model (2001-05), and co-led the Intel/Microsoft funded Universal Parallel Computing Research Center (UPCRC) at Illinois as its director of research in its founding year (2008-09). Professor Adve was the first woman of South Asian origin to be named fellow of the ACMand, as a Maurice Wilkes awardee, the first woman to receive a young-, mid-, or life-career award in computer architecture research. She is deeply committed to increasing the number of women in computing by influencing change that can enable more women to be successful at all stages of thecareer pipeline. She received the Ph.D. and M.S. degrees in Computer Science from the University of Wisconsin - Madison in 1993 and 1989 respectively, and the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology - Bombay in 1987. Before joining Illinois, she was on the faculty at Rice University from 1993 to 1999. 

src/data/compiled_bios/10.txt

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+ Marco Caccamo's Home Page Marco Caccamo Professor Department of Computer Science University of Illinois Office: 4118 SC Siebel Center for Computer Science 201 N. Goodwin Avenue Urbana, IL 61801 Phone: 217-244-0528 Fax: 217-244-6500 mcaccamo "at" illinois.edu Marco Caccamo graduated (summa cum laude) in Computer Engineering at University of Pisa on July 1997. He received a Ph.D. in Computer Engineering from Scuola Superiore Sant'Anna ( SSSUP ) in January 2002. He is a professor in the Department of Computer Science, with courtesy appointments in the Department of Electrical and Computer Engineering and Department of Aerospace Engineering at the University of Illinois at Urbana-Champaign (UIUC). He is the Principal Investigator at the "Real Time and Embedded System Laboratory" at UIUC. In broad terms, his research interests are centered on the area of embedded systems. He has worked in close collaboration with avionics, farming, and automotive industries developing innovative software architectures and toolkits for the design automation of embedded digital controllers, and low-level resource management solutions for real-time operating systems running on multicore architectures. More recently, he has begun to investigate real-time, security, and robustness problems in the software architecture of unmanned aerial vehicles (UAVs). See recent article about this work and take a look at one of our UAV testbed ). Current Students: Fardin Abdi (Ph.D) Ayoosh Bansal (Ph.D) Or Dantsker (Ph.D) Mirco Theile (Ph.D) Rohan Tabish (Ph.D) Jayati Singh (visiting student) Honors & Awards: IEEE Fellow, "For contributions to the theory and applications of hard real-time multicore computing", 2018 Alexander von Humboldt Professorship , 2018 ( TUM ) Paper of the month and Editor's pick of the year 2016, IEEE Transactions on Computers Engineering Council Outstanding Advising Award (Spring 2015) Best Student Paper Award (RTAS 2013) Ranked as excellent teacher by students of CS598MC (Fall 2007, Spring 2012, Fall 2014) IEEE Tech. Committee on RT Systems Service Award (for serving as General Chair of CPSWeek 2011) Best Paper Award (RTCSA 2008) Best Student Paper Award (RTSS 2004) NSF CAREER Award (2003) Professional Activities: Member of 2018 IEEE Computer Society Fellows Committee, Chair of WiP session at RTEST'18 conference, Associate Editor of IEEE Transactions on Computers (TC), 2017-18, Co-chair of Second TCRTS Workshop on Certifiable Multicore Avionics and Automotive Systems (CMAAS'17) General Chair of IEEE Real-Time Systems Symposium (RTSS'16), Program Chair of IEEE Real-Time Systems Symposium (RTSS'15), General Chair of Cyber Physical Systems Week (CPSWeek) 2011, General Chair of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11), Program Chair of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'10), Chair of WiP session at ECRTS'08 conference. Publications Teaching: CS424 (Real-Time Systems) CS598mc (Special topics: Cyber-Physical Systems) CS431 (Embedded Systems Architecture and Software) CS241 (Systems Programming) Research Projects sponsored by NSF: Hybrid hardware-software architecture for reconfigurable real-time systems : m odern SoC devices enable the development of hybrid embedded systems where sofware tasks, running on a traditional CPU, can coexist with hardware tasks running on reconfigurable hardware (FPGA). The main goal of this research is to develop a SoC real-time computing architecture that integrates hardware and software execution in a transparent manner, and can support QoS adaptation by means of partial reconfiguration of modern FPGA devices. CSR: Memory-Centric Real-Time Scheduling for Multicore Embedded Systems . M. Caccamo (PI), Co-PI: L. Sha , National Science Foundation, CNS-1219064 In modern automotive and avionics applications, the use of multiple sensors and especially real-time imaging sensors creates unprecedented workloads. From a computational perspective, multicore architectures have become mainstream; however, as a multicore chip is expected to process increasing volumes of data in real-time, the memory hierarchy becomes the bottleneck resource. In the worst case, task execution times can grow linearly with the number of cores in the system. This research aims at laying foundations for a modern memory-centric real-time scheduling theory that can effectively co-schedule the use of the memory hierarchy, the cores, and the on-chip network, including the I/O channels. According to the vision of Memory-Centric Scheduling, when the memory hierarchy is the system bottleneck, memory accesses should be scheduled to achieve high memory utilization. Performance of a real-time multicore system should be measured in terms of schedulable memory utilization rather than just core utilization. Ideally, the real-time constraints should be met as long as total memory utilization of all real-time applications (across all the cores contending for shared memory) is below 100%. See the presentation titled " The Migration of Safety-Critical RT Software to Multicore " ( pptx ) for learning about major findings of this research. CSR: Multicore Real Time Virtual Partitions . L. Sha (PI), Co-PIs: M. Caccamo, T. Abdelzaher, National Science Foundation, CNS-1302563 Embedded industry has a large body of certified real time safety and mission critical software developed for single core chips, using certification procedures developed for single core systems. Now, those chips are becoming obsolete, and newer chips are being designed with slower clock rates but multiple cores. Multicore computer platforms pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory and I/O bandwidth. This research aims at tackling this industry-wide challenge by introducing the notion of real time virtual partitions (RTVPs), each of which can be treated as a stand-alone single-core chip from the point of view of real-time schedulability analysis and certification process. Without a technology like RTVP, the change of workload in one core could adversely impact the schedulability of tasks in other cores, triggering the recertification of applications running on other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the avionic industry. Single Core Equivalence (SCE): a cost-effective solution for the transition of safety-critical RT software from single-core to multi-core commodity platforms. CPS: Breakthrough: Solar-powered, Long-endurance UAV for Real-time Onboard Data Processing . M. Caccamo (PI), National Science Foundation, CNS-1646383 Given the wide range of possibilities, unmanned aerial vehicles (UAVs) represent a growing market in CPS and they are perceived as an "enabling technology" to re-consider the human involvement in many military and civil applications on a global scale. One of the major challenges in enabling this growth is UAV endurance. This is directly related to the amount of energy available to the UAV to perform its mission. This proposal looks to increase UAV endurance by trading off UAV performance with energy efficient computing. This requires mapping of mission and goals into energy needs and computational requirements. The goal of the project is to show that this trade can enable long-duration flight especially when solar energy is utilized as a primary energy source. The ambitious plan is to develop a light weight and efficient aircraft capable of maneuver-aware power adaptation and real-time video/sensor acquisition and processing for up to 12 hours of continuous flight (this limit being set by daylight hours). This project aims to expanding the theoretical and practical foundations for the design and integration of UAVs capable of real-time sensing and processing from an array of visual, acoustic and other sensors. For more details, please check the project web-site . Former Research Projects sponsored by NSF Former Students: Renato Mancuso (Ph.D'17, Assistant Professor at Boston Univ.) Suraj Venkat (MS'17) Andrew Louis (MS'17, Embedded Software Engineer at Bell) Stanley Bak (Ph.D'13, Research Scientist, Air Force Research Lab (AFRL), Rome, NY) Roman Dudko (MS'12, Google) Bach Duy Bui (Ph.D'11, SW Engineer at Yahoo!, UIUC Research Center) Rodolfo Pellizzoni (Ph.D'10, Associate Professor Univ. of Waterloo) Olugbemiga Adekunle (MS'10, Instructor at Blue Ridge Community College, VA) Deepti K. Chivukula (MS'10, Associate, Firm Risk Management @ Morgan Stanley) Chin F. Cheah (MS'07, Citadel Investment Group) Sathish Gopalakrishnan ( Ph.D'05, Associate Professor UBC) Spencer Hoke (MS'05, Garmin) Deepu C. Thomas (MS'04, Microsoft) Simone Giannecchini (MS'03, Geosolutions, Italy) accesses since June 2005 

src/data/compiled_bios/100.txt

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+Boris Kozinsky works at the intersection of fundamental physics of materials properties, efficient computational algorithms, and data-intensive informatics approaches. The overall vision is to leverage the rapidly expanding power of computation and data science to accelerate discovery and design of new practical materials needed for breakthroughs in energy storage and conversion systems. Performance of these systems is controlled by atomic-scale transport and reaction mechanisms and their coupling at different length and time scales that are difficult to probe by experiment alone. Atomistic and electronic structure computations are emerging as a powerful tool for understanding and distilling the design rules governing quantum-level microscopic effects.Boris Kozinsky studied at MIT for his B.S. degrees in Physics, Mathematics, and Electrical Engineering and Computer Science, and received his PhD degree in Physics also from MIT in 2007. He then established and led the atomistic computational materials science team at Bosch Research in Cambridge MA, working closely together with leading academic and industrial groups. Leveraging over a decade of experience in industrial application-driven research, Boris Kozinsky emphasizes technological relevance and rapid screening methods for high performance materials and devices, in close collaboration with experiments. His work on development and application of computational methods led to advances and inventions in a wide range of materials systems, including 1D and 2D materials, piezoelectrics, thermoelectrics, batteries, super-ionic conductors, catalysts, and functional polymers.Current work is focused on:Design and discovery of materials for next-generation batteries, fuel cells and sensors using computations of electronic structure of correlated oxides, electrochemical activity and stability, and ionic conductivity of cathodes and solid electrolytes.Development of accurate and efficient computational methods by combining first-principles quantum calculations with multiscale analytical models of transport, lifetimes and coupling of electronic, thermal and ionic carriers.Machine learning approaches for accelerated materials discovery by identifying structure-property relationships and computable descriptors of complex materials properties, and by enhancing accuracy and efficiency of computational methods.Database-driven cloud infrastructure for intelligent automation of computational workflows, enabling exascale data generation, reusability and analytics.http://bkoz.seas.harvard.edu